fsl_espi.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * eSPI controller driver.
  4. *
  5. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  6. * Copyright 2020 NXP
  7. * Author: Mingkai Hu (Mingkai.hu@freescale.com)
  8. * Chuanhua Han (chuanhua.han@nxp.com)
  9. */
  10. #include <common.h>
  11. #include <log.h>
  12. #include <linux/bitops.h>
  13. #include <linux/delay.h>
  14. #include <malloc.h>
  15. #include <spi.h>
  16. #include <asm/immap_85xx.h>
  17. #include <dm.h>
  18. #include <errno.h>
  19. #include <fdtdec.h>
  20. #include <dm/platform_data/fsl_espi.h>
  21. struct fsl_spi_slave {
  22. struct spi_slave slave;
  23. ccsr_espi_t *espi;
  24. u32 speed_hz;
  25. unsigned int cs;
  26. unsigned int div16;
  27. unsigned int pm;
  28. int tx_timeout;
  29. unsigned int mode;
  30. size_t cmd_len;
  31. u8 cmd_buf[16];
  32. size_t data_len;
  33. unsigned int max_transfer_length;
  34. };
  35. #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
  36. #define US_PER_SECOND 1000000UL
  37. /* default SCK frequency, unit: HZ */
  38. #define FSL_ESPI_DEFAULT_SCK_FREQ 10000000
  39. #define ESPI_MAX_CS_NUM 4
  40. #define ESPI_FIFO_WIDTH_BIT 32
  41. #define ESPI_EV_RNE BIT(9)
  42. #define ESPI_EV_TNF BIT(8)
  43. #define ESPI_EV_DON BIT(14)
  44. #define ESPI_EV_TXE BIT(15)
  45. #define ESPI_EV_RFCNT_SHIFT 24
  46. #define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT)
  47. #define ESPI_MODE_EN BIT(31) /* Enable interface */
  48. #define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */
  49. #define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */
  50. #define ESPI_COM_CS(x) ((x) << 30)
  51. #define ESPI_COM_TRANLEN(x) ((x) << 0)
  52. #define ESPI_CSMODE_CI_INACTIVEHIGH BIT(31)
  53. #define ESPI_CSMODE_CP_BEGIN_EDGCLK BIT(30)
  54. #define ESPI_CSMODE_REV_MSB_FIRST BIT(29)
  55. #define ESPI_CSMODE_DIV16 BIT(28)
  56. #define ESPI_CSMODE_PM(x) ((x) << 24)
  57. #define ESPI_CSMODE_POL_ASSERTED_LOW BIT(20)
  58. #define ESPI_CSMODE_LEN(x) ((x) << 16)
  59. #define ESPI_CSMODE_CSBEF(x) ((x) << 12)
  60. #define ESPI_CSMODE_CSAFT(x) ((x) << 8)
  61. #define ESPI_CSMODE_CSCG(x) ((x) << 3)
  62. #define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \
  63. ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
  64. ESPI_CSMODE_CSCG(1))
  65. #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
  66. void fsl_spi_cs_activate(struct spi_slave *slave, uint cs)
  67. {
  68. struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
  69. ccsr_espi_t *espi = fsl->espi;
  70. unsigned int com = 0;
  71. size_t data_len = fsl->data_len;
  72. com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
  73. com |= ESPI_COM_CS(cs);
  74. com |= ESPI_COM_TRANLEN(data_len - 1);
  75. out_be32(&espi->com, com);
  76. }
  77. void fsl_spi_cs_deactivate(struct spi_slave *slave)
  78. {
  79. struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
  80. ccsr_espi_t *espi = fsl->espi;
  81. /* clear the RXCNT and TXCNT */
  82. out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
  83. out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
  84. }
  85. static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
  86. {
  87. ccsr_espi_t *espi = fsl->espi;
  88. unsigned int tmpdout, event;
  89. int tmp_tx_timeout;
  90. if (dout)
  91. tmpdout = *(u32 *)dout;
  92. else
  93. tmpdout = 0;
  94. out_be32(&espi->tx, tmpdout);
  95. out_be32(&espi->event, ESPI_EV_TNF);
  96. debug("***spi_xfer:...%08x written\n", tmpdout);
  97. tmp_tx_timeout = fsl->tx_timeout;
  98. /* Wait for eSPI transmit to go out */
  99. while (tmp_tx_timeout--) {
  100. event = in_be32(&espi->event);
  101. if (event & ESPI_EV_DON || event & ESPI_EV_TXE) {
  102. out_be32(&espi->event, ESPI_EV_TXE);
  103. break;
  104. }
  105. udelay(1);
  106. }
  107. if (tmp_tx_timeout < 0)
  108. debug("***spi_xfer:...Tx timeout! event = %08x\n", event);
  109. }
  110. static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
  111. unsigned int bytes)
  112. {
  113. ccsr_espi_t *espi = fsl->espi;
  114. unsigned int tmpdin, rx_times;
  115. unsigned char *buf, *p_cursor;
  116. if (bytes <= 0)
  117. return 0;
  118. rx_times = DIV_ROUND_UP(bytes, 4);
  119. buf = (unsigned char *)malloc(4 * rx_times);
  120. if (!buf) {
  121. debug("SF: Failed to malloc memory.\n");
  122. return -1;
  123. }
  124. p_cursor = buf;
  125. while (rx_times--) {
  126. tmpdin = in_be32(&espi->rx);
  127. debug("***spi_xfer:...%08x readed\n", tmpdin);
  128. *(u32 *)p_cursor = tmpdin;
  129. p_cursor += 4;
  130. }
  131. if (din)
  132. memcpy(din, buf, bytes);
  133. free(buf);
  134. out_be32(&espi->event, ESPI_EV_RNE);
  135. return bytes;
  136. }
  137. void espi_release_bus(struct fsl_spi_slave *fsl)
  138. {
  139. /* Disable the SPI hardware */
  140. out_be32(&fsl->espi->mode,
  141. in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN));
  142. }
  143. int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen,
  144. const void *data_out, void *data_in, unsigned long flags)
  145. {
  146. struct spi_slave *slave = &fsl->slave;
  147. ccsr_espi_t *espi = fsl->espi;
  148. unsigned int event, rx_bytes;
  149. const void *dout = NULL;
  150. void *din = NULL;
  151. int len = 0;
  152. int num_blks, num_chunks, max_tran_len, tran_len;
  153. int num_bytes;
  154. unsigned char *buffer = NULL;
  155. size_t buf_len;
  156. u8 *cmd_buf = fsl->cmd_buf;
  157. size_t cmd_len = fsl->cmd_len;
  158. size_t data_len = bitlen / 8;
  159. size_t rx_offset = 0;
  160. int rf_cnt;
  161. max_tran_len = fsl->max_transfer_length;
  162. switch (flags) {
  163. case SPI_XFER_BEGIN:
  164. cmd_len = data_len;
  165. fsl->cmd_len = cmd_len;
  166. memcpy(cmd_buf, data_out, cmd_len);
  167. return 0;
  168. case 0:
  169. case SPI_XFER_END:
  170. if (bitlen == 0) {
  171. fsl_spi_cs_deactivate(slave);
  172. return 0;
  173. }
  174. buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len);
  175. len = cmd_len + data_len;
  176. rx_offset = cmd_len;
  177. buffer = (unsigned char *)malloc(buf_len);
  178. if (!buffer) {
  179. debug("SF: Failed to malloc memory.\n");
  180. return 1;
  181. }
  182. memcpy(buffer, cmd_buf, cmd_len);
  183. if (data_in == NULL)
  184. memcpy(buffer + cmd_len, data_out, data_len);
  185. break;
  186. case SPI_XFER_BEGIN | SPI_XFER_END:
  187. len = data_len;
  188. buffer = (unsigned char *)malloc(len * 2);
  189. if (!buffer) {
  190. debug("SF: Failed to malloc memory.\n");
  191. return 1;
  192. }
  193. memcpy(buffer, data_out, len);
  194. rx_offset = len;
  195. cmd_len = 0;
  196. break;
  197. }
  198. debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) len %u\n",
  199. *(uint *)data_out, data_out, *(uint *)data_in, data_in, len);
  200. num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
  201. while (num_chunks--) {
  202. if (data_in)
  203. din = buffer + rx_offset;
  204. dout = buffer;
  205. tran_len = min(data_len, (size_t)max_tran_len);
  206. num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
  207. num_bytes = (tran_len + cmd_len) % 4;
  208. fsl->data_len = tran_len + cmd_len;
  209. fsl_spi_cs_activate(slave, cs);
  210. /* Clear all eSPI events */
  211. out_be32(&espi->event , 0xffffffff);
  212. /* handle data in 32-bit chunks */
  213. while (num_blks) {
  214. event = in_be32(&espi->event);
  215. if (event & ESPI_EV_TNF) {
  216. fsl_espi_tx(fsl, dout);
  217. /* Set up the next iteration */
  218. if (len > 4) {
  219. len -= 4;
  220. dout += 4;
  221. }
  222. }
  223. event = in_be32(&espi->event);
  224. if (event & ESPI_EV_RNE) {
  225. rf_cnt = ((event & ESPI_EV_RFCNT_MASK)
  226. >> ESPI_EV_RFCNT_SHIFT);
  227. if (rf_cnt >= 4)
  228. rx_bytes = 4;
  229. else if (num_blks == 1 && rf_cnt == num_bytes)
  230. rx_bytes = num_bytes;
  231. else
  232. continue;
  233. if (fsl_espi_rx(fsl, din, rx_bytes)
  234. == rx_bytes) {
  235. num_blks--;
  236. if (din)
  237. din = (unsigned char *)din
  238. + rx_bytes;
  239. }
  240. }
  241. }
  242. if (data_in) {
  243. memcpy(data_in, buffer + 2 * cmd_len, tran_len);
  244. if (*buffer == 0x0b) {
  245. data_in += tran_len;
  246. data_len -= tran_len;
  247. *(int *)buffer += tran_len;
  248. }
  249. }
  250. fsl_spi_cs_deactivate(slave);
  251. }
  252. free(buffer);
  253. return 0;
  254. }
  255. void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs)
  256. {
  257. ccsr_espi_t *espi = fsl->espi;
  258. unsigned char pm = fsl->pm;
  259. unsigned int mode = fsl->mode;
  260. unsigned int div16 = fsl->div16;
  261. int i;
  262. /* Enable eSPI interface */
  263. out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
  264. | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
  265. out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
  266. out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */
  267. /* Init CS mode interface */
  268. for (i = 0; i < ESPI_MAX_CS_NUM; i++)
  269. out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
  270. out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
  271. ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
  272. | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
  273. | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
  274. /* Set eSPI BRG clock source */
  275. out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
  276. | ESPI_CSMODE_PM(pm) | div16);
  277. /* Set eSPI mode */
  278. if (mode & SPI_CPHA)
  279. out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
  280. | ESPI_CSMODE_CP_BEGIN_EDGCLK);
  281. if (mode & SPI_CPOL)
  282. out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
  283. | ESPI_CSMODE_CI_INACTIVEHIGH);
  284. /* Character bit order: msb first */
  285. out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
  286. | ESPI_CSMODE_REV_MSB_FIRST);
  287. /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
  288. out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
  289. | ESPI_CSMODE_LEN(7));
  290. }
  291. void espi_setup_slave(struct fsl_spi_slave *fsl)
  292. {
  293. unsigned int max_hz;
  294. sys_info_t sysinfo;
  295. unsigned long spibrg = 0;
  296. unsigned long spi_freq = 0;
  297. unsigned char pm = 0;
  298. max_hz = fsl->speed_hz;
  299. get_sys_info(&sysinfo);
  300. spibrg = sysinfo.freq_systembus / 2;
  301. fsl->div16 = 0;
  302. if ((spibrg / max_hz) > 32) {
  303. fsl->div16 = ESPI_CSMODE_DIV16;
  304. pm = spibrg / (max_hz * 16 * 2);
  305. if (pm > 16) {
  306. pm = 16;
  307. debug("max_hz is too low: %d Hz, %ld Hz is used.\n",
  308. max_hz, spibrg / (32 * 16));
  309. }
  310. } else {
  311. pm = spibrg / (max_hz * 2);
  312. }
  313. if (pm)
  314. pm--;
  315. fsl->pm = pm;
  316. if (fsl->div16)
  317. spi_freq = spibrg / ((pm + 1) * 2 * 16);
  318. else
  319. spi_freq = spibrg / ((pm + 1) * 2);
  320. /* set tx_timeout to 10 times of one espi FIFO entry go out */
  321. fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
  322. * 10), spi_freq);/* Set eSPI BRG clock source */
  323. }
  324. #if !CONFIG_IS_ENABLED(DM_SPI)
  325. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  326. {
  327. return bus == 0 && cs < ESPI_MAX_CS_NUM;
  328. }
  329. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  330. unsigned int max_hz, unsigned int mode)
  331. {
  332. struct fsl_spi_slave *fsl;
  333. if (!spi_cs_is_valid(bus, cs))
  334. return NULL;
  335. fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
  336. if (!fsl)
  337. return NULL;
  338. fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
  339. fsl->mode = mode;
  340. fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
  341. fsl->speed_hz = max_hz;
  342. espi_setup_slave(fsl);
  343. return &fsl->slave;
  344. }
  345. void spi_free_slave(struct spi_slave *slave)
  346. {
  347. struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
  348. free(fsl);
  349. }
  350. int spi_claim_bus(struct spi_slave *slave)
  351. {
  352. struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
  353. espi_claim_bus(fsl, slave->cs);
  354. return 0;
  355. }
  356. void spi_release_bus(struct spi_slave *slave)
  357. {
  358. struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
  359. espi_release_bus(fsl);
  360. }
  361. int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
  362. void *din, unsigned long flags)
  363. {
  364. struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;
  365. return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags);
  366. }
  367. #else
  368. static void __espi_set_speed(struct fsl_spi_slave *fsl)
  369. {
  370. espi_setup_slave(fsl);
  371. /* Set eSPI BRG clock source */
  372. out_be32(&fsl->espi->csmode[fsl->cs],
  373. in_be32(&fsl->espi->csmode[fsl->cs])
  374. | ESPI_CSMODE_PM(fsl->pm) | fsl->div16);
  375. }
  376. static void __espi_set_mode(struct fsl_spi_slave *fsl)
  377. {
  378. /* Set eSPI mode */
  379. if (fsl->mode & SPI_CPHA)
  380. out_be32(&fsl->espi->csmode[fsl->cs],
  381. in_be32(&fsl->espi->csmode[fsl->cs])
  382. | ESPI_CSMODE_CP_BEGIN_EDGCLK);
  383. if (fsl->mode & SPI_CPOL)
  384. out_be32(&fsl->espi->csmode[fsl->cs],
  385. in_be32(&fsl->espi->csmode[fsl->cs])
  386. | ESPI_CSMODE_CI_INACTIVEHIGH);
  387. }
  388. static int fsl_espi_claim_bus(struct udevice *dev)
  389. {
  390. struct udevice *bus = dev->parent;
  391. struct fsl_spi_slave *fsl = dev_get_priv(bus);
  392. espi_claim_bus(fsl, fsl->cs);
  393. return 0;
  394. }
  395. static int fsl_espi_release_bus(struct udevice *dev)
  396. {
  397. struct udevice *bus = dev->parent;
  398. struct fsl_spi_slave *fsl = dev_get_priv(bus);
  399. espi_release_bus(fsl);
  400. return 0;
  401. }
  402. static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
  403. const void *dout, void *din, unsigned long flags)
  404. {
  405. struct udevice *bus = dev->parent;
  406. struct fsl_spi_slave *fsl = dev_get_priv(bus);
  407. return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags);
  408. }
  409. static int fsl_espi_set_speed(struct udevice *bus, uint speed)
  410. {
  411. struct fsl_spi_slave *fsl = dev_get_priv(bus);
  412. debug("%s speed %u\n", __func__, speed);
  413. fsl->speed_hz = speed;
  414. __espi_set_speed(fsl);
  415. return 0;
  416. }
  417. static int fsl_espi_set_mode(struct udevice *bus, uint mode)
  418. {
  419. struct fsl_spi_slave *fsl = dev_get_priv(bus);
  420. debug("%s mode %u\n", __func__, mode);
  421. fsl->mode = mode;
  422. __espi_set_mode(fsl);
  423. return 0;
  424. }
  425. static int fsl_espi_child_pre_probe(struct udevice *dev)
  426. {
  427. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  428. struct udevice *bus = dev->parent;
  429. struct fsl_spi_slave *fsl = dev_get_priv(bus);
  430. debug("%s cs %u\n", __func__, slave_plat->cs);
  431. fsl->cs = slave_plat->cs;
  432. return 0;
  433. }
  434. static int fsl_espi_probe(struct udevice *bus)
  435. {
  436. struct fsl_espi_plat *plat = dev_get_plat(bus);
  437. struct fsl_spi_slave *fsl = dev_get_priv(bus);
  438. fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
  439. fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
  440. fsl->speed_hz = plat->speed_hz;
  441. debug("%s probe done, bus-num %d.\n", bus->name, dev_seq(bus));
  442. return 0;
  443. }
  444. static const struct dm_spi_ops fsl_espi_ops = {
  445. .claim_bus = fsl_espi_claim_bus,
  446. .release_bus = fsl_espi_release_bus,
  447. .xfer = fsl_espi_xfer,
  448. .set_speed = fsl_espi_set_speed,
  449. .set_mode = fsl_espi_set_mode,
  450. };
  451. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  452. static int fsl_espi_of_to_plat(struct udevice *bus)
  453. {
  454. fdt_addr_t addr;
  455. struct fsl_espi_plat *plat = bus->plat;
  456. const void *blob = gd->fdt_blob;
  457. int node = dev_of_offset(bus);
  458. addr = dev_read_addr(bus);
  459. if (addr == FDT_ADDR_T_NONE)
  460. return -EINVAL;
  461. plat->regs_addr = lower_32_bits(addr);
  462. plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  463. FSL_ESPI_DEFAULT_SCK_FREQ);
  464. debug("ESPI: regs=%p, max-frequency=%d\n",
  465. &plat->regs_addr, plat->speed_hz);
  466. return 0;
  467. }
  468. static const struct udevice_id fsl_espi_ids[] = {
  469. { .compatible = "fsl,mpc8536-espi" },
  470. { }
  471. };
  472. #endif
  473. U_BOOT_DRIVER(fsl_espi) = {
  474. .name = "fsl_espi",
  475. .id = UCLASS_SPI,
  476. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  477. .of_match = fsl_espi_ids,
  478. .of_to_plat = fsl_espi_of_to_plat,
  479. #endif
  480. .ops = &fsl_espi_ops,
  481. .plat_auto = sizeof(struct fsl_espi_plat),
  482. .priv_auto = sizeof(struct fsl_spi_slave),
  483. .probe = fsl_espi_probe,
  484. .child_pre_probe = fsl_espi_child_pre_probe,
  485. };
  486. #endif