serial_mcf.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
  4. * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
  5. *
  6. * Modified to add device model (DM) support
  7. * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
  8. *
  9. * Modified to add DM and fdt support, removed non DM code
  10. * (C) Copyright 2018 Angelo Dureghello <angelo@sysam.it>
  11. */
  12. /*
  13. * Minimal serial functions needed to use one of the uart ports
  14. * as serial console interface.
  15. */
  16. #include <common.h>
  17. #include <dm.h>
  18. #include <dm/platform_data/serial_coldfire.h>
  19. #include <serial.h>
  20. #include <linux/compiler.h>
  21. #include <asm/immap.h>
  22. #include <asm/uart.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. extern void uart_port_conf(int port);
  25. static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
  26. {
  27. u32 counter;
  28. uart_port_conf(port_idx);
  29. /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
  30. writeb(UART_UCR_RESET_RX, &uart->ucr);
  31. writeb(UART_UCR_RESET_TX, &uart->ucr);
  32. writeb(UART_UCR_RESET_ERROR, &uart->ucr);
  33. writeb(UART_UCR_RESET_MR, &uart->ucr);
  34. __asm__("nop");
  35. writeb(0, &uart->uimr);
  36. /* write to CSR: RX/TX baud rate from timers */
  37. writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
  38. writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
  39. writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
  40. /* Setting up BaudRate */
  41. counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
  42. counter = counter / baudrate;
  43. /* write to CTUR: divide counter upper byte */
  44. writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
  45. /* write to CTLR: divide counter lower byte */
  46. writeb((u8)(counter & 0x00ff), &uart->ubg2);
  47. writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
  48. return (0);
  49. }
  50. static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
  51. {
  52. u32 counter;
  53. /* Setting up BaudRate */
  54. counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
  55. counter = counter / baudrate;
  56. /* write to CTUR: divide counter upper byte */
  57. writeb(((counter & 0xff00) >> 8), &uart->ubg1);
  58. /* write to CTLR: divide counter lower byte */
  59. writeb((counter & 0x00ff), &uart->ubg2);
  60. writeb(UART_UCR_RESET_RX, &uart->ucr);
  61. writeb(UART_UCR_RESET_TX, &uart->ucr);
  62. writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
  63. }
  64. static int coldfire_serial_probe(struct udevice *dev)
  65. {
  66. struct coldfire_serial_plat *plat = dev->plat;
  67. plat->port = dev_seq(dev);
  68. return mcf_serial_init_common((uart_t *)plat->base,
  69. plat->port, plat->baudrate);
  70. }
  71. static int coldfire_serial_putc(struct udevice *dev, const char ch)
  72. {
  73. struct coldfire_serial_plat *plat = dev->plat;
  74. uart_t *uart = (uart_t *)plat->base;
  75. /* Wait for last character to go. */
  76. if (!(readb(&uart->usr) & UART_USR_TXRDY))
  77. return -EAGAIN;
  78. writeb(ch, &uart->utb);
  79. return 0;
  80. }
  81. static int coldfire_serial_getc(struct udevice *dev)
  82. {
  83. struct coldfire_serial_plat *plat = dev->plat;
  84. uart_t *uart = (uart_t *)(plat->base);
  85. /* Wait for a character to arrive. */
  86. if (!(readb(&uart->usr) & UART_USR_RXRDY))
  87. return -EAGAIN;
  88. return readb(&uart->urb);
  89. }
  90. int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
  91. {
  92. struct coldfire_serial_plat *plat = dev->plat;
  93. uart_t *uart = (uart_t *)(plat->base);
  94. mcf_serial_setbrg_common(uart, baudrate);
  95. return 0;
  96. }
  97. static int coldfire_serial_pending(struct udevice *dev, bool input)
  98. {
  99. struct coldfire_serial_plat *plat = dev->plat;
  100. uart_t *uart = (uart_t *)(plat->base);
  101. if (input)
  102. return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
  103. else
  104. return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
  105. return 0;
  106. }
  107. static int coldfire_of_to_plat(struct udevice *dev)
  108. {
  109. struct coldfire_serial_plat *plat = dev_get_plat(dev);
  110. fdt_addr_t addr_base;
  111. addr_base = dev_read_addr(dev);
  112. if (addr_base == FDT_ADDR_T_NONE)
  113. return -ENODEV;
  114. plat->base = (uint32_t)addr_base;
  115. plat->baudrate = gd->baudrate;
  116. return 0;
  117. }
  118. static const struct dm_serial_ops coldfire_serial_ops = {
  119. .putc = coldfire_serial_putc,
  120. .pending = coldfire_serial_pending,
  121. .getc = coldfire_serial_getc,
  122. .setbrg = coldfire_serial_setbrg,
  123. };
  124. static const struct udevice_id coldfire_serial_ids[] = {
  125. { .compatible = "fsl,mcf-uart" },
  126. { }
  127. };
  128. U_BOOT_DRIVER(serial_coldfire) = {
  129. .name = "serial_coldfire",
  130. .id = UCLASS_SERIAL,
  131. .of_match = coldfire_serial_ids,
  132. .of_to_plat = coldfire_of_to_plat,
  133. .plat_auto = sizeof(struct coldfire_serial_plat),
  134. .probe = coldfire_serial_probe,
  135. .ops = &coldfire_serial_ops,
  136. .flags = DM_FLAG_PRE_RELOC,
  137. };