pcie_rockchip.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Rockchip AXI PCIe host controller driver
  4. *
  5. * Copyright (c) 2016 Rockchip, Inc.
  6. * Copyright (c) 2020 Amarula Solutions(India)
  7. * Copyright (c) 2020 Jagan Teki <jagan@amarulasolutions.com>
  8. * Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
  9. * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
  10. *
  11. * Bits taken from Linux Rockchip PCIe host controller.
  12. */
  13. #include <common.h>
  14. #include <clk.h>
  15. #include <dm.h>
  16. #include <dm/device_compat.h>
  17. #include <generic-phy.h>
  18. #include <pci.h>
  19. #include <power-domain.h>
  20. #include <power/regulator.h>
  21. #include <reset.h>
  22. #include <syscon.h>
  23. #include <asm/io.h>
  24. #include <asm-generic/gpio.h>
  25. #include <asm/arch-rockchip/clock.h>
  26. #include <linux/iopoll.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
  29. #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
  30. #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
  31. #define PCIE_CLIENT_BASE 0x0
  32. #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
  33. #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
  34. #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
  35. #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
  36. #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
  37. #define PCIE_CLIENT_BASIC_STATUS1 0x0048
  38. #define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
  39. #define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
  40. #define PCIE_LINK_UP(x) \
  41. (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
  42. #define PCIE_RC_NORMAL_BASE 0x800000
  43. #define PCIE_LM_BASE 0x900000
  44. #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
  45. #define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
  46. #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
  47. #define PCIE_LM_RCBARPIE BIT(19)
  48. #define PCIE_LM_RCBARPIS BIT(20)
  49. #define PCIE_RC_BASE 0xa00000
  50. #define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
  51. #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
  52. #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
  53. #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
  54. #define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
  55. #define PCIE_ATR_BASE 0xc00000
  56. #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
  57. #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
  58. #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
  59. #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
  60. #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
  61. #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
  62. #define PCIE_ATR_HDR_MEM 0x2
  63. #define PCIE_ATR_HDR_IO 0x6
  64. #define PCIE_ATR_HDR_CFG_TYPE0 0xa
  65. #define PCIE_ATR_HDR_CFG_TYPE1 0xb
  66. #define PCIE_ATR_HDR_RID BIT(23)
  67. #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
  68. #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
  69. struct rockchip_pcie {
  70. fdt_addr_t axi_base;
  71. fdt_addr_t apb_base;
  72. int first_busno;
  73. struct udevice *dev;
  74. /* resets */
  75. struct reset_ctl core_rst;
  76. struct reset_ctl mgmt_rst;
  77. struct reset_ctl mgmt_sticky_rst;
  78. struct reset_ctl pipe_rst;
  79. struct reset_ctl pm_rst;
  80. struct reset_ctl pclk_rst;
  81. struct reset_ctl aclk_rst;
  82. /* gpio */
  83. struct gpio_desc ep_gpio;
  84. /* vpcie regulators */
  85. struct udevice *vpcie12v;
  86. struct udevice *vpcie3v3;
  87. struct udevice *vpcie1v8;
  88. struct udevice *vpcie0v9;
  89. /* phy */
  90. struct phy pcie_phy;
  91. };
  92. static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
  93. {
  94. unsigned int bus = PCI_BUS(bdf);
  95. unsigned int dev = PCI_DEV(bdf);
  96. unsigned int func = PCI_FUNC(bdf);
  97. return (bus << 20) | (dev << 15) | (func << 12) | (offset & ~0x3);
  98. }
  99. static int rockchip_pcie_rd_conf(const struct udevice *udev, pci_dev_t bdf,
  100. uint offset, ulong *valuep,
  101. enum pci_size_t size)
  102. {
  103. struct rockchip_pcie *priv = dev_get_priv(udev);
  104. unsigned int bus = PCI_BUS(bdf);
  105. unsigned int dev = PCI_DEV(bdf);
  106. int where = rockchip_pcie_off_conf(bdf, offset);
  107. ulong value;
  108. if (bus == priv->first_busno && dev == 0) {
  109. value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where);
  110. *valuep = pci_conv_32_to_size(value, offset, size);
  111. return 0;
  112. }
  113. if ((bus == priv->first_busno + 1) && dev == 0) {
  114. value = readl(priv->axi_base + where);
  115. *valuep = pci_conv_32_to_size(value, offset, size);
  116. return 0;
  117. }
  118. *valuep = pci_get_ff(size);
  119. return 0;
  120. }
  121. static int rockchip_pcie_wr_conf(struct udevice *udev, pci_dev_t bdf,
  122. uint offset, ulong value,
  123. enum pci_size_t size)
  124. {
  125. struct rockchip_pcie *priv = dev_get_priv(udev);
  126. unsigned int bus = PCI_BUS(bdf);
  127. unsigned int dev = PCI_DEV(bdf);
  128. int where = rockchip_pcie_off_conf(bdf, offset);
  129. ulong old;
  130. if (bus == priv->first_busno && dev == 0) {
  131. old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where);
  132. value = pci_conv_size_to_32(old, value, offset, size);
  133. writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + where);
  134. return 0;
  135. }
  136. if ((bus == priv->first_busno + 1) && dev == 0) {
  137. old = readl(priv->axi_base + where);
  138. value = pci_conv_size_to_32(old, value, offset, size);
  139. writel(value, priv->axi_base + where);
  140. return 0;
  141. }
  142. return 0;
  143. }
  144. static int rockchip_pcie_atr_init(struct rockchip_pcie *priv)
  145. {
  146. struct udevice *ctlr = pci_get_controller(priv->dev);
  147. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  148. u64 addr, size, offset;
  149. u32 type;
  150. int i, region;
  151. /* Use region 0 to map PCI configuration space. */
  152. writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));
  153. writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));
  154. writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,
  155. priv->apb_base + PCIE_ATR_OB_DESC0(0));
  156. writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0));
  157. for (i = 0; i < hose->region_count; i++) {
  158. if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
  159. continue;
  160. if (hose->regions[i].flags == PCI_REGION_IO)
  161. type = PCIE_ATR_HDR_IO;
  162. else
  163. type = PCIE_ATR_HDR_MEM;
  164. /* Only support identity mappings. */
  165. if (hose->regions[i].bus_start !=
  166. hose->regions[i].phys_start)
  167. return -EINVAL;
  168. /* Only support mappings aligned on a region boundary. */
  169. addr = hose->regions[i].bus_start;
  170. if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))
  171. return -EINVAL;
  172. /* Mappings should lie between AXI and APB regions. */
  173. size = hose->regions[i].size;
  174. if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE)
  175. return -EINVAL;
  176. if (addr + size > (u64)priv->apb_base)
  177. return -EINVAL;
  178. offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE;
  179. region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);
  180. while (size > 0) {
  181. writel(32 - 1,
  182. priv->apb_base + PCIE_ATR_OB_ADDR0(region));
  183. writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region));
  184. writel(type | PCIE_ATR_HDR_RID,
  185. priv->apb_base + PCIE_ATR_OB_DESC0(region));
  186. writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region));
  187. addr += PCIE_ATR_OB_REGION_SIZE;
  188. size -= PCIE_ATR_OB_REGION_SIZE;
  189. region++;
  190. }
  191. }
  192. /* Passthrough inbound translations unmodified. */
  193. writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2));
  194. writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2));
  195. return 0;
  196. }
  197. static int rockchip_pcie_init_port(struct udevice *dev)
  198. {
  199. struct rockchip_pcie *priv = dev_get_priv(dev);
  200. u32 cr, val, status;
  201. int ret;
  202. if (dm_gpio_is_valid(&priv->ep_gpio))
  203. dm_gpio_set_value(&priv->ep_gpio, 0);
  204. ret = reset_assert(&priv->aclk_rst);
  205. if (ret) {
  206. dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret);
  207. return ret;
  208. }
  209. ret = reset_assert(&priv->pclk_rst);
  210. if (ret) {
  211. dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret);
  212. return ret;
  213. }
  214. ret = reset_assert(&priv->pm_rst);
  215. if (ret) {
  216. dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret);
  217. return ret;
  218. }
  219. ret = generic_phy_init(&priv->pcie_phy);
  220. if (ret) {
  221. dev_err(dev, "failed to init phy (ret=%d)\n", ret);
  222. goto err_exit_phy;
  223. }
  224. ret = reset_assert(&priv->core_rst);
  225. if (ret) {
  226. dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);
  227. goto err_exit_phy;
  228. }
  229. ret = reset_assert(&priv->mgmt_rst);
  230. if (ret) {
  231. dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);
  232. goto err_exit_phy;
  233. }
  234. ret = reset_assert(&priv->mgmt_sticky_rst);
  235. if (ret) {
  236. dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",
  237. ret);
  238. goto err_exit_phy;
  239. }
  240. ret = reset_assert(&priv->pipe_rst);
  241. if (ret) {
  242. dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);
  243. goto err_exit_phy;
  244. }
  245. udelay(10);
  246. ret = reset_deassert(&priv->pm_rst);
  247. if (ret) {
  248. dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);
  249. goto err_exit_phy;
  250. }
  251. ret = reset_deassert(&priv->aclk_rst);
  252. if (ret) {
  253. dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);
  254. goto err_exit_phy;
  255. }
  256. ret = reset_deassert(&priv->pclk_rst);
  257. if (ret) {
  258. dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);
  259. goto err_exit_phy;
  260. }
  261. /* Select GEN1 for now */
  262. cr = PCIE_CLIENT_GEN_SEL_1;
  263. /* Set Root complex mode */
  264. cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
  265. writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
  266. ret = generic_phy_power_on(&priv->pcie_phy);
  267. if (ret) {
  268. dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
  269. goto err_power_off_phy;
  270. }
  271. ret = reset_deassert(&priv->mgmt_sticky_rst);
  272. if (ret) {
  273. dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n",
  274. ret);
  275. goto err_power_off_phy;
  276. }
  277. ret = reset_deassert(&priv->core_rst);
  278. if (ret) {
  279. dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret);
  280. goto err_power_off_phy;
  281. }
  282. ret = reset_deassert(&priv->mgmt_rst);
  283. if (ret) {
  284. dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret);
  285. goto err_power_off_phy;
  286. }
  287. ret = reset_deassert(&priv->pipe_rst);
  288. if (ret) {
  289. dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret);
  290. goto err_power_off_phy;
  291. }
  292. /* Enable Gen1 training */
  293. writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,
  294. priv->apb_base + PCIE_CLIENT_CONFIG);
  295. if (dm_gpio_is_valid(&priv->ep_gpio))
  296. dm_gpio_set_value(&priv->ep_gpio, 1);
  297. ret = readl_poll_sleep_timeout
  298. (priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,
  299. status, PCIE_LINK_UP(status), 20, 500 * 1000);
  300. if (ret) {
  301. dev_err(dev, "PCIe link training gen1 timeout!\n");
  302. goto err_power_off_phy;
  303. }
  304. /* Initialize Root Complex registers. */
  305. writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);
  306. writel(PCI_CLASS_BRIDGE_PCI << 16,
  307. priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);
  308. writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,
  309. priv->apb_base + PCIE_LM_RCBAR);
  310. if (dev_read_bool(dev, "aspm-no-l0s")) {
  311. val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP);
  312. val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;
  313. writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP);
  314. }
  315. /* Configure Address Translation. */
  316. ret = rockchip_pcie_atr_init(priv);
  317. if (ret) {
  318. dev_err(dev, "PCIE-%d: ATR init failed\n", dev_seq(dev));
  319. goto err_power_off_phy;
  320. }
  321. return 0;
  322. err_power_off_phy:
  323. generic_phy_power_off(&priv->pcie_phy);
  324. err_exit_phy:
  325. generic_phy_exit(&priv->pcie_phy);
  326. return ret;
  327. }
  328. static int rockchip_pcie_set_vpcie(struct udevice *dev)
  329. {
  330. struct rockchip_pcie *priv = dev_get_priv(dev);
  331. int ret;
  332. if (priv->vpcie3v3) {
  333. ret = regulator_set_enable(priv->vpcie3v3, true);
  334. if (ret) {
  335. dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",
  336. ret);
  337. return ret;
  338. }
  339. }
  340. if (priv->vpcie1v8) {
  341. ret = regulator_set_enable(priv->vpcie1v8, true);
  342. if (ret) {
  343. dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n",
  344. ret);
  345. goto err_disable_3v3;
  346. }
  347. }
  348. if (priv->vpcie0v9) {
  349. ret = regulator_set_enable(priv->vpcie0v9, true);
  350. if (ret) {
  351. dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n",
  352. ret);
  353. goto err_disable_1v8;
  354. }
  355. }
  356. return 0;
  357. err_disable_1v8:
  358. if (priv->vpcie1v8)
  359. regulator_set_enable(priv->vpcie1v8, false);
  360. err_disable_3v3:
  361. if (priv->vpcie3v3)
  362. regulator_set_enable(priv->vpcie3v3, false);
  363. return ret;
  364. }
  365. static int rockchip_pcie_parse_dt(struct udevice *dev)
  366. {
  367. struct rockchip_pcie *priv = dev_get_priv(dev);
  368. int ret;
  369. priv->axi_base = dev_read_addr_name(dev, "axi-base");
  370. if (!priv->axi_base)
  371. return -ENODEV;
  372. priv->apb_base = dev_read_addr_name(dev, "apb-base");
  373. if (!priv->axi_base)
  374. return -ENODEV;
  375. ret = gpio_request_by_name(dev, "ep-gpios", 0,
  376. &priv->ep_gpio, GPIOD_IS_OUT);
  377. if (ret) {
  378. dev_err(dev, "failed to find ep-gpios property\n");
  379. return ret;
  380. }
  381. ret = reset_get_by_name(dev, "core", &priv->core_rst);
  382. if (ret) {
  383. dev_err(dev, "failed to get core reset (ret=%d)\n", ret);
  384. return ret;
  385. }
  386. ret = reset_get_by_name(dev, "mgmt", &priv->mgmt_rst);
  387. if (ret) {
  388. dev_err(dev, "failed to get mgmt reset (ret=%d)\n", ret);
  389. return ret;
  390. }
  391. ret = reset_get_by_name(dev, "mgmt-sticky", &priv->mgmt_sticky_rst);
  392. if (ret) {
  393. dev_err(dev, "failed to get mgmt-sticky reset (ret=%d)\n", ret);
  394. return ret;
  395. }
  396. ret = reset_get_by_name(dev, "pipe", &priv->pipe_rst);
  397. if (ret) {
  398. dev_err(dev, "failed to get pipe reset (ret=%d)\n", ret);
  399. return ret;
  400. }
  401. ret = reset_get_by_name(dev, "pm", &priv->pm_rst);
  402. if (ret) {
  403. dev_err(dev, "failed to get pm reset (ret=%d)\n", ret);
  404. return ret;
  405. }
  406. ret = reset_get_by_name(dev, "pclk", &priv->pclk_rst);
  407. if (ret) {
  408. dev_err(dev, "failed to get pclk reset (ret=%d)\n", ret);
  409. return ret;
  410. }
  411. ret = reset_get_by_name(dev, "aclk", &priv->aclk_rst);
  412. if (ret) {
  413. dev_err(dev, "failed to get aclk reset (ret=%d)\n", ret);
  414. return ret;
  415. }
  416. ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
  417. &priv->vpcie3v3);
  418. if (ret && ret != -ENOENT) {
  419. dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);
  420. return ret;
  421. }
  422. ret = device_get_supply_regulator(dev, "vpcie1v8-supply",
  423. &priv->vpcie1v8);
  424. if (ret && ret != -ENOENT) {
  425. dev_err(dev, "failed to get vpcie1v8 supply (ret=%d)\n", ret);
  426. return ret;
  427. }
  428. ret = device_get_supply_regulator(dev, "vpcie0v9-supply",
  429. &priv->vpcie0v9);
  430. if (ret && ret != -ENOENT) {
  431. dev_err(dev, "failed to get vpcie0v9 supply (ret=%d)\n", ret);
  432. return ret;
  433. }
  434. ret = generic_phy_get_by_index(dev, 0, &priv->pcie_phy);
  435. if (ret) {
  436. dev_err(dev, "failed to get pcie-phy (ret=%d)\n", ret);
  437. return ret;
  438. }
  439. return 0;
  440. }
  441. static int rockchip_pcie_probe(struct udevice *dev)
  442. {
  443. struct rockchip_pcie *priv = dev_get_priv(dev);
  444. struct udevice *ctlr = pci_get_controller(dev);
  445. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  446. int ret;
  447. priv->first_busno = dev_seq(dev);
  448. priv->dev = dev;
  449. ret = rockchip_pcie_parse_dt(dev);
  450. if (ret)
  451. return ret;
  452. ret = rockchip_pcie_set_vpcie(dev);
  453. if (ret)
  454. return ret;
  455. ret = rockchip_pcie_init_port(dev);
  456. if (ret)
  457. return ret;
  458. dev_info(dev, "PCIE-%d: Link up (Bus%d)\n",
  459. dev_seq(dev), hose->first_busno);
  460. return 0;
  461. }
  462. static const struct dm_pci_ops rockchip_pcie_ops = {
  463. .read_config = rockchip_pcie_rd_conf,
  464. .write_config = rockchip_pcie_wr_conf,
  465. };
  466. static const struct udevice_id rockchip_pcie_ids[] = {
  467. { .compatible = "rockchip,rk3399-pcie" },
  468. { }
  469. };
  470. U_BOOT_DRIVER(rockchip_pcie) = {
  471. .name = "rockchip_pcie",
  472. .id = UCLASS_PCI,
  473. .of_match = rockchip_pcie_ids,
  474. .ops = &rockchip_pcie_ops,
  475. .probe = rockchip_pcie_probe,
  476. .priv_auto = sizeof(struct rockchip_pcie),
  477. };