pcie_mediatek.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek PCIe host controller driver.
  4. *
  5. * Copyright (c) 2017-2019 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. * Honghui Zhang <honghui.zhang@mediatek.com>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <generic-phy.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <pci.h>
  16. #include <reset.h>
  17. #include <asm/io.h>
  18. #include <dm/devres.h>
  19. #include <linux/bitops.h>
  20. #include <linux/iopoll.h>
  21. #include <linux/list.h>
  22. #include "pci_internal.h"
  23. /* PCIe shared registers */
  24. #define PCIE_SYS_CFG 0x00
  25. #define PCIE_INT_ENABLE 0x0c
  26. #define PCIE_CFG_ADDR 0x20
  27. #define PCIE_CFG_DATA 0x24
  28. /* PCIe per port registers */
  29. #define PCIE_BAR0_SETUP 0x10
  30. #define PCIE_CLASS 0x34
  31. #define PCIE_LINK_STATUS 0x50
  32. #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
  33. #define PCIE_PORT_PERST(x) BIT(1 + (x))
  34. #define PCIE_PORT_LINKUP BIT(0)
  35. #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
  36. #define PCIE_BAR_ENABLE BIT(0)
  37. #define PCIE_REVISION_ID BIT(0)
  38. #define PCIE_CLASS_CODE (0x60400 << 8)
  39. #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
  40. ((((regn) >> 8) & GENMASK(3, 0)) << 24))
  41. #define PCIE_CONF_ADDR(regn, bdf) \
  42. (PCIE_CONF_REG(regn) | (bdf))
  43. /* MediaTek specific configuration registers */
  44. #define PCIE_FTS_NUM 0x70c
  45. #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
  46. #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
  47. #define PCIE_FC_CREDIT 0x73c
  48. #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
  49. #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
  50. /* PCIe V2 share registers */
  51. #define PCIE_SYS_CFG_V2 0x0
  52. #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
  53. #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
  54. /* PCIe V2 per-port registers */
  55. #define PCIE_CONF_VEND_ID 0x100
  56. #define PCIE_CONF_DEVICE_ID 0x102
  57. #define PCIE_CONF_CLASS_ID 0x106
  58. #define PCIE_AHB_TRANS_BASE0_L 0x438
  59. #define PCIE_AHB_TRANS_BASE0_H 0x43c
  60. #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
  61. #define PCIE_AXI_WINDOW0 0x448
  62. #define WIN_ENABLE BIT(7)
  63. /*
  64. * Define PCIe to AHB window size as 2^33 to support max 8GB address space
  65. * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
  66. * start from 0x40000000).
  67. */
  68. #define PCIE2AHB_SIZE 0x21
  69. /* PCIe V2 configuration transaction header */
  70. #define PCIE_CFG_HEADER0 0x460
  71. #define PCIE_CFG_HEADER1 0x464
  72. #define PCIE_CFG_HEADER2 0x468
  73. #define PCIE_CFG_WDATA 0x470
  74. #define PCIE_APP_TLP_REQ 0x488
  75. #define PCIE_CFG_RDATA 0x48c
  76. #define APP_CFG_REQ BIT(0)
  77. #define APP_CPL_STATUS GENMASK(7, 5)
  78. #define CFG_WRRD_TYPE_0 4
  79. #define CFG_WR_FMT 2
  80. #define CFG_RD_FMT 0
  81. #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
  82. #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
  83. #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
  84. #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
  85. #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
  86. #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
  87. #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
  88. #define CFG_HEADER_DW0(type, fmt) \
  89. (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
  90. #define CFG_HEADER_DW1(where, size) \
  91. (GENMASK(((size) - 1), 0) << ((where) & 0x3))
  92. #define CFG_HEADER_DW2(regn, fun, dev, bus) \
  93. (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
  94. CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
  95. #define PCIE_RST_CTRL 0x510
  96. #define PCIE_PHY_RSTB BIT(0)
  97. #define PCIE_PIPE_SRSTB BIT(1)
  98. #define PCIE_MAC_SRSTB BIT(2)
  99. #define PCIE_CRSTB BIT(3)
  100. #define PCIE_PERSTB BIT(8)
  101. #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
  102. #define PCIE_LINK_STATUS_V2 0x804
  103. #define PCIE_PORT_LINKUP_V2 BIT(11)
  104. #define PCI_VENDOR_ID_MEDIATEK 0x14c3
  105. enum MTK_PCIE_GEN {PCIE_V1, PCIE_V2, PCIE_V3};
  106. struct mtk_pcie_port {
  107. void __iomem *base;
  108. struct list_head list;
  109. struct mtk_pcie *pcie;
  110. struct reset_ctl reset;
  111. struct clk sys_ck;
  112. struct clk ahb_ck;
  113. struct clk axi_ck;
  114. struct clk aux_ck;
  115. struct clk obff_ck;
  116. struct clk pipe_ck;
  117. struct phy phy;
  118. u32 slot;
  119. };
  120. struct mtk_pcie {
  121. void __iomem *base;
  122. void *priv;
  123. struct clk free_ck;
  124. struct list_head ports;
  125. };
  126. static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf,
  127. uint offset, void **paddress)
  128. {
  129. struct mtk_pcie *pcie = dev_get_priv(udev);
  130. writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
  131. *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
  132. return 0;
  133. }
  134. static int mtk_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
  135. uint offset, ulong *valuep,
  136. enum pci_size_t size)
  137. {
  138. return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
  139. bdf, offset, valuep, size);
  140. }
  141. static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  142. uint offset, ulong value,
  143. enum pci_size_t size)
  144. {
  145. return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
  146. bdf, offset, value, size);
  147. }
  148. static const struct dm_pci_ops mtk_pcie_ops = {
  149. .read_config = mtk_pcie_read_config,
  150. .write_config = mtk_pcie_write_config,
  151. };
  152. static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
  153. {
  154. u32 val;
  155. int err;
  156. err = readl_poll_timeout(port->base + PCIE_APP_TLP_REQ, val,
  157. !(val & APP_CFG_REQ), 100 * 1000);
  158. if (err)
  159. return -1;
  160. if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
  161. return -1;
  162. return 0;
  163. }
  164. static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, pci_dev_t devfn,
  165. int where, int size, ulong *val)
  166. {
  167. u32 tmp;
  168. writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
  169. port->base + PCIE_CFG_HEADER0);
  170. writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
  171. writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_DEV(devfn), bus),
  172. port->base + PCIE_CFG_HEADER2);
  173. /* Trigger h/w to transmit Cfgrd TLP */
  174. tmp = readl(port->base + PCIE_APP_TLP_REQ);
  175. tmp |= APP_CFG_REQ;
  176. writel(tmp, port->base + PCIE_APP_TLP_REQ);
  177. /* Check completion status */
  178. if (mtk_pcie_check_cfg_cpld(port))
  179. return -1;
  180. /* Read cpld payload of Cfgrd */
  181. *val = readl(port->base + PCIE_CFG_RDATA);
  182. if (size == 1)
  183. *val = (*val >> (8 * (where & 3))) & 0xff;
  184. else if (size == 2)
  185. *val = (*val >> (8 * (where & 3))) & 0xffff;
  186. return 0;
  187. }
  188. static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, pci_dev_t devfn,
  189. int where, int size, u32 val)
  190. {
  191. /* Write PCIe configuration transaction header for Cfgwr */
  192. writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
  193. port->base + PCIE_CFG_HEADER0);
  194. writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
  195. writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_DEV(devfn), bus),
  196. port->base + PCIE_CFG_HEADER2);
  197. /* Write Cfgwr data */
  198. val = val << 8 * (where & 3);
  199. writel(val, port->base + PCIE_CFG_WDATA);
  200. /* Trigger h/w to transmit Cfgwr TLP */
  201. val = readl(port->base + PCIE_APP_TLP_REQ);
  202. val |= APP_CFG_REQ;
  203. writel(val, port->base + PCIE_APP_TLP_REQ);
  204. /* Check completion status */
  205. return mtk_pcie_check_cfg_cpld(port);
  206. }
  207. static struct mtk_pcie_port *mtk_pcie_find_port(const struct udevice *bus,
  208. pci_dev_t bdf)
  209. {
  210. struct mtk_pcie *pcie = dev_get_priv(bus);
  211. struct mtk_pcie_port *port;
  212. struct udevice *dev;
  213. struct pci_child_plat *pplat = NULL;
  214. int ret = 0;
  215. if (PCI_BUS(bdf) != 0) {
  216. ret = pci_get_bus(PCI_BUS(bdf), &dev);
  217. if (ret) {
  218. debug("No such device,ret = %d\n", ret);
  219. return NULL;
  220. }
  221. while (dev_seq(dev->parent) != 0)
  222. dev = dev->parent;
  223. pplat = dev_get_parent_plat(dev);
  224. }
  225. list_for_each_entry(port, &pcie->ports, list) {
  226. if ((PCI_BUS(bdf) == 0) && (PCI_DEV(bdf) == port->slot))
  227. return port;
  228. if (PCI_BUS(bdf) != 0 && PCI_DEV(bdf) == 0 &&
  229. PCI_DEV(pplat->devfn) == port->slot)
  230. return port;
  231. }
  232. return NULL;
  233. }
  234. static int mtk_pcie_config_read(const struct udevice *bus, pci_dev_t bdf,
  235. uint offset, ulong *valuep,
  236. enum pci_size_t size)
  237. {
  238. struct mtk_pcie_port *port;
  239. int ret;
  240. port = mtk_pcie_find_port(bus, bdf);
  241. if (!port) {
  242. *valuep = pci_get_ff(size);
  243. return 0;
  244. }
  245. ret = mtk_pcie_hw_rd_cfg(port, PCI_BUS(bdf), bdf, offset, (1 << size), valuep);
  246. if (ret)
  247. *valuep = pci_get_ff(size);
  248. return ret;
  249. }
  250. static int mtk_pcie_config_write(struct udevice *bus, pci_dev_t bdf,
  251. uint offset, ulong value,
  252. enum pci_size_t size)
  253. {
  254. struct mtk_pcie_port *port;
  255. port = mtk_pcie_find_port(bus, bdf);
  256. if (!port)
  257. return 0;
  258. /* Do not modify RC bar 0/1. */
  259. if (PCI_BUS(bdf) == 0 && (offset == 0x10 || offset == 0x14))
  260. return 0;
  261. return mtk_pcie_hw_wr_cfg(port, PCI_BUS(bdf), bdf, offset, (1 << size), value);
  262. }
  263. static const struct dm_pci_ops mtk_pcie_ops_v2 = {
  264. .read_config = mtk_pcie_config_read,
  265. .write_config = mtk_pcie_config_write,
  266. };
  267. static void mtk_pcie_port_free(struct mtk_pcie_port *port)
  268. {
  269. list_del(&port->list);
  270. free(port);
  271. }
  272. static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
  273. {
  274. struct mtk_pcie *pcie = port->pcie;
  275. u32 slot = PCI_DEV(port->slot << 11);
  276. u32 val;
  277. int err;
  278. /* assert port PERST_N */
  279. setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
  280. /* de-assert port PERST_N */
  281. clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
  282. /* 100ms timeout value should be enough for Gen1/2 training */
  283. err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
  284. !!(val & PCIE_PORT_LINKUP), 100000);
  285. if (err)
  286. return -ETIMEDOUT;
  287. /* disable interrupt */
  288. clrbits_le32(pcie->base + PCIE_INT_ENABLE,
  289. PCIE_PORT_INT_EN(port->slot));
  290. /* map to all DDR region. We need to set it before cfg operation. */
  291. writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
  292. port->base + PCIE_BAR0_SETUP);
  293. /* configure class code and revision ID */
  294. writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
  295. /* configure FC credit */
  296. writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot),
  297. pcie->base + PCIE_CFG_ADDR);
  298. clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
  299. PCIE_FC_CREDIT_VAL(0x806c));
  300. /* configure RC FTS number to 250 when it leaves L0s */
  301. writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR);
  302. clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
  303. PCIE_FTS_NUM_L0(0x50));
  304. return 0;
  305. }
  306. static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
  307. {
  308. struct mtk_pcie *pcie = port->pcie;
  309. struct udevice *dev = pcie->priv;
  310. struct pci_region *pci_mem;
  311. u32 val;
  312. int err;
  313. /* MT7622/MT7629 platforms need to enable LTSSM and ASPM from PCIe subsys */
  314. if (pcie->base) {
  315. val = readl(pcie->base + PCIE_SYS_CFG_V2);
  316. val |= PCIE_CSR_LTSSM_EN(port->slot) |
  317. PCIE_CSR_ASPM_L1_EN(port->slot);
  318. writel(val, pcie->base + PCIE_SYS_CFG_V2);
  319. }
  320. /* Assert all reset signals */
  321. writel(0, port->base + PCIE_RST_CTRL);
  322. /*
  323. * Enable PCIe link down reset, if link status changed from link up to
  324. * link down, this will reset MAC control registers and configuration
  325. * space.
  326. */
  327. writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
  328. udelay(500);
  329. /* De-assert PHY, PE, PIPE, MAC and configuration reset */
  330. val = readl(port->base + PCIE_RST_CTRL);
  331. val |= PCIE_PHY_RSTB | PCIE_PIPE_SRSTB | PCIE_MAC_SRSTB | PCIE_CRSTB;
  332. writel(val, port->base + PCIE_RST_CTRL);
  333. mdelay(100);
  334. val |= PCIE_PERSTB;
  335. writel(val, port->base + PCIE_RST_CTRL);
  336. /* Set up vendor ID and class code */
  337. val = PCI_VENDOR_ID_MEDIATEK;
  338. writew(val, port->base + PCIE_CONF_VEND_ID);
  339. val = PCI_CLASS_BRIDGE_PCI;
  340. writew(val, port->base + PCIE_CONF_CLASS_ID);
  341. /* 100ms timeout value should be enough for Gen1/2 training */
  342. err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
  343. !!(val & PCIE_PORT_LINKUP_V2),
  344. 100 * 1000);
  345. if (err)
  346. return -ETIMEDOUT;
  347. pci_get_regions(dev, NULL, &pci_mem, NULL);
  348. /* Set AHB to PCIe translation windows */
  349. val = lower_32_bits(pci_mem->bus_start) |
  350. AHB2PCIE_SIZE(fls(pci_mem->size) - 1);
  351. writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
  352. val = upper_32_bits(pci_mem->bus_start);
  353. writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
  354. /* Set PCIe to AXI translation memory space.*/
  355. val = PCIE2AHB_SIZE | WIN_ENABLE;
  356. writel(val, port->base + PCIE_AXI_WINDOW0);
  357. return 0;
  358. }
  359. static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
  360. {
  361. int err;
  362. err = clk_enable(&port->sys_ck);
  363. if (err)
  364. goto err_sys_clk;
  365. err = reset_assert(&port->reset);
  366. if (err)
  367. goto err_reset;
  368. err = reset_deassert(&port->reset);
  369. if (err)
  370. goto err_reset;
  371. err = generic_phy_init(&port->phy);
  372. if (err)
  373. goto err_phy_init;
  374. err = generic_phy_power_on(&port->phy);
  375. if (err)
  376. goto err_phy_on;
  377. if (!mtk_pcie_startup_port(port))
  378. return;
  379. pr_err("Port%d link down\n", port->slot);
  380. generic_phy_power_off(&port->phy);
  381. err_phy_on:
  382. generic_phy_exit(&port->phy);
  383. err_phy_init:
  384. err_reset:
  385. clk_disable(&port->sys_ck);
  386. err_sys_clk:
  387. mtk_pcie_port_free(port);
  388. }
  389. static void mtk_pcie_enable_port_v2(struct mtk_pcie_port *port)
  390. {
  391. int err = 0;
  392. err = clk_enable(&port->sys_ck);
  393. if (err) {
  394. debug("clk_enable(sys_ck) failed: %d\n", err);
  395. goto exit;
  396. }
  397. err = clk_enable(&port->ahb_ck);
  398. if (err) {
  399. debug("clk_enable(ahb_ck) failed: %d\n", err);
  400. goto exit;
  401. }
  402. err = clk_enable(&port->aux_ck);
  403. if (err) {
  404. debug("clk_enable(aux_ck) failed: %d\n", err);
  405. goto exit;
  406. }
  407. err = clk_enable(&port->axi_ck);
  408. if (err) {
  409. debug("clk_enable(axi_ck) failed: %d\n", err);
  410. goto exit;
  411. }
  412. err = clk_enable(&port->obff_ck);
  413. if (err) {
  414. debug("clk_enable(obff_ck) failed: %d\n", err);
  415. goto exit;
  416. }
  417. err = clk_enable(&port->pipe_ck);
  418. if (err) {
  419. debug("clk_enable(pipe_ck) failed: %d\n", err);
  420. goto exit;
  421. }
  422. err = mtk_pcie_startup_port_v2(port);
  423. if (!err)
  424. return;
  425. pr_err("Port%d link down\n", port->slot);
  426. exit:
  427. mtk_pcie_port_free(port);
  428. }
  429. static int mtk_pcie_parse_port(struct udevice *dev, u32 slot)
  430. {
  431. struct mtk_pcie *pcie = dev_get_priv(dev);
  432. struct mtk_pcie_port *port;
  433. char name[10];
  434. int err;
  435. port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
  436. if (!port)
  437. return -ENOMEM;
  438. snprintf(name, sizeof(name), "port%d", slot);
  439. port->base = dev_remap_addr_name(dev, name);
  440. if (!port->base)
  441. return -ENOENT;
  442. snprintf(name, sizeof(name), "sys_ck%d", slot);
  443. err = clk_get_by_name(dev, name, &port->sys_ck);
  444. if (err)
  445. return err;
  446. err = reset_get_by_index(dev, slot, &port->reset);
  447. if (err)
  448. return err;
  449. err = generic_phy_get_by_index(dev, slot, &port->phy);
  450. if (err)
  451. return err;
  452. port->slot = slot;
  453. port->pcie = pcie;
  454. INIT_LIST_HEAD(&port->list);
  455. list_add_tail(&port->list, &pcie->ports);
  456. return 0;
  457. }
  458. static int mtk_pcie_parse_port_v2(struct udevice *dev, u32 slot)
  459. {
  460. struct mtk_pcie *pcie = dev_get_priv(dev);
  461. struct mtk_pcie_port *port;
  462. char name[10];
  463. int err;
  464. port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
  465. if (!port)
  466. return -ENOMEM;
  467. snprintf(name, sizeof(name), "port%d", slot);
  468. port->base = dev_remap_addr_name(dev, name);
  469. if (!port->base) {
  470. debug("failed to map port%d base\n", slot);
  471. return -ENOENT;
  472. }
  473. snprintf(name, sizeof(name), "sys_ck%d", slot);
  474. err = clk_get_by_name(dev, name, &port->sys_ck);
  475. if (err) {
  476. debug("clk_get_by_name(sys_ck) failed: %d\n", err);
  477. return err;
  478. }
  479. snprintf(name, sizeof(name), "ahb_ck%d", slot);
  480. err = clk_get_by_name(dev, name, &port->ahb_ck);
  481. if (err) {
  482. debug("clk_get_by_name(ahb_ck) failed: %d\n", err);
  483. return err;
  484. }
  485. snprintf(name, sizeof(name), "aux_ck%d", slot);
  486. err = clk_get_by_name(dev, name, &port->aux_ck);
  487. if (err) {
  488. debug("clk_get_by_name(aux_ck) failed: %d\n", err);
  489. return err;
  490. }
  491. snprintf(name, sizeof(name), "axi_ck%d", slot);
  492. err = clk_get_by_name(dev, name, &port->axi_ck);
  493. if (err) {
  494. debug("clk_get_by_name(axi_ck) failed: %d\n", err);
  495. return err;
  496. }
  497. snprintf(name, sizeof(name), "obff_ck%d", slot);
  498. err = clk_get_by_name(dev, name, &port->obff_ck);
  499. if (err) {
  500. debug("clk_get_by_name(obff_ck) failed: %d\n", err);
  501. return err;
  502. }
  503. snprintf(name, sizeof(name), "pipe_ck%d", slot);
  504. err = clk_get_by_name(dev, name, &port->pipe_ck);
  505. if (err) {
  506. debug("clk_get_by_name(pipe_ck) failed: %d\n", err);
  507. return err;
  508. }
  509. port->slot = slot;
  510. port->pcie = pcie;
  511. INIT_LIST_HEAD(&port->list);
  512. list_add_tail(&port->list, &pcie->ports);
  513. return 0;
  514. }
  515. static int mtk_pcie_probe(struct udevice *dev)
  516. {
  517. struct mtk_pcie *pcie = dev_get_priv(dev);
  518. struct mtk_pcie_port *port, *tmp;
  519. ofnode subnode;
  520. int err;
  521. INIT_LIST_HEAD(&pcie->ports);
  522. pcie->base = dev_remap_addr_name(dev, "subsys");
  523. if (!pcie->base)
  524. return -ENOENT;
  525. err = clk_get_by_name(dev, "free_ck", &pcie->free_ck);
  526. if (err)
  527. return err;
  528. /* enable top level clock */
  529. err = clk_enable(&pcie->free_ck);
  530. if (err)
  531. return err;
  532. dev_for_each_subnode(subnode, dev) {
  533. struct fdt_pci_addr addr;
  534. u32 slot = 0;
  535. if (!ofnode_is_available(subnode))
  536. continue;
  537. err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
  538. if (err)
  539. return err;
  540. slot = PCI_DEV(addr.phys_hi);
  541. err = mtk_pcie_parse_port(dev, slot);
  542. if (err)
  543. return err;
  544. }
  545. /* enable each port, and then check link status */
  546. list_for_each_entry_safe(port, tmp, &pcie->ports, list)
  547. mtk_pcie_enable_port(port);
  548. return 0;
  549. }
  550. static int mtk_pcie_probe_v2(struct udevice *dev)
  551. {
  552. struct mtk_pcie *pcie = dev_get_priv(dev);
  553. struct mtk_pcie_port *port, *tmp;
  554. struct fdt_pci_addr addr;
  555. ofnode subnode;
  556. unsigned int slot;
  557. int err;
  558. INIT_LIST_HEAD(&pcie->ports);
  559. pcie->base = dev_remap_addr_name(dev, "subsys");
  560. if (!pcie->base)
  561. return -ENOENT;
  562. pcie->priv = dev;
  563. dev_for_each_subnode(subnode, dev) {
  564. if (!ofnode_is_available(subnode))
  565. continue;
  566. err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
  567. if (err)
  568. return err;
  569. slot = PCI_DEV(addr.phys_hi);
  570. err = mtk_pcie_parse_port_v2(dev, slot);
  571. if (err)
  572. return err;
  573. }
  574. /* enable each port, and then check link status */
  575. list_for_each_entry_safe(port, tmp, &pcie->ports, list)
  576. mtk_pcie_enable_port_v2(port);
  577. return 0;
  578. }
  579. static const struct udevice_id mtk_pcie_ids[] = {
  580. { .compatible = "mediatek,mt7623-pcie", PCIE_V1},
  581. { }
  582. };
  583. U_BOOT_DRIVER(pcie_mediatek_v1) = {
  584. .name = "pcie_mediatek_v1",
  585. .id = UCLASS_PCI,
  586. .of_match = mtk_pcie_ids,
  587. .ops = &mtk_pcie_ops,
  588. .probe = mtk_pcie_probe,
  589. .priv_auto = sizeof(struct mtk_pcie),
  590. };
  591. static const struct udevice_id mtk_pcie_ids_v2[] = {
  592. { .compatible = "mediatek,mt7622-pcie", PCIE_V2},
  593. { }
  594. };
  595. U_BOOT_DRIVER(pcie_mediatek_v2) = {
  596. .name = "pcie_mediatek_v2",
  597. .id = UCLASS_PCI,
  598. .of_match = mtk_pcie_ids_v2,
  599. .ops = &mtk_pcie_ops_v2,
  600. .probe = mtk_pcie_probe_v2,
  601. .priv_auto = sizeof(struct mtk_pcie),
  602. };