pcie_layerscape_gen4.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2018-2019 NXP
  4. *
  5. * PCIe Gen4 driver for NXP Layerscape SoCs
  6. * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <pci.h>
  12. #include <asm/io.h>
  13. #include <errno.h>
  14. #include <malloc.h>
  15. #include <dm.h>
  16. #include <linux/sizes.h>
  17. #include "pcie_layerscape_gen4.h"
  18. DECLARE_GLOBAL_DATA_PTR;
  19. LIST_HEAD(ls_pcie_g4_list);
  20. static u64 bar_size[4] = {
  21. PCIE_BAR0_SIZE,
  22. PCIE_BAR1_SIZE,
  23. PCIE_BAR2_SIZE,
  24. PCIE_BAR4_SIZE
  25. };
  26. static int ls_pcie_g4_ltssm(struct ls_pcie_g4 *pcie)
  27. {
  28. u32 state;
  29. state = pf_ctrl_readl(pcie, PCIE_LTSSM_STA) & LTSSM_STATE_MASK;
  30. return state;
  31. }
  32. static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie)
  33. {
  34. int ltssm;
  35. ltssm = ls_pcie_g4_ltssm(pcie);
  36. if (ltssm != LTSSM_PCIE_L0)
  37. return 0;
  38. return 1;
  39. }
  40. static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie)
  41. {
  42. ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY);
  43. }
  44. static void ls_pcie_g4_cfg_set_target(struct ls_pcie_g4 *pcie, u32 target)
  45. {
  46. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target);
  47. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0);
  48. }
  49. static int ls_pcie_g4_outbound_win_set(struct ls_pcie_g4 *pcie, int idx,
  50. int type, u64 phys, u64 bus_addr,
  51. pci_size_t size)
  52. {
  53. u32 val;
  54. u32 size_h, size_l;
  55. if (idx >= PAB_WINS_NUM)
  56. return -EINVAL;
  57. size_h = upper_32_bits(~(size - 1));
  58. size_l = lower_32_bits(~(size - 1));
  59. val = ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
  60. val &= ~((AXI_AMAP_CTRL_TYPE_MASK << AXI_AMAP_CTRL_TYPE_SHIFT) |
  61. (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT) |
  62. AXI_AMAP_CTRL_EN);
  63. val |= ((type & AXI_AMAP_CTRL_TYPE_MASK) << AXI_AMAP_CTRL_TYPE_SHIFT) |
  64. ((size_l >> AXI_AMAP_CTRL_SIZE_SHIFT) <<
  65. AXI_AMAP_CTRL_SIZE_SHIFT) | AXI_AMAP_CTRL_EN;
  66. ccsr_writel(pcie, PAB_AXI_AMAP_CTRL(idx), val);
  67. ccsr_writel(pcie, PAB_AXI_AMAP_AXI_WIN(idx), lower_32_bits(phys));
  68. ccsr_writel(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(idx), upper_32_bits(phys));
  69. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
  70. ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
  71. ccsr_writel(pcie, PAB_EXT_AXI_AMAP_SIZE(idx), size_h);
  72. return 0;
  73. }
  74. static int ls_pcie_g4_rc_inbound_win_set(struct ls_pcie_g4 *pcie, int idx,
  75. int type, u64 phys, u64 bus_addr,
  76. pci_size_t size)
  77. {
  78. u32 val;
  79. pci_size_t win_size = ~(size - 1);
  80. val = ccsr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
  81. val &= ~(PEX_AMAP_CTRL_TYPE_MASK << PEX_AMAP_CTRL_TYPE_SHIFT);
  82. val &= ~(PEX_AMAP_CTRL_EN_MASK << PEX_AMAP_CTRL_EN_SHIFT);
  83. val = (val | (type << PEX_AMAP_CTRL_TYPE_SHIFT));
  84. val = (val | (1 << PEX_AMAP_CTRL_EN_SHIFT));
  85. ccsr_writel(pcie, PAB_PEX_AMAP_CTRL(idx),
  86. val | lower_32_bits(win_size));
  87. ccsr_writel(pcie, PAB_EXT_PEX_AMAP_SIZE(idx), upper_32_bits(win_size));
  88. ccsr_writel(pcie, PAB_PEX_AMAP_AXI_WIN(idx), lower_32_bits(phys));
  89. ccsr_writel(pcie, PAB_EXT_PEX_AMAP_AXI_WIN(idx), upper_32_bits(phys));
  90. ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
  91. ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
  92. return 0;
  93. }
  94. static void ls_pcie_g4_dump_wins(struct ls_pcie_g4 *pcie, int wins)
  95. {
  96. int i;
  97. for (i = 0; i < wins; i++) {
  98. debug("APIO Win%d:\n", i);
  99. debug("\tLOWER PHYS: 0x%08x\n",
  100. ccsr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(i)));
  101. debug("\tUPPER PHYS: 0x%08x\n",
  102. ccsr_readl(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(i)));
  103. debug("\tLOWER BUS: 0x%08x\n",
  104. ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_L(i)));
  105. debug("\tUPPER BUS: 0x%08x\n",
  106. ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(i)));
  107. debug("\tSIZE: 0x%08x\n",
  108. ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)) &
  109. (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT));
  110. debug("\tEXT_SIZE: 0x%08x\n",
  111. ccsr_readl(pcie, PAB_EXT_AXI_AMAP_SIZE(i)));
  112. debug("\tPARAM: 0x%08x\n",
  113. ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(i)));
  114. debug("\tCTRL: 0x%08x\n",
  115. ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)));
  116. }
  117. }
  118. static void ls_pcie_g4_setup_wins(struct ls_pcie_g4 *pcie)
  119. {
  120. struct pci_region *io, *mem, *pref;
  121. int idx = 1;
  122. /* INBOUND WIN */
  123. ls_pcie_g4_rc_inbound_win_set(pcie, 0, IB_TYPE_MEM_F, 0, 0, SIZE_1T);
  124. /* OUTBOUND WIN 0: CFG */
  125. ls_pcie_g4_outbound_win_set(pcie, 0, PAB_AXI_TYPE_CFG,
  126. pcie->cfg_res.start, 0,
  127. fdt_resource_size(&pcie->cfg_res));
  128. pci_get_regions(pcie->bus, &io, &mem, &pref);
  129. if (io)
  130. /* OUTBOUND WIN: IO */
  131. ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_IO,
  132. io->phys_start, io->bus_start,
  133. io->size);
  134. if (mem)
  135. /* OUTBOUND WIN: MEM */
  136. ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
  137. mem->phys_start, mem->bus_start,
  138. mem->size);
  139. if (pref)
  140. /* OUTBOUND WIN: perf MEM */
  141. ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
  142. pref->phys_start, pref->bus_start,
  143. pref->size);
  144. ls_pcie_g4_dump_wins(pcie, idx);
  145. }
  146. /* Return 0 if the address is valid, -errno if not valid */
  147. static int ls_pcie_g4_addr_valid(struct ls_pcie_g4 *pcie, pci_dev_t bdf)
  148. {
  149. struct udevice *bus = pcie->bus;
  150. if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
  151. return -ENODEV;
  152. if (!pcie->enabled)
  153. return -ENXIO;
  154. if (PCI_BUS(bdf) < dev_seq(bus))
  155. return -EINVAL;
  156. if ((PCI_BUS(bdf) > dev_seq(bus)) && (!ls_pcie_g4_link_up(pcie)))
  157. return -EINVAL;
  158. if (PCI_BUS(bdf) <= (dev_seq(bus) + 1) && (PCI_DEV(bdf) > 0))
  159. return -EINVAL;
  160. return 0;
  161. }
  162. void *ls_pcie_g4_conf_address(struct ls_pcie_g4 *pcie, pci_dev_t bdf,
  163. int offset)
  164. {
  165. struct udevice *bus = pcie->bus;
  166. u32 target;
  167. if (PCI_BUS(bdf) == dev_seq(bus)) {
  168. if (offset < INDIRECT_ADDR_BNDRY) {
  169. ccsr_set_page(pcie, 0);
  170. return pcie->ccsr + offset;
  171. }
  172. ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
  173. return pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset);
  174. }
  175. target = PAB_TARGET_BUS(PCI_BUS(bdf) - dev_seq(bus)) |
  176. PAB_TARGET_DEV(PCI_DEV(bdf)) |
  177. PAB_TARGET_FUNC(PCI_FUNC(bdf));
  178. ls_pcie_g4_cfg_set_target(pcie, target);
  179. return pcie->cfg + offset;
  180. }
  181. static int ls_pcie_g4_read_config(const struct udevice *bus, pci_dev_t bdf,
  182. uint offset, ulong *valuep,
  183. enum pci_size_t size)
  184. {
  185. struct ls_pcie_g4 *pcie = dev_get_priv(bus);
  186. void *address;
  187. int ret = 0;
  188. if (ls_pcie_g4_addr_valid(pcie, bdf)) {
  189. *valuep = pci_get_ff(size);
  190. return 0;
  191. }
  192. address = ls_pcie_g4_conf_address(pcie, bdf, offset);
  193. switch (size) {
  194. case PCI_SIZE_8:
  195. *valuep = readb(address);
  196. break;
  197. case PCI_SIZE_16:
  198. *valuep = readw(address);
  199. break;
  200. case PCI_SIZE_32:
  201. *valuep = readl(address);
  202. break;
  203. default:
  204. ret = -EINVAL;
  205. break;
  206. }
  207. return ret;
  208. }
  209. static int ls_pcie_g4_write_config(struct udevice *bus, pci_dev_t bdf,
  210. uint offset, ulong value,
  211. enum pci_size_t size)
  212. {
  213. struct ls_pcie_g4 *pcie = dev_get_priv(bus);
  214. void *address;
  215. if (ls_pcie_g4_addr_valid(pcie, bdf))
  216. return 0;
  217. address = ls_pcie_g4_conf_address(pcie, bdf, offset);
  218. switch (size) {
  219. case PCI_SIZE_8:
  220. writeb(value, address);
  221. return 0;
  222. case PCI_SIZE_16:
  223. writew(value, address);
  224. return 0;
  225. case PCI_SIZE_32:
  226. writel(value, address);
  227. return 0;
  228. default:
  229. return -EINVAL;
  230. }
  231. }
  232. static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie)
  233. {
  234. u32 val;
  235. /* Fix class code */
  236. val = ccsr_readl(pcie, GPEX_CLASSCODE);
  237. val &= ~(GPEX_CLASSCODE_MASK << GPEX_CLASSCODE_SHIFT);
  238. val |= PCI_CLASS_BRIDGE_PCI << GPEX_CLASSCODE_SHIFT;
  239. ccsr_writel(pcie, GPEX_CLASSCODE, val);
  240. /* Enable APIO and Memory/IO/CFG Wins */
  241. val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
  242. val |= APIO_EN | MEM_WIN_EN | IO_WIN_EN | CFG_WIN_EN;
  243. ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
  244. ls_pcie_g4_setup_wins(pcie);
  245. pcie->stream_id_cur = 0;
  246. }
  247. static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf,
  248. int bar, u64 phys)
  249. {
  250. u32 val;
  251. /* PF BAR1 is for MSI-X and only need to enable */
  252. if (bar == 1) {
  253. ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), BAR_AMAP_EN);
  254. return;
  255. }
  256. val = upper_32_bits(phys);
  257. ccsr_writel(pcie, PAB_EXT_PEX_BAR_AMAP(pf, bar), val);
  258. val = lower_32_bits(phys) | BAR_AMAP_EN;
  259. ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), val);
  260. }
  261. static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)
  262. {
  263. u64 phys;
  264. int bar;
  265. u32 val;
  266. if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1)
  267. return;
  268. phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
  269. for (bar = 0; bar < PF_BAR_NUM; bar++) {
  270. ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys);
  271. phys += PCIE_BAR_SIZE;
  272. }
  273. /* OUTBOUND: map MEM */
  274. ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM,
  275. pcie->cfg_res.start +
  276. CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
  277. CONFIG_SYS_PCI_MEMORY_SIZE);
  278. val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf));
  279. val &= ~FUNC_NUM_PCIE_MASK;
  280. val |= pf;
  281. ccsr_writel(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf), val);
  282. }
  283. static void ls_pcie_g4_ep_enable_bar(struct ls_pcie_g4 *pcie, int pf,
  284. int bar, bool vf_bar, bool enable)
  285. {
  286. u32 val;
  287. u32 bar_pos = BAR_POS(bar, pf, vf_bar);
  288. val = ccsr_readl(pcie, GPEX_BAR_ENABLE);
  289. if (enable)
  290. val |= 1 << bar_pos;
  291. else
  292. val &= ~(1 << bar_pos);
  293. ccsr_writel(pcie, GPEX_BAR_ENABLE, val);
  294. }
  295. static void ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4 *pcie, int pf,
  296. int bar, bool vf_bar, u64 size)
  297. {
  298. u32 bar_pos = BAR_POS(bar, pf, vf_bar);
  299. u32 mask_l = lower_32_bits(~(size - 1));
  300. u32 mask_h = upper_32_bits(~(size - 1));
  301. ccsr_writel(pcie, GPEX_BAR_SELECT, bar_pos);
  302. ccsr_writel(pcie, GPEX_BAR_SIZE_LDW, mask_l);
  303. ccsr_writel(pcie, GPEX_BAR_SIZE_UDW, mask_h);
  304. }
  305. static void ls_pcie_g4_ep_setup_bar(struct ls_pcie_g4 *pcie, int pf,
  306. int bar, bool vf_bar, u64 size)
  307. {
  308. bool en = size ? true : false;
  309. ls_pcie_g4_ep_enable_bar(pcie, pf, bar, vf_bar, en);
  310. ls_pcie_g4_ep_set_bar_size(pcie, pf, bar, vf_bar, size);
  311. }
  312. static void ls_pcie_g4_ep_setup_bars(struct ls_pcie_g4 *pcie, int pf)
  313. {
  314. int bar;
  315. /* Setup PF BARs */
  316. for (bar = 0; bar < PF_BAR_NUM; bar++)
  317. ls_pcie_g4_ep_setup_bar(pcie, pf, bar, false, bar_size[bar]);
  318. if (!pcie->sriov_support)
  319. return;
  320. /* Setup VF BARs */
  321. for (bar = 0; bar < VF_BAR_NUM; bar++)
  322. ls_pcie_g4_ep_setup_bar(pcie, pf, bar, true, bar_size[bar]);
  323. }
  324. static void ls_pcie_g4_set_sriov(struct ls_pcie_g4 *pcie, int pf)
  325. {
  326. unsigned int val;
  327. val = ccsr_readl(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf));
  328. val &= ~(TTL_VF_MASK << TTL_VF_SHIFT);
  329. val |= PCIE_VF_NUM << TTL_VF_SHIFT;
  330. val &= ~(INI_VF_MASK << INI_VF_SHIFT);
  331. val |= PCIE_VF_NUM << INI_VF_SHIFT;
  332. ccsr_writel(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf), val);
  333. val = ccsr_readl(pcie, PCIE_SRIOV_VF_OFFSET_STRIDE);
  334. val += PCIE_VF_NUM * pf - pf;
  335. ccsr_writel(pcie, GPEX_SRIOV_VF_OFFSET_STRIDE(pf), val);
  336. }
  337. static void ls_pcie_g4_setup_ep(struct ls_pcie_g4 *pcie)
  338. {
  339. u32 pf, sriov;
  340. u32 val;
  341. int i;
  342. /* Enable APIO and Memory Win */
  343. val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
  344. val |= APIO_EN | MEM_WIN_EN;
  345. ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
  346. sriov = ccsr_readl(pcie, PCIE_SRIOV_CAPABILITY);
  347. if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
  348. pcie->sriov_support = 1;
  349. pf = pcie->sriov_support ? PCIE_PF_NUM : 1;
  350. for (i = 0; i < pf; i++) {
  351. ls_pcie_g4_ep_setup_bars(pcie, i);
  352. ls_pcie_g4_ep_setup_wins(pcie, i);
  353. if (pcie->sriov_support)
  354. ls_pcie_g4_set_sriov(pcie, i);
  355. }
  356. ls_pcie_g4_ep_enable_cfg(pcie);
  357. ls_pcie_g4_dump_wins(pcie, pf);
  358. }
  359. static int ls_pcie_g4_probe(struct udevice *dev)
  360. {
  361. struct ls_pcie_g4 *pcie = dev_get_priv(dev);
  362. const void *fdt = gd->fdt_blob;
  363. int node = dev_of_offset(dev);
  364. u32 link_ctrl_sta;
  365. u32 val;
  366. int ret;
  367. pcie->bus = dev;
  368. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  369. "ccsr", &pcie->ccsr_res);
  370. if (ret) {
  371. printf("ls-pcie-g4: resource \"ccsr\" not found\n");
  372. return ret;
  373. }
  374. pcie->idx = (pcie->ccsr_res.start - PCIE_SYS_BASE_ADDR) /
  375. PCIE_CCSR_SIZE;
  376. list_add(&pcie->list, &ls_pcie_g4_list);
  377. pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
  378. if (!pcie->enabled) {
  379. printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
  380. return 0;
  381. }
  382. pcie->ccsr = map_physmem(pcie->ccsr_res.start,
  383. fdt_resource_size(&pcie->ccsr_res),
  384. MAP_NOCACHE);
  385. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  386. "config", &pcie->cfg_res);
  387. if (ret) {
  388. printf("%s: resource \"config\" not found\n", dev->name);
  389. return ret;
  390. }
  391. pcie->cfg = map_physmem(pcie->cfg_res.start,
  392. fdt_resource_size(&pcie->cfg_res),
  393. MAP_NOCACHE);
  394. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  395. "lut", &pcie->lut_res);
  396. if (ret) {
  397. printf("ls-pcie-g4: resource \"lut\" not found\n");
  398. return ret;
  399. }
  400. pcie->lut = map_physmem(pcie->lut_res.start,
  401. fdt_resource_size(&pcie->lut_res),
  402. MAP_NOCACHE);
  403. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  404. "pf_ctrl", &pcie->pf_ctrl_res);
  405. if (ret) {
  406. printf("ls-pcie-g4: resource \"pf_ctrl\" not found\n");
  407. return ret;
  408. }
  409. pcie->pf_ctrl = map_physmem(pcie->pf_ctrl_res.start,
  410. fdt_resource_size(&pcie->pf_ctrl_res),
  411. MAP_NOCACHE);
  412. pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
  413. debug("%s ccsr:%lx, cfg:0x%lx, big-endian:%d\n",
  414. dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg,
  415. pcie->big_endian);
  416. pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
  417. if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
  418. printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
  419. ls_pcie_g4_setup_ep(pcie);
  420. } else {
  421. printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
  422. ls_pcie_g4_setup_ctrl(pcie);
  423. }
  424. /* Enable Amba & PEX PIO */
  425. val = ccsr_readl(pcie, PAB_CTRL);
  426. val |= PAB_CTRL_APIO_EN | PAB_CTRL_PPIO_EN;
  427. ccsr_writel(pcie, PAB_CTRL, val);
  428. val = ccsr_readl(pcie, PAB_PEX_PIO_CTRL(0));
  429. val |= PPIO_EN;
  430. ccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val);
  431. if (!ls_pcie_g4_link_up(pcie)) {
  432. /* Let the user know there's no PCIe link */
  433. printf(": no link\n");
  434. return 0;
  435. }
  436. /* Print the negotiated PCIe link width */
  437. link_ctrl_sta = ccsr_readl(pcie, PCIE_LINK_CTRL_STA);
  438. printf(": x%d gen%d\n",
  439. (link_ctrl_sta >> PCIE_LINK_WIDTH_SHIFT & PCIE_LINK_WIDTH_MASK),
  440. (link_ctrl_sta >> PCIE_LINK_SPEED_SHIFT) & PCIE_LINK_SPEED_MASK);
  441. return 0;
  442. }
  443. static const struct dm_pci_ops ls_pcie_g4_ops = {
  444. .read_config = ls_pcie_g4_read_config,
  445. .write_config = ls_pcie_g4_write_config,
  446. };
  447. static const struct udevice_id ls_pcie_g4_ids[] = {
  448. { .compatible = "fsl,lx2160a-pcie" },
  449. { }
  450. };
  451. U_BOOT_DRIVER(pcie_layerscape_gen4) = {
  452. .name = "pcie_layerscape_gen4",
  453. .id = UCLASS_PCI,
  454. .of_match = ls_pcie_g4_ids,
  455. .ops = &ls_pcie_g4_ops,
  456. .probe = ls_pcie_g4_probe,
  457. .priv_auto = sizeof(struct ls_pcie_g4),
  458. };