pcie_dw_ti.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Texas Instruments, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <pci.h>
  9. #include <generic-phy.h>
  10. #include <power-domain.h>
  11. #include <regmap.h>
  12. #include <syscon.h>
  13. #include <asm/io.h>
  14. #include <asm-generic/gpio.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <linux/err.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define PCIE_VENDORID_MASK GENMASK(15, 0)
  21. #define PCIE_DEVICEID_SHIFT 16
  22. /* PCI DBICS registers */
  23. #define PCIE_CONFIG_BAR0 0x10
  24. #define PCIE_LINK_STATUS_REG 0x80
  25. #define PCIE_LINK_STATUS_SPEED_OFF 16
  26. #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
  27. #define PCIE_LINK_STATUS_WIDTH_OFF 20
  28. #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
  29. #define PCIE_LINK_CAPABILITY 0x7c
  30. #define PCIE_LINK_CTL_2 0xa0
  31. #define TARGET_LINK_SPEED_MASK 0xf
  32. #define LINK_SPEED_GEN_1 0x1
  33. #define LINK_SPEED_GEN_2 0x2
  34. #define LINK_SPEED_GEN_3 0x3
  35. #define PCIE_MISC_CONTROL_1_OFF 0x8bc
  36. #define PCIE_DBI_RO_WR_EN BIT(0)
  37. #define PLR_OFFSET 0x700
  38. #define PCIE_PORT_DEBUG0 (PLR_OFFSET + 0x28)
  39. #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
  40. #define PORT_LOGIC_LTSSM_STATE_L0 0x11
  41. #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c
  42. #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
  43. #define PCIE_LINK_UP_TIMEOUT_MS 100
  44. /*
  45. * iATU Unroll-specific register definitions
  46. * From 4.80 core version the address translation will be made by unroll.
  47. * The registers are offset from atu_base
  48. */
  49. #define PCIE_ATU_UNR_REGION_CTRL1 0x00
  50. #define PCIE_ATU_UNR_REGION_CTRL2 0x04
  51. #define PCIE_ATU_UNR_LOWER_BASE 0x08
  52. #define PCIE_ATU_UNR_UPPER_BASE 0x0c
  53. #define PCIE_ATU_UNR_LIMIT 0x10
  54. #define PCIE_ATU_UNR_LOWER_TARGET 0x14
  55. #define PCIE_ATU_UNR_UPPER_TARGET 0x18
  56. #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  57. #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  58. #define PCIE_ATU_TYPE_MEM (0x0 << 0)
  59. #define PCIE_ATU_TYPE_IO (0x2 << 0)
  60. #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  61. #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  62. #define PCIE_ATU_ENABLE (0x1 << 31)
  63. #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  64. #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
  65. #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
  66. #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
  67. /* Register address builder */
  68. #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
  69. /* Offsets from App base */
  70. #define PCIE_CMD_STATUS 0x04
  71. #define LTSSM_EN_VAL BIT(0)
  72. /* Parameters for the waiting for iATU enabled routine */
  73. #define LINK_WAIT_MAX_IATU_RETRIES 5
  74. #define LINK_WAIT_IATU 10000
  75. #define AM654_PCIE_DEV_TYPE_MASK 0x3
  76. #define EP 0x0
  77. #define LEG_EP 0x1
  78. #define RC 0x2
  79. /**
  80. * struct pcie_dw_ti - TI DW PCIe controller state
  81. *
  82. * @app_base: The base address of application register space
  83. * @dbics_base: The base address of dbics register space
  84. * @cfg_base: The base address of configuration space
  85. * @atu_base: The base address of ATU space
  86. * @cfg_size: The size of the configuration space which is needed
  87. * as it gets written into the PCIE_ATU_LIMIT register
  88. * @first_busno: This driver supports multiple PCIe controllers.
  89. * first_busno stores the bus number of the PCIe root-port
  90. * number which may vary depending on the PCIe setup
  91. * (PEX switches etc).
  92. */
  93. struct pcie_dw_ti {
  94. void *app_base;
  95. void *dbi_base;
  96. void *cfg_base;
  97. void *atu_base;
  98. fdt_size_t cfg_size;
  99. int first_busno;
  100. struct udevice *dev;
  101. /* IO and MEM PCI regions */
  102. struct pci_region io;
  103. struct pci_region mem;
  104. };
  105. enum dw_pcie_device_mode {
  106. DW_PCIE_UNKNOWN_TYPE,
  107. DW_PCIE_EP_TYPE,
  108. DW_PCIE_LEG_EP_TYPE,
  109. DW_PCIE_RC_TYPE,
  110. };
  111. static int pcie_dw_get_link_speed(struct pcie_dw_ti *pci)
  112. {
  113. return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
  114. PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
  115. }
  116. static int pcie_dw_get_link_width(struct pcie_dw_ti *pci)
  117. {
  118. return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
  119. PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
  120. }
  121. static void dw_pcie_writel_ob_unroll(struct pcie_dw_ti *pci, u32 index, u32 reg,
  122. u32 val)
  123. {
  124. u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
  125. void __iomem *base = pci->atu_base;
  126. writel(val, base + offset + reg);
  127. }
  128. static u32 dw_pcie_readl_ob_unroll(struct pcie_dw_ti *pci, u32 index, u32 reg)
  129. {
  130. u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
  131. void __iomem *base = pci->atu_base;
  132. return readl(base + offset + reg);
  133. }
  134. /**
  135. * pcie_dw_prog_outbound_atu_unroll() - Configure ATU for outbound accesses
  136. *
  137. * @pcie: Pointer to the PCI controller state
  138. * @index: ATU region index
  139. * @type: ATU accsess type
  140. * @cpu_addr: the physical address for the translation entry
  141. * @pci_addr: the pcie bus address for the translation entry
  142. * @size: the size of the translation entry
  143. */
  144. static void pcie_dw_prog_outbound_atu_unroll(struct pcie_dw_ti *pci, int index,
  145. int type, u64 cpu_addr,
  146. u64 pci_addr, u32 size)
  147. {
  148. u32 retries, val;
  149. debug("ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
  150. index, type, cpu_addr, pci_addr, size);
  151. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
  152. lower_32_bits(cpu_addr));
  153. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
  154. upper_32_bits(cpu_addr));
  155. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
  156. lower_32_bits(cpu_addr + size - 1));
  157. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
  158. lower_32_bits(pci_addr));
  159. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
  160. upper_32_bits(pci_addr));
  161. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
  162. type);
  163. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
  164. PCIE_ATU_ENABLE);
  165. /*
  166. * Make sure ATU enable takes effect before any subsequent config
  167. * and I/O accesses.
  168. */
  169. for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
  170. val = dw_pcie_readl_ob_unroll(pci, index,
  171. PCIE_ATU_UNR_REGION_CTRL2);
  172. if (val & PCIE_ATU_ENABLE)
  173. return;
  174. udelay(LINK_WAIT_IATU);
  175. }
  176. dev_err(pci->dev, "outbound iATU is not being enabled\n");
  177. }
  178. /**
  179. * set_cfg_address() - Configure the PCIe controller config space access
  180. *
  181. * @pcie: Pointer to the PCI controller state
  182. * @d: PCI device to access
  183. * @where: Offset in the configuration space
  184. *
  185. * Configures the PCIe controller to access the configuration space of
  186. * a specific PCIe device and returns the address to use for this
  187. * access.
  188. *
  189. * Return: Address that can be used to access the configation space
  190. * of the requested device / offset
  191. */
  192. static uintptr_t set_cfg_address(struct pcie_dw_ti *pcie,
  193. pci_dev_t d, uint where)
  194. {
  195. int bus = PCI_BUS(d) - pcie->first_busno;
  196. uintptr_t va_address;
  197. u32 atu_type;
  198. /* Use dbi_base for own configuration read and write */
  199. if (!bus) {
  200. va_address = (uintptr_t)pcie->dbi_base;
  201. goto out;
  202. }
  203. if (bus == 1)
  204. /* For local bus, change TLP Type field to 4. */
  205. atu_type = PCIE_ATU_TYPE_CFG0;
  206. else
  207. /* Otherwise, change TLP Type field to 5. */
  208. atu_type = PCIE_ATU_TYPE_CFG1;
  209. /*
  210. * Not accessing root port configuration space?
  211. * Region #0 is used for Outbound CFG space access.
  212. * Direction = Outbound
  213. * Region Index = 0
  214. */
  215. d = PCI_MASK_BUS(d);
  216. d = PCI_ADD_BUS(bus, d);
  217. pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
  218. atu_type, (u64)pcie->cfg_base,
  219. d << 8, pcie->cfg_size);
  220. va_address = (uintptr_t)pcie->cfg_base;
  221. out:
  222. va_address += where & ~0x3;
  223. return va_address;
  224. }
  225. /**
  226. * pcie_dw_addr_valid() - Check for valid bus address
  227. *
  228. * @d: The PCI device to access
  229. * @first_busno: Bus number of the PCIe controller root complex
  230. *
  231. * Return 1 (true) if the PCI device can be accessed by this controller.
  232. *
  233. * Return: 1 on valid, 0 on invalid
  234. */
  235. static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
  236. {
  237. if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
  238. return 0;
  239. if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
  240. return 0;
  241. return 1;
  242. }
  243. /**
  244. * pcie_dw_ti_read_config() - Read from configuration space
  245. *
  246. * @bus: Pointer to the PCI bus
  247. * @bdf: Identifies the PCIe device to access
  248. * @offset: The offset into the device's configuration space
  249. * @valuep: A pointer at which to store the read value
  250. * @size: Indicates the size of access to perform
  251. *
  252. * Read a value of size @size from offset @offset within the configuration
  253. * space of the device identified by the bus, device & function numbers in @bdf
  254. * on the PCI bus @bus.
  255. *
  256. * Return: 0 on success
  257. */
  258. static int pcie_dw_ti_read_config(const struct udevice *bus, pci_dev_t bdf,
  259. uint offset, ulong *valuep,
  260. enum pci_size_t size)
  261. {
  262. struct pcie_dw_ti *pcie = dev_get_priv(bus);
  263. uintptr_t va_address;
  264. ulong value;
  265. debug("PCIE CFG read: bdf=%2x:%2x:%2x ",
  266. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  267. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  268. debug("- out of range\n");
  269. *valuep = pci_get_ff(size);
  270. return 0;
  271. }
  272. va_address = set_cfg_address(pcie, bdf, offset);
  273. value = readl(va_address);
  274. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  275. *valuep = pci_conv_32_to_size(value, offset, size);
  276. pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
  277. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  278. pcie->io.bus_start, pcie->io.size);
  279. return 0;
  280. }
  281. /**
  282. * pcie_dw_ti_write_config() - Write to configuration space
  283. *
  284. * @bus: Pointer to the PCI bus
  285. * @bdf: Identifies the PCIe device to access
  286. * @offset: The offset into the device's configuration space
  287. * @value: The value to write
  288. * @size: Indicates the size of access to perform
  289. *
  290. * Write the value @value of size @size from offset @offset within the
  291. * configuration space of the device identified by the bus, device & function
  292. * numbers in @bdf on the PCI bus @bus.
  293. *
  294. * Return: 0 on success
  295. */
  296. static int pcie_dw_ti_write_config(struct udevice *bus, pci_dev_t bdf,
  297. uint offset, ulong value,
  298. enum pci_size_t size)
  299. {
  300. struct pcie_dw_ti *pcie = dev_get_priv(bus);
  301. uintptr_t va_address;
  302. ulong old;
  303. debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  304. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  305. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  306. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  307. debug("- out of range\n");
  308. return 0;
  309. }
  310. va_address = set_cfg_address(pcie, bdf, offset);
  311. old = readl(va_address);
  312. value = pci_conv_size_to_32(old, value, offset, size);
  313. writel(value, va_address);
  314. pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
  315. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  316. pcie->io.bus_start, pcie->io.size);
  317. return 0;
  318. }
  319. static inline void dw_pcie_dbi_write_enable(struct pcie_dw_ti *pci, bool en)
  320. {
  321. u32 val;
  322. val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
  323. if (en)
  324. val |= PCIE_DBI_RO_WR_EN;
  325. else
  326. val &= ~PCIE_DBI_RO_WR_EN;
  327. writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
  328. }
  329. /**
  330. * pcie_dw_configure() - Configure link capabilities and speed
  331. *
  332. * @regs_base: A pointer to the PCIe controller registers
  333. * @cap_speed: The capabilities and speed to configure
  334. *
  335. * Configure the link capabilities and speed in the PCIe root complex.
  336. */
  337. static void pcie_dw_configure(struct pcie_dw_ti *pci, u32 cap_speed)
  338. {
  339. u32 val;
  340. dw_pcie_dbi_write_enable(pci, true);
  341. val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY);
  342. val &= ~TARGET_LINK_SPEED_MASK;
  343. val |= cap_speed;
  344. writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY);
  345. val = readl(pci->dbi_base + PCIE_LINK_CTL_2);
  346. val &= ~TARGET_LINK_SPEED_MASK;
  347. val |= cap_speed;
  348. writel(val, pci->dbi_base + PCIE_LINK_CTL_2);
  349. dw_pcie_dbi_write_enable(pci, false);
  350. }
  351. /**
  352. * is_link_up() - Return the link state
  353. *
  354. * @regs_base: A pointer to the PCIe DBICS registers
  355. *
  356. * Return: 1 (true) for active line and 0 (false) for no link
  357. */
  358. static int is_link_up(struct pcie_dw_ti *pci)
  359. {
  360. u32 val;
  361. val = readl(pci->dbi_base + PCIE_PORT_DEBUG0);
  362. val &= PORT_LOGIC_LTSSM_STATE_MASK;
  363. return (val == PORT_LOGIC_LTSSM_STATE_L0);
  364. }
  365. /**
  366. * wait_link_up() - Wait for the link to come up
  367. *
  368. * @regs_base: A pointer to the PCIe controller registers
  369. *
  370. * Return: 1 (true) for active line and 0 (false) for no link (timeout)
  371. */
  372. static int wait_link_up(struct pcie_dw_ti *pci)
  373. {
  374. unsigned long timeout;
  375. timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
  376. while (!is_link_up(pci)) {
  377. if (get_timer(0) > timeout)
  378. return 0;
  379. };
  380. return 1;
  381. }
  382. static int pcie_dw_ti_pcie_link_up(struct pcie_dw_ti *pci, u32 cap_speed)
  383. {
  384. u32 val;
  385. if (is_link_up(pci)) {
  386. printf("PCI Link already up before configuration!\n");
  387. return 1;
  388. }
  389. /* DW pre link configurations */
  390. pcie_dw_configure(pci, cap_speed);
  391. /* Initiate link training */
  392. val = readl(pci->app_base + PCIE_CMD_STATUS);
  393. val |= LTSSM_EN_VAL;
  394. writel(val, pci->app_base + PCIE_CMD_STATUS);
  395. /* Check that link was established */
  396. if (!wait_link_up(pci))
  397. return 0;
  398. /*
  399. * Link can be established in Gen 1. still need to wait
  400. * till MAC nagaotiation is completed
  401. */
  402. udelay(100);
  403. return 1;
  404. }
  405. /**
  406. * pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion
  407. *
  408. * @pcie: Pointer to the PCI controller state
  409. *
  410. * Configure the host BARs of the PCIe controller root port so that
  411. * PCI(e) devices may access the system memory.
  412. */
  413. static void pcie_dw_setup_host(struct pcie_dw_ti *pci)
  414. {
  415. u32 val;
  416. /* setup RC BARs */
  417. writel(PCI_BASE_ADDRESS_MEM_TYPE_64,
  418. pci->dbi_base + PCI_BASE_ADDRESS_0);
  419. writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1);
  420. /* setup interrupt pins */
  421. dw_pcie_dbi_write_enable(pci, true);
  422. val = readl(pci->dbi_base + PCI_INTERRUPT_LINE);
  423. val &= 0xffff00ff;
  424. val |= 0x00000100;
  425. writel(val, pci->dbi_base + PCI_INTERRUPT_LINE);
  426. dw_pcie_dbi_write_enable(pci, false);
  427. /* setup bus numbers */
  428. val = readl(pci->dbi_base + PCI_PRIMARY_BUS);
  429. val &= 0xff000000;
  430. val |= 0x00ff0100;
  431. writel(val, pci->dbi_base + PCI_PRIMARY_BUS);
  432. /* setup command register */
  433. val = readl(pci->dbi_base + PCI_COMMAND);
  434. val &= 0xffff0000;
  435. val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  436. PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
  437. writel(val, pci->dbi_base + PCI_COMMAND);
  438. /* Enable write permission for the DBI read-only register */
  439. dw_pcie_dbi_write_enable(pci, true);
  440. /* program correct class for RC */
  441. writew(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
  442. /* Better disable write permission right after the update */
  443. dw_pcie_dbi_write_enable(pci, false);
  444. val = readl(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
  445. val |= PORT_LOGIC_SPEED_CHANGE;
  446. writel(val, pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
  447. }
  448. static int pcie_am654_set_mode(struct pcie_dw_ti *pci,
  449. enum dw_pcie_device_mode mode)
  450. {
  451. struct regmap *syscon;
  452. u32 val;
  453. u32 mask;
  454. int ret;
  455. syscon = syscon_regmap_lookup_by_phandle(pci->dev,
  456. "ti,syscon-pcie-mode");
  457. if (IS_ERR(syscon))
  458. return 0;
  459. mask = AM654_PCIE_DEV_TYPE_MASK;
  460. switch (mode) {
  461. case DW_PCIE_RC_TYPE:
  462. val = RC;
  463. break;
  464. case DW_PCIE_EP_TYPE:
  465. val = EP;
  466. break;
  467. default:
  468. dev_err(pci->dev, "INVALID device type %d\n", mode);
  469. return -EINVAL;
  470. }
  471. ret = regmap_update_bits(syscon, 0, mask, val);
  472. if (ret) {
  473. dev_err(pci->dev, "failed to set pcie mode\n");
  474. return ret;
  475. }
  476. return 0;
  477. }
  478. static int pcie_dw_init_id(struct pcie_dw_ti *pci)
  479. {
  480. struct regmap *devctrl_regs;
  481. unsigned int id;
  482. int ret;
  483. devctrl_regs = syscon_regmap_lookup_by_phandle(pci->dev,
  484. "ti,syscon-pcie-id");
  485. if (IS_ERR(devctrl_regs))
  486. return PTR_ERR(devctrl_regs);
  487. ret = regmap_read(devctrl_regs, 0, &id);
  488. if (ret)
  489. return ret;
  490. dw_pcie_dbi_write_enable(pci, true);
  491. writew(id & PCIE_VENDORID_MASK, pci->dbi_base + PCI_VENDOR_ID);
  492. writew(id >> PCIE_DEVICEID_SHIFT, pci->dbi_base + PCI_DEVICE_ID);
  493. dw_pcie_dbi_write_enable(pci, false);
  494. return 0;
  495. }
  496. /**
  497. * pcie_dw_ti_probe() - Probe the PCIe bus for active link
  498. *
  499. * @dev: A pointer to the device being operated on
  500. *
  501. * Probe for an active link on the PCIe bus and configure the controller
  502. * to enable this port.
  503. *
  504. * Return: 0 on success, else -ENODEV
  505. */
  506. static int pcie_dw_ti_probe(struct udevice *dev)
  507. {
  508. struct pcie_dw_ti *pci = dev_get_priv(dev);
  509. struct udevice *ctlr = pci_get_controller(dev);
  510. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  511. struct power_domain pci_pwrdmn;
  512. struct phy phy0, phy1;
  513. int ret;
  514. ret = power_domain_get_by_index(dev, &pci_pwrdmn, 0);
  515. if (ret) {
  516. dev_err(dev, "failed to get power domain\n");
  517. return ret;
  518. }
  519. ret = power_domain_on(&pci_pwrdmn);
  520. if (ret) {
  521. dev_err(dev, "Power domain on failed\n");
  522. return ret;
  523. }
  524. ret = generic_phy_get_by_name(dev, "pcie-phy0", &phy0);
  525. if (ret) {
  526. dev_err(dev, "Unable to get phy0");
  527. return ret;
  528. }
  529. generic_phy_reset(&phy0);
  530. generic_phy_init(&phy0);
  531. generic_phy_power_on(&phy0);
  532. ret = generic_phy_get_by_name(dev, "pcie-phy1", &phy1);
  533. if (ret) {
  534. dev_err(dev, "Unable to get phy1");
  535. return ret;
  536. }
  537. generic_phy_reset(&phy1);
  538. generic_phy_init(&phy1);
  539. generic_phy_power_on(&phy1);
  540. pci->first_busno = dev_seq(dev);
  541. pci->dev = dev;
  542. pcie_dw_setup_host(pci);
  543. pcie_dw_init_id(pci);
  544. if (device_is_compatible(dev, "ti,am654-pcie-rc"))
  545. pcie_am654_set_mode(pci, DW_PCIE_RC_TYPE);
  546. if (!pcie_dw_ti_pcie_link_up(pci, LINK_SPEED_GEN_2)) {
  547. printf("PCIE-%d: Link down\n", dev_seq(dev));
  548. return -ENODEV;
  549. }
  550. printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev),
  551. pcie_dw_get_link_speed(pci),
  552. pcie_dw_get_link_width(pci),
  553. hose->first_busno);
  554. /* Store the IO and MEM windows settings for future use by the ATU */
  555. pci->io.phys_start = hose->regions[0].phys_start; /* IO base */
  556. pci->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
  557. pci->io.size = hose->regions[0].size; /* IO size */
  558. pci->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
  559. pci->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
  560. pci->mem.size = hose->regions[1].size; /* MEM size */
  561. pcie_dw_prog_outbound_atu_unroll(pci, PCIE_ATU_REGION_INDEX0,
  562. PCIE_ATU_TYPE_MEM,
  563. pci->mem.phys_start,
  564. pci->mem.bus_start, pci->mem.size);
  565. return 0;
  566. }
  567. /**
  568. * pcie_dw_ti_of_to_plat() - Translate from DT to device state
  569. *
  570. * @dev: A pointer to the device being operated on
  571. *
  572. * Translate relevant data from the device tree pertaining to device @dev into
  573. * state that the driver will later make use of. This state is stored in the
  574. * device's private data structure.
  575. *
  576. * Return: 0 on success, else -EINVAL
  577. */
  578. static int pcie_dw_ti_of_to_plat(struct udevice *dev)
  579. {
  580. struct pcie_dw_ti *pcie = dev_get_priv(dev);
  581. /* Get the controller base address */
  582. pcie->dbi_base = (void *)dev_read_addr_name(dev, "dbics");
  583. if ((fdt_addr_t)pcie->dbi_base == FDT_ADDR_T_NONE)
  584. return -EINVAL;
  585. /* Get the config space base address and size */
  586. pcie->cfg_base = (void *)dev_read_addr_size_name(dev, "config",
  587. &pcie->cfg_size);
  588. if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
  589. return -EINVAL;
  590. /* Get the iATU base address and size */
  591. pcie->atu_base = (void *)dev_read_addr_name(dev, "atu");
  592. if ((fdt_addr_t)pcie->atu_base == FDT_ADDR_T_NONE)
  593. return -EINVAL;
  594. /* Get the app base address and size */
  595. pcie->app_base = (void *)dev_read_addr_name(dev, "app");
  596. if ((fdt_addr_t)pcie->app_base == FDT_ADDR_T_NONE)
  597. return -EINVAL;
  598. return 0;
  599. }
  600. static const struct dm_pci_ops pcie_dw_ti_ops = {
  601. .read_config = pcie_dw_ti_read_config,
  602. .write_config = pcie_dw_ti_write_config,
  603. };
  604. static const struct udevice_id pcie_dw_ti_ids[] = {
  605. { .compatible = "ti,am654-pcie-rc" },
  606. { }
  607. };
  608. U_BOOT_DRIVER(pcie_dw_ti) = {
  609. .name = "pcie_dw_ti",
  610. .id = UCLASS_PCI,
  611. .of_match = pcie_dw_ti_ids,
  612. .ops = &pcie_dw_ti_ops,
  613. .of_to_plat = pcie_dw_ti_of_to_plat,
  614. .probe = pcie_dw_ti_probe,
  615. .priv_auto = sizeof(struct pcie_dw_ti),
  616. };