pcie_dw_mvebu.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Marvell International Ltd.
  4. *
  5. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  6. *
  7. * Based on:
  8. * - drivers/pci/pcie_imx.c
  9. * - drivers/pci/pci_mvebu.c
  10. * - drivers/pci/pcie_xilinx.c
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <log.h>
  15. #include <pci.h>
  16. #include <asm/io.h>
  17. #include <asm-generic/gpio.h>
  18. #include <linux/delay.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /* PCI Config space registers */
  21. #define PCIE_CONFIG_BAR0 0x10
  22. #define PCIE_LINK_STATUS_REG 0x80
  23. #define PCIE_LINK_STATUS_SPEED_OFF 16
  24. #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
  25. #define PCIE_LINK_STATUS_WIDTH_OFF 20
  26. #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
  27. /* Resizable bar capability registers */
  28. #define RESIZABLE_BAR_CAP 0x250
  29. #define RESIZABLE_BAR_CTL0 0x254
  30. #define RESIZABLE_BAR_CTL1 0x258
  31. /* iATU registers */
  32. #define PCIE_ATU_VIEWPORT 0x900
  33. #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
  34. #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
  35. #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  36. #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  37. #define PCIE_ATU_CR1 0x904
  38. #define PCIE_ATU_TYPE_MEM (0x0 << 0)
  39. #define PCIE_ATU_TYPE_IO (0x2 << 0)
  40. #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  41. #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  42. #define PCIE_ATU_CR2 0x908
  43. #define PCIE_ATU_ENABLE (0x1 << 31)
  44. #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  45. #define PCIE_ATU_LOWER_BASE 0x90C
  46. #define PCIE_ATU_UPPER_BASE 0x910
  47. #define PCIE_ATU_LIMIT 0x914
  48. #define PCIE_ATU_LOWER_TARGET 0x918
  49. #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
  50. #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
  51. #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
  52. #define PCIE_ATU_UPPER_TARGET 0x91C
  53. #define PCIE_LINK_CAPABILITY 0x7C
  54. #define PCIE_LINK_CTL_2 0xA0
  55. #define TARGET_LINK_SPEED_MASK 0xF
  56. #define LINK_SPEED_GEN_1 0x1
  57. #define LINK_SPEED_GEN_2 0x2
  58. #define LINK_SPEED_GEN_3 0x3
  59. #define PCIE_GEN3_RELATED 0x890
  60. #define GEN3_EQU_DISABLE (1 << 16)
  61. #define GEN3_ZRXDC_NON_COMP (1 << 0)
  62. #define PCIE_GEN3_EQU_CTRL 0x8A8
  63. #define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
  64. #define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4)
  65. #define PCIE_LINK_UP_TIMEOUT_MS 100
  66. #define PCIE_GLOBAL_CONTROL 0x8000
  67. #define PCIE_APP_LTSSM_EN (1 << 2)
  68. #define PCIE_DEVICE_TYPE_OFFSET (4)
  69. #define PCIE_DEVICE_TYPE_MASK (0xF)
  70. #define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */
  71. #define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */
  72. #define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */
  73. #define PCIE_GLOBAL_STATUS 0x8008
  74. #define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
  75. #define PCIE_GLB_STS_PHY_LINK_UP (1 << 9)
  76. #define PCIE_ARCACHE_TRC 0x8050
  77. #define PCIE_AWCACHE_TRC 0x8054
  78. #define ARCACHE_SHAREABLE_CACHEABLE 0x3511
  79. #define AWCACHE_SHAREABLE_CACHEABLE 0x5311
  80. #define LINK_SPEED_GEN_1 0x1
  81. #define LINK_SPEED_GEN_2 0x2
  82. #define LINK_SPEED_GEN_3 0x3
  83. /**
  84. * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
  85. *
  86. * @ctrl_base: The base address of the register space
  87. * @cfg_base: The base address of the configuration space
  88. * @cfg_size: The size of the configuration space which is needed
  89. * as it gets written into the PCIE_ATU_LIMIT register
  90. * @first_busno: This driver supports multiple PCIe controllers.
  91. * first_busno stores the bus number of the PCIe root-port
  92. * number which may vary depending on the PCIe setup
  93. * (PEX switches etc).
  94. */
  95. struct pcie_dw_mvebu {
  96. void *ctrl_base;
  97. void *cfg_base;
  98. fdt_size_t cfg_size;
  99. int first_busno;
  100. /* IO and MEM PCI regions */
  101. struct pci_region io;
  102. struct pci_region mem;
  103. };
  104. static int pcie_dw_get_link_speed(const void *regs_base)
  105. {
  106. return (readl(regs_base + PCIE_LINK_STATUS_REG) &
  107. PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
  108. }
  109. static int pcie_dw_get_link_width(const void *regs_base)
  110. {
  111. return (readl(regs_base + PCIE_LINK_STATUS_REG) &
  112. PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
  113. }
  114. /**
  115. * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
  116. *
  117. * @pcie: Pointer to the PCI controller state
  118. * @index: ATU region index
  119. * @type: ATU accsess type
  120. * @cpu_addr: the physical address for the translation entry
  121. * @pci_addr: the pcie bus address for the translation entry
  122. * @size: the size of the translation entry
  123. */
  124. static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
  125. int type, u64 cpu_addr, u64 pci_addr,
  126. u32 size)
  127. {
  128. writel(PCIE_ATU_REGION_OUTBOUND | index,
  129. pcie->ctrl_base + PCIE_ATU_VIEWPORT);
  130. writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
  131. writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
  132. writel(lower_32_bits(cpu_addr + size - 1),
  133. pcie->ctrl_base + PCIE_ATU_LIMIT);
  134. writel(lower_32_bits(pci_addr),
  135. pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
  136. writel(upper_32_bits(pci_addr),
  137. pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
  138. writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
  139. writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
  140. }
  141. /**
  142. * set_cfg_address() - Configure the PCIe controller config space access
  143. *
  144. * @pcie: Pointer to the PCI controller state
  145. * @d: PCI device to access
  146. * @where: Offset in the configuration space
  147. *
  148. * Configures the PCIe controller to access the configuration space of
  149. * a specific PCIe device and returns the address to use for this
  150. * access.
  151. *
  152. * Return: Address that can be used to access the configation space
  153. * of the requested device / offset
  154. */
  155. static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
  156. pci_dev_t d, uint where)
  157. {
  158. uintptr_t va_address;
  159. u32 atu_type;
  160. /*
  161. * Region #0 is used for Outbound CFG space access.
  162. * Direction = Outbound
  163. * Region Index = 0
  164. */
  165. if (PCI_BUS(d) == (pcie->first_busno + 1))
  166. /* For local bus, change TLP Type field to 4. */
  167. atu_type = PCIE_ATU_TYPE_CFG0;
  168. else
  169. /* Otherwise, change TLP Type field to 5. */
  170. atu_type = PCIE_ATU_TYPE_CFG1;
  171. if (PCI_BUS(d) == pcie->first_busno) {
  172. /* Accessing root port configuration space. */
  173. va_address = (uintptr_t)pcie->ctrl_base;
  174. } else {
  175. d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
  176. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
  177. atu_type, (u64)pcie->cfg_base,
  178. d << 8, pcie->cfg_size);
  179. va_address = (uintptr_t)pcie->cfg_base;
  180. }
  181. va_address += where & ~0x3;
  182. return va_address;
  183. }
  184. /**
  185. * pcie_dw_addr_valid() - Check for valid bus address
  186. *
  187. * @d: The PCI device to access
  188. * @first_busno: Bus number of the PCIe controller root complex
  189. *
  190. * Return 1 (true) if the PCI device can be accessed by this controller.
  191. *
  192. * Return: 1 on valid, 0 on invalid
  193. */
  194. static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
  195. {
  196. if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
  197. return 0;
  198. if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
  199. return 0;
  200. return 1;
  201. }
  202. /**
  203. * pcie_dw_mvebu_read_config() - Read from configuration space
  204. *
  205. * @bus: Pointer to the PCI bus
  206. * @bdf: Identifies the PCIe device to access
  207. * @offset: The offset into the device's configuration space
  208. * @valuep: A pointer at which to store the read value
  209. * @size: Indicates the size of access to perform
  210. *
  211. * Read a value of size @size from offset @offset within the configuration
  212. * space of the device identified by the bus, device & function numbers in @bdf
  213. * on the PCI bus @bus.
  214. *
  215. * Return: 0 on success
  216. */
  217. static int pcie_dw_mvebu_read_config(const struct udevice *bus, pci_dev_t bdf,
  218. uint offset, ulong *valuep,
  219. enum pci_size_t size)
  220. {
  221. struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
  222. uintptr_t va_address;
  223. ulong value;
  224. debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
  225. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  226. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  227. debug("- out of range\n");
  228. *valuep = pci_get_ff(size);
  229. return 0;
  230. }
  231. va_address = set_cfg_address(pcie, bdf, offset);
  232. value = readl(va_address);
  233. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  234. *valuep = pci_conv_32_to_size(value, offset, size);
  235. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
  236. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  237. pcie->io.bus_start, pcie->io.size);
  238. return 0;
  239. }
  240. /**
  241. * pcie_dw_mvebu_write_config() - Write to configuration space
  242. *
  243. * @bus: Pointer to the PCI bus
  244. * @bdf: Identifies the PCIe device to access
  245. * @offset: The offset into the device's configuration space
  246. * @value: The value to write
  247. * @size: Indicates the size of access to perform
  248. *
  249. * Write the value @value of size @size from offset @offset within the
  250. * configuration space of the device identified by the bus, device & function
  251. * numbers in @bdf on the PCI bus @bus.
  252. *
  253. * Return: 0 on success
  254. */
  255. static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
  256. uint offset, ulong value,
  257. enum pci_size_t size)
  258. {
  259. struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
  260. uintptr_t va_address;
  261. ulong old;
  262. debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  263. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  264. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  265. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  266. debug("- out of range\n");
  267. return 0;
  268. }
  269. va_address = set_cfg_address(pcie, bdf, offset);
  270. old = readl(va_address);
  271. value = pci_conv_size_to_32(old, value, offset, size);
  272. writel(value, va_address);
  273. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
  274. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  275. pcie->io.bus_start, pcie->io.size);
  276. return 0;
  277. }
  278. /**
  279. * pcie_dw_configure() - Configure link capabilities and speed
  280. *
  281. * @regs_base: A pointer to the PCIe controller registers
  282. * @cap_speed: The capabilities and speed to configure
  283. *
  284. * Configure the link capabilities and speed in the PCIe root complex.
  285. */
  286. static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
  287. {
  288. /*
  289. * TODO (shadi@marvell.com, sr@denx.de):
  290. * Need to read the serdes speed from the dts and according to it
  291. * configure the PCIe gen
  292. */
  293. /* Set link to GEN 3 */
  294. clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
  295. TARGET_LINK_SPEED_MASK, cap_speed);
  296. clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
  297. TARGET_LINK_SPEED_MASK, cap_speed);
  298. setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
  299. }
  300. /**
  301. * is_link_up() - Return the link state
  302. *
  303. * @regs_base: A pointer to the PCIe controller registers
  304. *
  305. * Return: 1 (true) for active line and 0 (false) for no link
  306. */
  307. static int is_link_up(const void *regs_base)
  308. {
  309. u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
  310. u32 reg;
  311. reg = readl(regs_base + PCIE_GLOBAL_STATUS);
  312. if ((reg & mask) == mask)
  313. return 1;
  314. return 0;
  315. }
  316. /**
  317. * wait_link_up() - Wait for the link to come up
  318. *
  319. * @regs_base: A pointer to the PCIe controller registers
  320. *
  321. * Return: 1 (true) for active line and 0 (false) for no link (timeout)
  322. */
  323. static int wait_link_up(const void *regs_base)
  324. {
  325. unsigned long timeout;
  326. timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
  327. while (!is_link_up(regs_base)) {
  328. if (get_timer(0) > timeout)
  329. return 0;
  330. };
  331. return 1;
  332. }
  333. /**
  334. * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
  335. *
  336. * @regs_base: A pointer to the PCIe controller registers
  337. * @cap_speed: The capabilities and speed to configure
  338. *
  339. * Configure the PCIe controller root complex depending on the
  340. * requested link capabilities and speed.
  341. *
  342. * Return: 1 (true) for active line and 0 (false) for no link
  343. */
  344. static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
  345. {
  346. if (!is_link_up(regs_base)) {
  347. /* Disable LTSSM state machine to enable configuration */
  348. clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
  349. PCIE_APP_LTSSM_EN);
  350. }
  351. clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
  352. PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
  353. PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);
  354. /* Set the PCIe master AXI attributes */
  355. writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
  356. writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);
  357. /* DW pre link configurations */
  358. pcie_dw_configure(regs_base, cap_speed);
  359. if (!is_link_up(regs_base)) {
  360. /* Configuration done. Start LTSSM */
  361. setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
  362. PCIE_APP_LTSSM_EN);
  363. }
  364. /* Check that link was established */
  365. if (!wait_link_up(regs_base))
  366. return 0;
  367. /*
  368. * Link can be established in Gen 1. still need to wait
  369. * till MAC nagaotiation is completed
  370. */
  371. udelay(100);
  372. return 1;
  373. }
  374. /**
  375. * pcie_dw_set_host_bars() - Configure the host BARs
  376. *
  377. * @regs_base: A pointer to the PCIe controller registers
  378. *
  379. * Configure the host BARs of the PCIe controller root port so that
  380. * PCI(e) devices may access the system memory.
  381. */
  382. static void pcie_dw_set_host_bars(const void *regs_base)
  383. {
  384. u32 size = gd->ram_size;
  385. u64 max_size;
  386. u32 reg;
  387. u32 bar0;
  388. /* Verify the maximal BAR size */
  389. reg = readl(regs_base + RESIZABLE_BAR_CAP);
  390. max_size = 1ULL << (5 + (reg + (1 << 4)));
  391. if (size > max_size) {
  392. size = max_size;
  393. printf("Warning: PCIe BARs can't map all DRAM space\n");
  394. }
  395. /* Set the BAR base and size towards DDR */
  396. bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
  397. bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
  398. writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
  399. reg = ((size >> 20) - 1) << 12;
  400. writel(size, regs_base + RESIZABLE_BAR_CTL0);
  401. }
  402. /**
  403. * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
  404. *
  405. * @dev: A pointer to the device being operated on
  406. *
  407. * Probe for an active link on the PCIe bus and configure the controller
  408. * to enable this port.
  409. *
  410. * Return: 0 on success, else -ENODEV
  411. */
  412. static int pcie_dw_mvebu_probe(struct udevice *dev)
  413. {
  414. struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
  415. struct udevice *ctlr = pci_get_controller(dev);
  416. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  417. #if CONFIG_IS_ENABLED(DM_GPIO)
  418. struct gpio_desc reset_gpio;
  419. gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
  420. GPIOD_IS_OUT);
  421. /*
  422. * Issue reset to add-in card trough the dedicated GPIO.
  423. * Some boards are connecting the card reset pin to common system
  424. * reset wire and others are using separate GPIO port.
  425. * In the last case we have to release a reset of the addon card
  426. * using this GPIO.
  427. */
  428. if (dm_gpio_is_valid(&reset_gpio)) {
  429. dm_gpio_set_value(&reset_gpio, 1); /* assert */
  430. mdelay(200);
  431. dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
  432. mdelay(200);
  433. }
  434. #else
  435. debug("PCIE Reset on GPIO support is missing\n");
  436. #endif /* DM_GPIO */
  437. pcie->first_busno = dev_seq(dev);
  438. /* Don't register host if link is down */
  439. if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
  440. printf("PCIE-%d: Link down\n", dev_seq(dev));
  441. } else {
  442. printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev),
  443. pcie_dw_get_link_speed(pcie->ctrl_base),
  444. pcie_dw_get_link_width(pcie->ctrl_base),
  445. hose->first_busno);
  446. }
  447. /* Store the IO and MEM windows settings for future use by the ATU */
  448. pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
  449. pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
  450. pcie->io.size = hose->regions[0].size; /* IO size */
  451. pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
  452. pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
  453. pcie->mem.size = hose->regions[1].size; /* MEM size */
  454. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
  455. PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
  456. pcie->mem.bus_start, pcie->mem.size);
  457. /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
  458. clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
  459. 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
  460. pcie_dw_set_host_bars(pcie->ctrl_base);
  461. return 0;
  462. }
  463. /**
  464. * pcie_dw_mvebu_of_to_plat() - Translate from DT to device state
  465. *
  466. * @dev: A pointer to the device being operated on
  467. *
  468. * Translate relevant data from the device tree pertaining to device @dev into
  469. * state that the driver will later make use of. This state is stored in the
  470. * device's private data structure.
  471. *
  472. * Return: 0 on success, else -EINVAL
  473. */
  474. static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
  475. {
  476. struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
  477. /* Get the controller base address */
  478. pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);
  479. if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
  480. return -EINVAL;
  481. /* Get the config space base address and size */
  482. pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
  483. &pcie->cfg_size);
  484. if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
  485. return -EINVAL;
  486. return 0;
  487. }
  488. static const struct dm_pci_ops pcie_dw_mvebu_ops = {
  489. .read_config = pcie_dw_mvebu_read_config,
  490. .write_config = pcie_dw_mvebu_write_config,
  491. };
  492. static const struct udevice_id pcie_dw_mvebu_ids[] = {
  493. { .compatible = "marvell,armada8k-pcie" },
  494. { }
  495. };
  496. U_BOOT_DRIVER(pcie_dw_mvebu) = {
  497. .name = "pcie_dw_mvebu",
  498. .id = UCLASS_PCI,
  499. .of_match = pcie_dw_mvebu_ids,
  500. .ops = &pcie_dw_mvebu_ops,
  501. .of_to_plat = pcie_dw_mvebu_of_to_plat,
  502. .probe = pcie_dw_mvebu_probe,
  503. .priv_auto = sizeof(struct pcie_dw_mvebu),
  504. };