pci-aardvark.c 20 KB

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  1. /*
  2. * ***************************************************************************
  3. * Copyright (C) 2015 Marvell International Ltd.
  4. * ***************************************************************************
  5. * This program is free software: you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation, either version 2 of the License, or any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  16. * ***************************************************************************
  17. */
  18. /* pcie_advk.c
  19. *
  20. * Ported from Linux driver - driver/pci/host/pci-aardvark.c
  21. *
  22. * Author: Victor Gu <xigu@marvell.com>
  23. * Hezi Shahmoon <hezi.shahmoon@marvell.com>
  24. *
  25. */
  26. #include <common.h>
  27. #include <dm.h>
  28. #include <pci.h>
  29. #include <asm/io.h>
  30. #include <asm-generic/gpio.h>
  31. #include <dm/device_compat.h>
  32. #include <linux/bitops.h>
  33. #include <linux/delay.h>
  34. #include <linux/ioport.h>
  35. /* PCIe core registers */
  36. #define PCIE_CORE_CMD_STATUS_REG 0x4
  37. #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
  38. #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
  39. #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
  40. #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
  41. #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
  42. #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
  43. #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
  44. #define PCIE_CORE_LINK_TRAINING BIT(5)
  45. #define PCIE_CORE_ERR_CAPCTL_REG 0x118
  46. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
  47. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
  48. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
  49. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
  50. /* PIO registers base address and register offsets */
  51. #define PIO_BASE_ADDR 0x4000
  52. #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
  53. #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
  54. #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
  55. #define PIO_STAT (PIO_BASE_ADDR + 0x4)
  56. #define PIO_COMPLETION_STATUS_SHIFT 7
  57. #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
  58. #define PIO_COMPLETION_STATUS_OK 0
  59. #define PIO_COMPLETION_STATUS_UR 1
  60. #define PIO_COMPLETION_STATUS_CRS 2
  61. #define PIO_COMPLETION_STATUS_CA 4
  62. #define PIO_NON_POSTED_REQ BIT(10)
  63. #define PIO_ERR_STATUS BIT(11)
  64. #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
  65. #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
  66. #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
  67. #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
  68. #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
  69. #define PIO_START (PIO_BASE_ADDR + 0x1c)
  70. #define PIO_ISR (PIO_BASE_ADDR + 0x20)
  71. /* Aardvark Control registers */
  72. #define CONTROL_BASE_ADDR 0x4800
  73. #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
  74. #define PCIE_GEN_SEL_MSK 0x3
  75. #define PCIE_GEN_SEL_SHIFT 0x0
  76. #define SPEED_GEN_1 0
  77. #define SPEED_GEN_2 1
  78. #define SPEED_GEN_3 2
  79. #define IS_RC_MSK 1
  80. #define IS_RC_SHIFT 2
  81. #define LANE_CNT_MSK 0x18
  82. #define LANE_CNT_SHIFT 0x3
  83. #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
  84. #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
  85. #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
  86. #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
  87. #define LINK_TRAINING_EN BIT(6)
  88. #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
  89. #define PCIE_CORE_CTRL2_RESERVED 0x7
  90. #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
  91. #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
  92. #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
  93. /* LMI registers base address and register offsets */
  94. #define LMI_BASE_ADDR 0x6000
  95. #define CFG_REG (LMI_BASE_ADDR + 0x0)
  96. #define LTSSM_SHIFT 24
  97. #define LTSSM_MASK 0x3f
  98. #define LTSSM_L0 0x10
  99. /* PCIe core controller registers */
  100. #define CTRL_CORE_BASE_ADDR 0x18000
  101. #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
  102. #define CTRL_MODE_SHIFT 0x0
  103. #define CTRL_MODE_MASK 0x1
  104. #define PCIE_CORE_MODE_DIRECT 0x0
  105. #define PCIE_CORE_MODE_COMMAND 0x1
  106. /* Transaction types */
  107. #define PCIE_CONFIG_RD_TYPE0 0x8
  108. #define PCIE_CONFIG_RD_TYPE1 0x9
  109. #define PCIE_CONFIG_WR_TYPE0 0xa
  110. #define PCIE_CONFIG_WR_TYPE1 0xb
  111. /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
  112. #define PCIE_BDF(dev) (dev << 4)
  113. #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
  114. #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
  115. #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
  116. #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
  117. #define PCIE_CONF_ADDR(bus, devfn, where) \
  118. (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
  119. PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
  120. /* PCIe Retries & Timeout definitions */
  121. #define MAX_RETRIES 10
  122. #define PIO_WAIT_TIMEOUT 100
  123. #define LINK_WAIT_TIMEOUT 100000
  124. #define CFG_RD_UR_VAL 0xFFFFFFFF
  125. #define CFG_RD_CRS_VAL 0xFFFF0001
  126. /**
  127. * struct pcie_advk - Advk PCIe controller state
  128. *
  129. * @reg_base: The base address of the register space.
  130. * @first_busno: This driver supports multiple PCIe controllers.
  131. * first_busno stores the bus number of the PCIe root-port
  132. * number which may vary depending on the PCIe setup
  133. * (PEX switches etc).
  134. * @device: The pointer to PCI uclass device.
  135. */
  136. struct pcie_advk {
  137. void *base;
  138. int first_busno;
  139. struct udevice *dev;
  140. struct gpio_desc reset_gpio;
  141. };
  142. static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
  143. {
  144. writel(val, pcie->base + reg);
  145. }
  146. static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
  147. {
  148. return readl(pcie->base + reg);
  149. }
  150. /**
  151. * pcie_advk_addr_valid() - Check for valid bus address
  152. *
  153. * @bdf: The PCI device to access
  154. * @first_busno: Bus number of the PCIe controller root complex
  155. *
  156. * Return: 1 on valid, 0 on invalid
  157. */
  158. static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
  159. {
  160. /*
  161. * In PCIE-E only a single device (0) can exist
  162. * on the local bus. Beyound the local bus, there might be
  163. * a Switch and everything is possible.
  164. */
  165. if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
  166. return 0;
  167. return 1;
  168. }
  169. /**
  170. * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
  171. *
  172. * @pcie: The PCI device to access
  173. *
  174. * Wait up to 1 micro second for PIO access to be accomplished.
  175. *
  176. * Return 1 (true) if PIO access is accomplished.
  177. * Return 0 (false) if PIO access is timed out.
  178. */
  179. static int pcie_advk_wait_pio(struct pcie_advk *pcie)
  180. {
  181. uint start, isr;
  182. uint count;
  183. for (count = 0; count < MAX_RETRIES; count++) {
  184. start = advk_readl(pcie, PIO_START);
  185. isr = advk_readl(pcie, PIO_ISR);
  186. if (!start && isr)
  187. return 1;
  188. /*
  189. * Do not check the PIO state too frequently,
  190. * 100us delay is appropriate.
  191. */
  192. udelay(PIO_WAIT_TIMEOUT);
  193. }
  194. dev_err(pcie->dev, "config read/write timed out\n");
  195. return 0;
  196. }
  197. /**
  198. * pcie_advk_check_pio_status() - Validate PIO status and get the read result
  199. *
  200. * @pcie: Pointer to the PCI bus
  201. * @read: Read from or write to configuration space - true(read) false(write)
  202. * @read_val: Pointer to the read result, only valid when read is true
  203. *
  204. */
  205. static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
  206. bool read,
  207. uint *read_val)
  208. {
  209. uint reg;
  210. unsigned int status;
  211. char *strcomp_status, *str_posted;
  212. reg = advk_readl(pcie, PIO_STAT);
  213. status = (reg & PIO_COMPLETION_STATUS_MASK) >>
  214. PIO_COMPLETION_STATUS_SHIFT;
  215. switch (status) {
  216. case PIO_COMPLETION_STATUS_OK:
  217. if (reg & PIO_ERR_STATUS) {
  218. strcomp_status = "COMP_ERR";
  219. break;
  220. }
  221. /* Get the read result */
  222. if (read)
  223. *read_val = advk_readl(pcie, PIO_RD_DATA);
  224. /* No error */
  225. strcomp_status = NULL;
  226. break;
  227. case PIO_COMPLETION_STATUS_UR:
  228. if (read) {
  229. /* For reading, UR is not an error status. */
  230. *read_val = CFG_RD_UR_VAL;
  231. strcomp_status = NULL;
  232. } else {
  233. strcomp_status = "UR";
  234. }
  235. break;
  236. case PIO_COMPLETION_STATUS_CRS:
  237. if (read) {
  238. /* For reading, CRS is not an error status. */
  239. *read_val = CFG_RD_CRS_VAL;
  240. strcomp_status = NULL;
  241. } else {
  242. strcomp_status = "CRS";
  243. }
  244. break;
  245. case PIO_COMPLETION_STATUS_CA:
  246. strcomp_status = "CA";
  247. break;
  248. default:
  249. strcomp_status = "Unknown";
  250. break;
  251. }
  252. if (!strcomp_status)
  253. return 0;
  254. if (reg & PIO_NON_POSTED_REQ)
  255. str_posted = "Non-posted";
  256. else
  257. str_posted = "Posted";
  258. dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
  259. str_posted, strcomp_status, reg,
  260. advk_readl(pcie, PIO_ADDR_LS));
  261. return -EFAULT;
  262. }
  263. /**
  264. * pcie_advk_read_config() - Read from configuration space
  265. *
  266. * @bus: Pointer to the PCI bus
  267. * @bdf: Identifies the PCIe device to access
  268. * @offset: The offset into the device's configuration space
  269. * @valuep: A pointer at which to store the read value
  270. * @size: Indicates the size of access to perform
  271. *
  272. * Read a value of size @size from offset @offset within the configuration
  273. * space of the device identified by the bus, device & function numbers in @bdf
  274. * on the PCI bus @bus.
  275. *
  276. * Return: 0 on success
  277. */
  278. static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
  279. uint offset, ulong *valuep,
  280. enum pci_size_t size)
  281. {
  282. struct pcie_advk *pcie = dev_get_priv(bus);
  283. uint reg;
  284. int ret;
  285. dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
  286. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  287. if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
  288. dev_dbg(pcie->dev, "- out of range\n");
  289. *valuep = pci_get_ff(size);
  290. return 0;
  291. }
  292. /* Start PIO */
  293. advk_writel(pcie, 0, PIO_START);
  294. advk_writel(pcie, 1, PIO_ISR);
  295. /* Program the control register */
  296. reg = advk_readl(pcie, PIO_CTRL);
  297. reg &= ~PIO_CTRL_TYPE_MASK;
  298. if (PCI_BUS(bdf) == pcie->first_busno)
  299. reg |= PCIE_CONFIG_RD_TYPE0;
  300. else
  301. reg |= PCIE_CONFIG_RD_TYPE1;
  302. advk_writel(pcie, reg, PIO_CTRL);
  303. /* Program the address registers */
  304. reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
  305. advk_writel(pcie, reg, PIO_ADDR_LS);
  306. advk_writel(pcie, 0, PIO_ADDR_MS);
  307. /* Start the transfer */
  308. advk_writel(pcie, 1, PIO_START);
  309. if (!pcie_advk_wait_pio(pcie))
  310. return -EINVAL;
  311. /* Check PIO status and get the read result */
  312. ret = pcie_advk_check_pio_status(pcie, true, &reg);
  313. if (ret)
  314. return ret;
  315. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
  316. offset, size, reg);
  317. *valuep = pci_conv_32_to_size(reg, offset, size);
  318. return 0;
  319. }
  320. /**
  321. * pcie_calc_datastrobe() - Calculate data strobe
  322. *
  323. * @offset: The offset into the device's configuration space
  324. * @size: Indicates the size of access to perform
  325. *
  326. * Calculate data strobe according to offset and size
  327. *
  328. */
  329. static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
  330. {
  331. uint bytes, data_strobe;
  332. switch (size) {
  333. case PCI_SIZE_8:
  334. bytes = 1;
  335. break;
  336. case PCI_SIZE_16:
  337. bytes = 2;
  338. break;
  339. default:
  340. bytes = 4;
  341. }
  342. data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
  343. return data_strobe;
  344. }
  345. /**
  346. * pcie_advk_write_config() - Write to configuration space
  347. *
  348. * @bus: Pointer to the PCI bus
  349. * @bdf: Identifies the PCIe device to access
  350. * @offset: The offset into the device's configuration space
  351. * @value: The value to write
  352. * @size: Indicates the size of access to perform
  353. *
  354. * Write the value @value of size @size from offset @offset within the
  355. * configuration space of the device identified by the bus, device & function
  356. * numbers in @bdf on the PCI bus @bus.
  357. *
  358. * Return: 0 on success
  359. */
  360. static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
  361. uint offset, ulong value,
  362. enum pci_size_t size)
  363. {
  364. struct pcie_advk *pcie = dev_get_priv(bus);
  365. uint reg;
  366. dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  367. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  368. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
  369. offset, size, value);
  370. if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
  371. dev_dbg(pcie->dev, "- out of range\n");
  372. return 0;
  373. }
  374. /* Start PIO */
  375. advk_writel(pcie, 0, PIO_START);
  376. advk_writel(pcie, 1, PIO_ISR);
  377. /* Program the control register */
  378. reg = advk_readl(pcie, PIO_CTRL);
  379. reg &= ~PIO_CTRL_TYPE_MASK;
  380. if (PCI_BUS(bdf) == pcie->first_busno)
  381. reg |= PCIE_CONFIG_WR_TYPE0;
  382. else
  383. reg |= PCIE_CONFIG_WR_TYPE1;
  384. advk_writel(pcie, reg, PIO_CTRL);
  385. /* Program the address registers */
  386. reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
  387. advk_writel(pcie, reg, PIO_ADDR_LS);
  388. advk_writel(pcie, 0, PIO_ADDR_MS);
  389. dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
  390. /* Program the data register */
  391. reg = pci_conv_size_to_32(0, value, offset, size);
  392. advk_writel(pcie, reg, PIO_WR_DATA);
  393. dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
  394. /* Program the data strobe */
  395. reg = pcie_calc_datastrobe(offset, size);
  396. advk_writel(pcie, reg, PIO_WR_DATA_STRB);
  397. dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
  398. /* Start the transfer */
  399. advk_writel(pcie, 1, PIO_START);
  400. if (!pcie_advk_wait_pio(pcie)) {
  401. dev_dbg(pcie->dev, "- wait pio timeout\n");
  402. return -EINVAL;
  403. }
  404. /* Check PIO status */
  405. pcie_advk_check_pio_status(pcie, false, &reg);
  406. return 0;
  407. }
  408. /**
  409. * pcie_advk_link_up() - Check if PCIe link is up or not
  410. *
  411. * @pcie: The PCI device to access
  412. *
  413. * Return 1 (true) on link up.
  414. * Return 0 (false) on link down.
  415. */
  416. static int pcie_advk_link_up(struct pcie_advk *pcie)
  417. {
  418. u32 val, ltssm_state;
  419. val = advk_readl(pcie, CFG_REG);
  420. ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
  421. return ltssm_state >= LTSSM_L0;
  422. }
  423. /**
  424. * pcie_advk_wait_for_link() - Wait for link training to be accomplished
  425. *
  426. * @pcie: The PCI device to access
  427. *
  428. * Wait up to 1 second for link training to be accomplished.
  429. *
  430. * Return 1 (true) if link training ends up with link up success.
  431. * Return 0 (false) if link training ends up with link up failure.
  432. */
  433. static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
  434. {
  435. int retries;
  436. /* check if the link is up or not */
  437. for (retries = 0; retries < MAX_RETRIES; retries++) {
  438. if (pcie_advk_link_up(pcie)) {
  439. printf("PCIE-%d: Link up\n", pcie->first_busno);
  440. return 0;
  441. }
  442. udelay(LINK_WAIT_TIMEOUT);
  443. }
  444. printf("PCIE-%d: Link down\n", pcie->first_busno);
  445. return -ETIMEDOUT;
  446. }
  447. /**
  448. * pcie_advk_setup_hw() - PCIe initailzation
  449. *
  450. * @pcie: The PCI device to access
  451. *
  452. * Return: 0 on success
  453. */
  454. static int pcie_advk_setup_hw(struct pcie_advk *pcie)
  455. {
  456. u32 reg;
  457. /* Set to Direct mode */
  458. reg = advk_readl(pcie, CTRL_CONFIG_REG);
  459. reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
  460. reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
  461. advk_writel(pcie, reg, CTRL_CONFIG_REG);
  462. /* Set PCI global control register to RC mode */
  463. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  464. reg |= (IS_RC_MSK << IS_RC_SHIFT);
  465. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  466. /* Set Advanced Error Capabilities and Control PF0 register */
  467. reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
  468. PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
  469. PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
  470. PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
  471. advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
  472. /* Set PCIe Device Control and Status 1 PF0 register */
  473. reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
  474. PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
  475. advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
  476. /* Program PCIe Control 2 to disable strict ordering */
  477. reg = PCIE_CORE_CTRL2_RESERVED |
  478. PCIE_CORE_CTRL2_TD_ENABLE;
  479. advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  480. /* Set GEN2 */
  481. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  482. reg &= ~PCIE_GEN_SEL_MSK;
  483. reg |= SPEED_GEN_2;
  484. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  485. /* Set lane X1 */
  486. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  487. reg &= ~LANE_CNT_MSK;
  488. reg |= LANE_COUNT_1;
  489. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  490. /* Enable link training */
  491. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  492. reg |= LINK_TRAINING_EN;
  493. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  494. /*
  495. * Enable AXI address window location generation:
  496. * When it is enabled, the default outbound window
  497. * configurations (Default User Field: 0xD0074CFC)
  498. * are used to transparent address translation for
  499. * the outbound transactions. Thus, PCIe address
  500. * windows are not required.
  501. */
  502. reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
  503. reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
  504. advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  505. /*
  506. * Bypass the address window mapping for PIO:
  507. * Since PIO access already contains all required
  508. * info over AXI interface by PIO registers, the
  509. * address window is not required.
  510. */
  511. reg = advk_readl(pcie, PIO_CTRL);
  512. reg |= PIO_CTRL_ADDR_WIN_DISABLE;
  513. advk_writel(pcie, reg, PIO_CTRL);
  514. /* Start link training */
  515. reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
  516. reg |= PCIE_CORE_LINK_TRAINING;
  517. advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
  518. /* Wait for PCIe link up */
  519. if (pcie_advk_wait_for_link(pcie))
  520. return -ENXIO;
  521. reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
  522. reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
  523. PCIE_CORE_CMD_IO_ACCESS_EN |
  524. PCIE_CORE_CMD_MEM_IO_REQ_EN;
  525. advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
  526. return 0;
  527. }
  528. /**
  529. * pcie_advk_probe() - Probe the PCIe bus for active link
  530. *
  531. * @dev: A pointer to the device being operated on
  532. *
  533. * Probe for an active link on the PCIe bus and configure the controller
  534. * to enable this port.
  535. *
  536. * Return: 0 on success, else -ENODEV
  537. */
  538. static int pcie_advk_probe(struct udevice *dev)
  539. {
  540. struct pcie_advk *pcie = dev_get_priv(dev);
  541. gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio,
  542. GPIOD_IS_OUT);
  543. /*
  544. * Issue reset to add-in card through the dedicated GPIO.
  545. * Some boards are connecting the card reset pin to common system
  546. * reset wire and others are using separate GPIO port.
  547. * In the last case we have to release a reset of the addon card
  548. * using this GPIO.
  549. *
  550. * FIX-ME:
  551. * The PCIe RESET signal is not supposed to be released along
  552. * with the SOC RESET signal. It should be lowered as early as
  553. * possible before PCIe PHY initialization. Moreover, the PCIe
  554. * clock should be gated as well.
  555. */
  556. if (dm_gpio_is_valid(&pcie->reset_gpio)) {
  557. dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
  558. dm_gpio_set_value(&pcie->reset_gpio, 1);
  559. mdelay(200);
  560. dm_gpio_set_value(&pcie->reset_gpio, 0);
  561. } else {
  562. dev_warn(pcie->dev, "PCIE Reset on GPIO support is missing\n");
  563. }
  564. pcie->first_busno = dev_seq(dev);
  565. pcie->dev = pci_get_controller(dev);
  566. return pcie_advk_setup_hw(pcie);
  567. }
  568. static int pcie_advk_remove(struct udevice *dev)
  569. {
  570. struct pcie_advk *pcie = dev_get_priv(dev);
  571. u32 reg;
  572. if (dm_gpio_is_valid(&pcie->reset_gpio))
  573. dm_gpio_set_value(&pcie->reset_gpio, 1);
  574. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  575. reg &= ~LINK_TRAINING_EN;
  576. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  577. return 0;
  578. }
  579. /**
  580. * pcie_advk_of_to_plat() - Translate from DT to device state
  581. *
  582. * @dev: A pointer to the device being operated on
  583. *
  584. * Translate relevant data from the device tree pertaining to device @dev into
  585. * state that the driver will later make use of. This state is stored in the
  586. * device's private data structure.
  587. *
  588. * Return: 0 on success, else -EINVAL
  589. */
  590. static int pcie_advk_of_to_plat(struct udevice *dev)
  591. {
  592. struct pcie_advk *pcie = dev_get_priv(dev);
  593. /* Get the register base address */
  594. pcie->base = (void *)dev_read_addr_index(dev, 0);
  595. if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
  596. return -EINVAL;
  597. return 0;
  598. }
  599. static const struct dm_pci_ops pcie_advk_ops = {
  600. .read_config = pcie_advk_read_config,
  601. .write_config = pcie_advk_write_config,
  602. };
  603. static const struct udevice_id pcie_advk_ids[] = {
  604. { .compatible = "marvell,armada-37xx-pcie" },
  605. { }
  606. };
  607. U_BOOT_DRIVER(pcie_advk) = {
  608. .name = "pcie_advk",
  609. .id = UCLASS_PCI,
  610. .of_match = pcie_advk_ids,
  611. .ops = &pcie_advk_ops,
  612. .of_to_plat = pcie_advk_of_to_plat,
  613. .probe = pcie_advk_probe,
  614. .remove = pcie_advk_remove,
  615. .flags = DM_FLAG_OS_PREPARE,
  616. .priv_auto = sizeof(struct pcie_advk),
  617. };