zynq_gem.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011 Michal Simek
  4. *
  5. * Michal SIMEK <monstr@monstr.eu>
  6. *
  7. * Based on Xilinx gmac driver:
  8. * (C) Copyright 2011 Xilinx
  9. */
  10. #include <clk.h>
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <dm.h>
  14. #include <log.h>
  15. #include <net.h>
  16. #include <netdev.h>
  17. #include <config.h>
  18. #include <console.h>
  19. #include <malloc.h>
  20. #include <asm/cache.h>
  21. #include <asm/io.h>
  22. #include <phy.h>
  23. #include <miiphy.h>
  24. #include <wait_bit.h>
  25. #include <watchdog.h>
  26. #include <asm/system.h>
  27. #include <asm/arch/hardware.h>
  28. #include <asm/arch/sys_proto.h>
  29. #include <dm/device_compat.h>
  30. #include <linux/bitops.h>
  31. #include <linux/err.h>
  32. #include <linux/errno.h>
  33. /* Bit/mask specification */
  34. #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
  35. #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
  36. #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
  37. #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
  38. #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
  39. #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
  40. #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
  41. #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
  42. #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
  43. #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
  44. #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
  45. /* Wrap bit, last descriptor */
  46. #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
  47. #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
  48. #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
  49. #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
  50. #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
  51. #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
  52. #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
  53. #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
  54. #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
  55. #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
  56. #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
  57. #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
  58. #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
  59. #ifdef CONFIG_ARM64
  60. #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
  61. #else
  62. #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
  63. #endif
  64. #ifdef CONFIG_ARM64
  65. # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
  66. #else
  67. # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
  68. #endif
  69. #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
  70. ZYNQ_GEM_NWCFG_FDEN | \
  71. ZYNQ_GEM_NWCFG_FSREM | \
  72. ZYNQ_GEM_NWCFG_MDCCLKDIV)
  73. #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
  74. #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
  75. /* Use full configured addressable space (8 Kb) */
  76. #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
  77. /* Use full configured addressable space (4 Kb) */
  78. #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
  79. /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
  80. #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
  81. #if defined(CONFIG_PHYS_64BIT)
  82. # define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
  83. #else
  84. # define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
  85. #endif
  86. #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
  87. ZYNQ_GEM_DMACR_RXSIZE | \
  88. ZYNQ_GEM_DMACR_TXSIZE | \
  89. ZYNQ_GEM_DMACR_RXBUF | \
  90. ZYNQ_GEM_DMA_BUS_WIDTH)
  91. #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
  92. #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
  93. #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
  94. /* Use MII register 1 (MII status register) to detect PHY */
  95. #define PHY_DETECT_REG 1
  96. /* Mask used to verify certain PHY features (or register contents)
  97. * in the register above:
  98. * 0x1000: 10Mbps full duplex support
  99. * 0x0800: 10Mbps half duplex support
  100. * 0x0008: Auto-negotiation support
  101. */
  102. #define PHY_DETECT_MASK 0x1808
  103. /* TX BD status masks */
  104. #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
  105. #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
  106. #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
  107. /* Clock frequencies for different speeds */
  108. #define ZYNQ_GEM_FREQUENCY_10 2500000UL
  109. #define ZYNQ_GEM_FREQUENCY_100 25000000UL
  110. #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
  111. /* Device registers */
  112. struct zynq_gem_regs {
  113. u32 nwctrl; /* 0x0 - Network Control reg */
  114. u32 nwcfg; /* 0x4 - Network Config reg */
  115. u32 nwsr; /* 0x8 - Network Status reg */
  116. u32 reserved1;
  117. u32 dmacr; /* 0x10 - DMA Control reg */
  118. u32 txsr; /* 0x14 - TX Status reg */
  119. u32 rxqbase; /* 0x18 - RX Q Base address reg */
  120. u32 txqbase; /* 0x1c - TX Q Base address reg */
  121. u32 rxsr; /* 0x20 - RX Status reg */
  122. u32 reserved2[2];
  123. u32 idr; /* 0x2c - Interrupt Disable reg */
  124. u32 reserved3;
  125. u32 phymntnc; /* 0x34 - Phy Maintaince reg */
  126. u32 reserved4[18];
  127. u32 hashl; /* 0x80 - Hash Low address reg */
  128. u32 hashh; /* 0x84 - Hash High address reg */
  129. #define LADDR_LOW 0
  130. #define LADDR_HIGH 1
  131. u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
  132. u32 match[4]; /* 0xa8 - Type ID1 Match reg */
  133. u32 reserved6[18];
  134. #define STAT_SIZE 44
  135. u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
  136. u32 reserved9[20];
  137. u32 pcscntrl;
  138. u32 rserved12[36];
  139. u32 dcfg6; /* 0x294 Design config reg6 */
  140. u32 reserved7[106];
  141. u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
  142. u32 reserved8[15];
  143. u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
  144. u32 reserved10[17];
  145. u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
  146. u32 reserved11[2];
  147. u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
  148. };
  149. /* BD descriptors */
  150. struct emac_bd {
  151. u32 addr; /* Next descriptor pointer */
  152. u32 status;
  153. #if defined(CONFIG_PHYS_64BIT)
  154. u32 addr_hi;
  155. u32 reserved;
  156. #endif
  157. };
  158. /* Reduce amount of BUFs if you have limited amount of memory */
  159. #define RX_BUF 32
  160. /* Page table entries are set to 1MB, or multiples of 1MB
  161. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  162. */
  163. #define BD_SPACE 0x100000
  164. /* BD separation space */
  165. #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
  166. /* Setup the first free TX descriptor */
  167. #define TX_FREE_DESC 2
  168. /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
  169. struct zynq_gem_priv {
  170. struct emac_bd *tx_bd;
  171. struct emac_bd *rx_bd;
  172. char *rxbuffers;
  173. u32 rxbd_current;
  174. u32 rx_first_buf;
  175. int phyaddr;
  176. int init;
  177. struct zynq_gem_regs *iobase;
  178. struct zynq_gem_regs *mdiobase;
  179. phy_interface_t interface;
  180. struct phy_device *phydev;
  181. ofnode phy_of_node;
  182. struct mii_dev *bus;
  183. struct clk clk;
  184. u32 max_speed;
  185. bool int_pcs;
  186. bool dma_64bit;
  187. };
  188. static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
  189. u32 op, u16 *data)
  190. {
  191. u32 mgtcr;
  192. struct zynq_gem_regs *regs = priv->mdiobase;
  193. int err;
  194. err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
  195. true, 20000, false);
  196. if (err)
  197. return err;
  198. /* Construct mgtcr mask for the operation */
  199. mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
  200. (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
  201. (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
  202. /* Write mgtcr and wait for completion */
  203. writel(mgtcr, &regs->phymntnc);
  204. err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
  205. true, 20000, false);
  206. if (err)
  207. return err;
  208. if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
  209. *data = readl(&regs->phymntnc);
  210. return 0;
  211. }
  212. static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
  213. u32 regnum, u16 *val)
  214. {
  215. int ret;
  216. ret = phy_setup_op(priv, phy_addr, regnum,
  217. ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
  218. if (!ret)
  219. debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
  220. phy_addr, regnum, *val);
  221. return ret;
  222. }
  223. static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
  224. u32 regnum, u16 data)
  225. {
  226. debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
  227. regnum, data);
  228. return phy_setup_op(priv, phy_addr, regnum,
  229. ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
  230. }
  231. static int zynq_gem_setup_mac(struct udevice *dev)
  232. {
  233. u32 i, macaddrlow, macaddrhigh;
  234. struct eth_pdata *pdata = dev_get_plat(dev);
  235. struct zynq_gem_priv *priv = dev_get_priv(dev);
  236. struct zynq_gem_regs *regs = priv->iobase;
  237. /* Set the MAC bits [31:0] in BOT */
  238. macaddrlow = pdata->enetaddr[0];
  239. macaddrlow |= pdata->enetaddr[1] << 8;
  240. macaddrlow |= pdata->enetaddr[2] << 16;
  241. macaddrlow |= pdata->enetaddr[3] << 24;
  242. /* Set MAC bits [47:32] in TOP */
  243. macaddrhigh = pdata->enetaddr[4];
  244. macaddrhigh |= pdata->enetaddr[5] << 8;
  245. for (i = 0; i < 4; i++) {
  246. writel(0, &regs->laddr[i][LADDR_LOW]);
  247. writel(0, &regs->laddr[i][LADDR_HIGH]);
  248. /* Do not use MATCHx register */
  249. writel(0, &regs->match[i]);
  250. }
  251. writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
  252. writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
  253. return 0;
  254. }
  255. static int zynq_phy_init(struct udevice *dev)
  256. {
  257. int ret;
  258. struct zynq_gem_priv *priv = dev_get_priv(dev);
  259. struct zynq_gem_regs *regs_mdio = priv->mdiobase;
  260. const u32 supported = SUPPORTED_10baseT_Half |
  261. SUPPORTED_10baseT_Full |
  262. SUPPORTED_100baseT_Half |
  263. SUPPORTED_100baseT_Full |
  264. SUPPORTED_1000baseT_Half |
  265. SUPPORTED_1000baseT_Full;
  266. /* Enable only MDIO bus */
  267. writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs_mdio->nwctrl);
  268. priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
  269. priv->interface);
  270. if (!priv->phydev)
  271. return -ENODEV;
  272. if (priv->max_speed) {
  273. ret = phy_set_supported(priv->phydev, priv->max_speed);
  274. if (ret)
  275. return ret;
  276. }
  277. priv->phydev->supported &= supported | ADVERTISED_Pause |
  278. ADVERTISED_Asym_Pause;
  279. priv->phydev->advertising = priv->phydev->supported;
  280. priv->phydev->node = priv->phy_of_node;
  281. return phy_config(priv->phydev);
  282. }
  283. static int zynq_gem_init(struct udevice *dev)
  284. {
  285. u32 i, nwconfig;
  286. int ret;
  287. unsigned long clk_rate = 0;
  288. struct zynq_gem_priv *priv = dev_get_priv(dev);
  289. struct zynq_gem_regs *regs = priv->iobase;
  290. struct zynq_gem_regs *regs_mdio = priv->mdiobase;
  291. struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
  292. struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
  293. if (readl(&regs->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
  294. priv->dma_64bit = true;
  295. else
  296. priv->dma_64bit = false;
  297. #if defined(CONFIG_PHYS_64BIT)
  298. if (!priv->dma_64bit) {
  299. printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
  300. __func__);
  301. return -EINVAL;
  302. }
  303. #else
  304. if (priv->dma_64bit)
  305. debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
  306. __func__);
  307. #endif
  308. if (!priv->init) {
  309. /* Disable all interrupts */
  310. writel(0xFFFFFFFF, &regs->idr);
  311. /* Disable the receiver & transmitter */
  312. writel(0, &regs->nwctrl);
  313. writel(0, &regs->txsr);
  314. writel(0, &regs->rxsr);
  315. writel(0, &regs->phymntnc);
  316. /* Clear the Hash registers for the mac address
  317. * pointed by AddressPtr
  318. */
  319. writel(0x0, &regs->hashl);
  320. /* Write bits [63:32] in TOP */
  321. writel(0x0, &regs->hashh);
  322. /* Clear all counters */
  323. for (i = 0; i < STAT_SIZE; i++)
  324. readl(&regs->stat[i]);
  325. /* Setup RxBD space */
  326. memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
  327. for (i = 0; i < RX_BUF; i++) {
  328. priv->rx_bd[i].status = 0xF0000000;
  329. priv->rx_bd[i].addr =
  330. (lower_32_bits((ulong)(priv->rxbuffers)
  331. + (i * PKTSIZE_ALIGN)));
  332. #if defined(CONFIG_PHYS_64BIT)
  333. priv->rx_bd[i].addr_hi =
  334. (upper_32_bits((ulong)(priv->rxbuffers)
  335. + (i * PKTSIZE_ALIGN)));
  336. #endif
  337. }
  338. /* WRAP bit to last BD */
  339. priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
  340. /* Write RxBDs to IP */
  341. writel(lower_32_bits((ulong)priv->rx_bd), &regs->rxqbase);
  342. #if defined(CONFIG_PHYS_64BIT)
  343. writel(upper_32_bits((ulong)priv->rx_bd), &regs->upper_rxqbase);
  344. #endif
  345. /* Setup for DMA Configuration register */
  346. writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
  347. /* Setup for Network Control register, MDIO, Rx and Tx enable */
  348. setbits_le32(&regs_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
  349. /* Disable the second priority queue */
  350. dummy_tx_bd->addr = 0;
  351. #if defined(CONFIG_PHYS_64BIT)
  352. dummy_tx_bd->addr_hi = 0;
  353. #endif
  354. dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
  355. ZYNQ_GEM_TXBUF_LAST_MASK|
  356. ZYNQ_GEM_TXBUF_USED_MASK;
  357. dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
  358. ZYNQ_GEM_RXBUF_NEW_MASK;
  359. #if defined(CONFIG_PHYS_64BIT)
  360. dummy_rx_bd->addr_hi = 0;
  361. #endif
  362. dummy_rx_bd->status = 0;
  363. writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
  364. writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
  365. priv->init++;
  366. }
  367. ret = phy_startup(priv->phydev);
  368. if (ret)
  369. return ret;
  370. if (!priv->phydev->link) {
  371. printf("%s: No link.\n", priv->phydev->dev->name);
  372. return -1;
  373. }
  374. nwconfig = ZYNQ_GEM_NWCFG_INIT;
  375. /*
  376. * Set SGMII enable PCS selection only if internal PCS/PMA
  377. * core is used and interface is SGMII.
  378. */
  379. if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
  380. priv->int_pcs) {
  381. nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
  382. ZYNQ_GEM_NWCFG_PCS_SEL;
  383. #ifdef CONFIG_ARM64
  384. if (priv->phydev->phy_id != PHY_FIXED_ID)
  385. writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
  386. &regs->pcscntrl);
  387. else
  388. writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
  389. &regs->pcscntrl);
  390. #endif
  391. }
  392. switch (priv->phydev->speed) {
  393. case SPEED_1000:
  394. writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
  395. &regs->nwcfg);
  396. clk_rate = ZYNQ_GEM_FREQUENCY_1000;
  397. break;
  398. case SPEED_100:
  399. writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
  400. &regs->nwcfg);
  401. clk_rate = ZYNQ_GEM_FREQUENCY_100;
  402. break;
  403. case SPEED_10:
  404. clk_rate = ZYNQ_GEM_FREQUENCY_10;
  405. break;
  406. }
  407. ret = clk_set_rate(&priv->clk, clk_rate);
  408. if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
  409. dev_err(dev, "failed to set tx clock rate\n");
  410. return ret;
  411. }
  412. ret = clk_enable(&priv->clk);
  413. if (ret && ret != -ENOSYS) {
  414. dev_err(dev, "failed to enable tx clock\n");
  415. return ret;
  416. }
  417. setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
  418. ZYNQ_GEM_NWCTRL_TXEN_MASK);
  419. return 0;
  420. }
  421. static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
  422. {
  423. dma_addr_t addr;
  424. u32 size;
  425. struct zynq_gem_priv *priv = dev_get_priv(dev);
  426. struct zynq_gem_regs *regs = priv->iobase;
  427. struct emac_bd *current_bd = &priv->tx_bd[1];
  428. /* Setup Tx BD */
  429. memset(priv->tx_bd, 0, sizeof(struct emac_bd));
  430. priv->tx_bd->addr = lower_32_bits((ulong)ptr);
  431. #if defined(CONFIG_PHYS_64BIT)
  432. priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
  433. #endif
  434. priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
  435. ZYNQ_GEM_TXBUF_LAST_MASK;
  436. /* Dummy descriptor to mark it as the last in descriptor chain */
  437. current_bd->addr = 0x0;
  438. #if defined(CONFIG_PHYS_64BIT)
  439. current_bd->addr_hi = 0x0;
  440. #endif
  441. current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
  442. ZYNQ_GEM_TXBUF_LAST_MASK|
  443. ZYNQ_GEM_TXBUF_USED_MASK;
  444. /* setup BD */
  445. writel(lower_32_bits((ulong)priv->tx_bd), &regs->txqbase);
  446. #if defined(CONFIG_PHYS_64BIT)
  447. writel(upper_32_bits((ulong)priv->tx_bd), &regs->upper_txqbase);
  448. #endif
  449. addr = (ulong) ptr;
  450. addr &= ~(ARCH_DMA_MINALIGN - 1);
  451. size = roundup(len, ARCH_DMA_MINALIGN);
  452. flush_dcache_range(addr, addr + size);
  453. barrier();
  454. /* Start transmit */
  455. setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
  456. /* Read TX BD status */
  457. if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
  458. printf("TX buffers exhausted in mid frame\n");
  459. return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
  460. true, 20000, true);
  461. }
  462. /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
  463. static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
  464. {
  465. int frame_len;
  466. dma_addr_t addr;
  467. struct zynq_gem_priv *priv = dev_get_priv(dev);
  468. struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
  469. if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
  470. return -1;
  471. if (!(current_bd->status &
  472. (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
  473. printf("GEM: SOF or EOF not set for last buffer received!\n");
  474. return -1;
  475. }
  476. frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
  477. if (!frame_len) {
  478. printf("%s: Zero size packet?\n", __func__);
  479. return -1;
  480. }
  481. #if defined(CONFIG_PHYS_64BIT)
  482. addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
  483. | ((dma_addr_t)current_bd->addr_hi << 32));
  484. #else
  485. addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
  486. #endif
  487. addr &= ~(ARCH_DMA_MINALIGN - 1);
  488. *packetp = (uchar *)(uintptr_t)addr;
  489. invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
  490. barrier();
  491. return frame_len;
  492. }
  493. static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
  494. {
  495. struct zynq_gem_priv *priv = dev_get_priv(dev);
  496. struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
  497. struct emac_bd *first_bd;
  498. dma_addr_t addr;
  499. if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
  500. priv->rx_first_buf = priv->rxbd_current;
  501. } else {
  502. current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
  503. current_bd->status = 0xF0000000; /* FIXME */
  504. }
  505. if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
  506. first_bd = &priv->rx_bd[priv->rx_first_buf];
  507. first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
  508. first_bd->status = 0xF0000000;
  509. }
  510. /* Flush the cache for the packet as well */
  511. #if defined(CONFIG_PHYS_64BIT)
  512. addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
  513. | ((dma_addr_t)current_bd->addr_hi << 32));
  514. #else
  515. addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
  516. #endif
  517. flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN,
  518. ARCH_DMA_MINALIGN));
  519. barrier();
  520. if ((++priv->rxbd_current) >= RX_BUF)
  521. priv->rxbd_current = 0;
  522. return 0;
  523. }
  524. static void zynq_gem_halt(struct udevice *dev)
  525. {
  526. struct zynq_gem_priv *priv = dev_get_priv(dev);
  527. struct zynq_gem_regs *regs = priv->iobase;
  528. clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
  529. ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
  530. }
  531. __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
  532. {
  533. return -ENOSYS;
  534. }
  535. static int zynq_gem_read_rom_mac(struct udevice *dev)
  536. {
  537. struct eth_pdata *pdata = dev_get_plat(dev);
  538. if (!pdata)
  539. return -ENOSYS;
  540. return zynq_board_read_rom_ethaddr(pdata->enetaddr);
  541. }
  542. static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
  543. int devad, int reg)
  544. {
  545. struct zynq_gem_priv *priv = bus->priv;
  546. int ret;
  547. u16 val = 0;
  548. ret = phyread(priv, addr, reg, &val);
  549. debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
  550. return val;
  551. }
  552. static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
  553. int reg, u16 value)
  554. {
  555. struct zynq_gem_priv *priv = bus->priv;
  556. debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
  557. return phywrite(priv, addr, reg, value);
  558. }
  559. static int zynq_gem_probe(struct udevice *dev)
  560. {
  561. void *bd_space;
  562. struct zynq_gem_priv *priv = dev_get_priv(dev);
  563. int ret;
  564. /* Align rxbuffers to ARCH_DMA_MINALIGN */
  565. priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
  566. if (!priv->rxbuffers)
  567. return -ENOMEM;
  568. memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
  569. ulong addr = (ulong)priv->rxbuffers;
  570. flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
  571. barrier();
  572. /* Align bd_space to MMU_SECTION_SHIFT */
  573. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  574. if (!bd_space) {
  575. ret = -ENOMEM;
  576. goto err1;
  577. }
  578. mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
  579. BD_SPACE, DCACHE_OFF);
  580. /* Initialize the bd spaces for tx and rx bd's */
  581. priv->tx_bd = (struct emac_bd *)bd_space;
  582. priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
  583. ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
  584. if (ret < 0) {
  585. dev_err(dev, "failed to get clock\n");
  586. goto err1;
  587. }
  588. priv->bus = mdio_alloc();
  589. priv->bus->read = zynq_gem_miiphy_read;
  590. priv->bus->write = zynq_gem_miiphy_write;
  591. priv->bus->priv = priv;
  592. ret = mdio_register_seq(priv->bus, dev_seq(dev));
  593. if (ret)
  594. goto err2;
  595. ret = zynq_phy_init(dev);
  596. if (ret)
  597. goto err2;
  598. return ret;
  599. err2:
  600. free(priv->rxbuffers);
  601. err1:
  602. free(priv->tx_bd);
  603. return ret;
  604. }
  605. static int zynq_gem_remove(struct udevice *dev)
  606. {
  607. struct zynq_gem_priv *priv = dev_get_priv(dev);
  608. free(priv->phydev);
  609. mdio_unregister(priv->bus);
  610. mdio_free(priv->bus);
  611. return 0;
  612. }
  613. static const struct eth_ops zynq_gem_ops = {
  614. .start = zynq_gem_init,
  615. .send = zynq_gem_send,
  616. .recv = zynq_gem_recv,
  617. .free_pkt = zynq_gem_free_pkt,
  618. .stop = zynq_gem_halt,
  619. .write_hwaddr = zynq_gem_setup_mac,
  620. .read_rom_hwaddr = zynq_gem_read_rom_mac,
  621. };
  622. static int zynq_gem_of_to_plat(struct udevice *dev)
  623. {
  624. struct eth_pdata *pdata = dev_get_plat(dev);
  625. struct zynq_gem_priv *priv = dev_get_priv(dev);
  626. struct ofnode_phandle_args phandle_args;
  627. const char *phy_mode;
  628. pdata->iobase = (phys_addr_t)dev_read_addr(dev);
  629. priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
  630. priv->mdiobase = priv->iobase;
  631. /* Hardcode for now */
  632. priv->phyaddr = -1;
  633. if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  634. &phandle_args)) {
  635. fdt_addr_t addr;
  636. ofnode parent;
  637. debug("phy-handle does exist %s\n", dev->name);
  638. priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
  639. "reg", -1);
  640. priv->phy_of_node = phandle_args.node;
  641. priv->max_speed = ofnode_read_u32_default(phandle_args.node,
  642. "max-speed",
  643. SPEED_1000);
  644. parent = ofnode_get_parent(phandle_args.node);
  645. addr = ofnode_get_addr(parent);
  646. if (addr != FDT_ADDR_T_NONE) {
  647. debug("MDIO bus not found %s\n", dev->name);
  648. priv->mdiobase = (struct zynq_gem_regs *)addr;
  649. }
  650. }
  651. phy_mode = dev_read_prop(dev, "phy-mode", NULL);
  652. if (phy_mode)
  653. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  654. if (pdata->phy_interface == -1) {
  655. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  656. return -EINVAL;
  657. }
  658. priv->interface = pdata->phy_interface;
  659. priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
  660. printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n",
  661. (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr,
  662. phy_string_for_interface(priv->interface));
  663. return 0;
  664. }
  665. static const struct udevice_id zynq_gem_ids[] = {
  666. { .compatible = "cdns,versal-gem" },
  667. { .compatible = "cdns,zynqmp-gem" },
  668. { .compatible = "cdns,zynq-gem" },
  669. { .compatible = "cdns,gem" },
  670. { }
  671. };
  672. U_BOOT_DRIVER(zynq_gem) = {
  673. .name = "zynq_gem",
  674. .id = UCLASS_ETH,
  675. .of_match = zynq_gem_ids,
  676. .of_to_plat = zynq_gem_of_to_plat,
  677. .probe = zynq_gem_probe,
  678. .remove = zynq_gem_remove,
  679. .ops = &zynq_gem_ops,
  680. .priv_auto = sizeof(struct zynq_gem_priv),
  681. .plat_auto = sizeof(struct eth_pdata),
  682. };