xilinx_emaclite.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2009 Michal Simek
  4. * (C) Copyright 2003 Xilinx Inc.
  5. *
  6. * Michal SIMEK <monstr@monstr.eu>
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <net.h>
  11. #include <config.h>
  12. #include <dm.h>
  13. #include <console.h>
  14. #include <malloc.h>
  15. #include <asm/io.h>
  16. #include <phy.h>
  17. #include <miiphy.h>
  18. #include <fdtdec.h>
  19. #include <linux/delay.h>
  20. #include <linux/errno.h>
  21. #include <linux/kernel.h>
  22. #include <asm/io.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define ENET_ADDR_LENGTH 6
  25. #define ETH_FCS_LEN 4 /* Octets in the FCS */
  26. /* Xmit complete */
  27. #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
  28. /* Xmit interrupt enable bit */
  29. #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
  30. /* Program the MAC address */
  31. #define XEL_TSR_PROGRAM_MASK 0x00000002UL
  32. /* define for programming the MAC address into the EMAC Lite */
  33. #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
  34. /* Transmit packet length upper byte */
  35. #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
  36. /* Transmit packet length lower byte */
  37. #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
  38. /* Recv complete */
  39. #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
  40. /* Recv interrupt enable bit */
  41. #define XEL_RSR_RECV_IE_MASK 0x00000008UL
  42. /* MDIO Address Register Bit Masks */
  43. #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
  44. #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
  45. #define XEL_MDIOADDR_PHYADR_SHIFT 5
  46. #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
  47. /* MDIO Write Data Register Bit Masks */
  48. #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
  49. /* MDIO Read Data Register Bit Masks */
  50. #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
  51. /* MDIO Control Register Bit Masks */
  52. #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
  53. #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
  54. struct emaclite_regs {
  55. u32 tx_ping; /* 0x0 - TX Ping buffer */
  56. u32 reserved1[504];
  57. u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
  58. u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
  59. u32 mdiord;/* 0x7ec - MDIO Read Data Register */
  60. u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
  61. u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
  62. u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
  63. u32 tx_ping_tsr; /* 0x7fc - Tx status */
  64. u32 tx_pong; /* 0x800 - TX Pong buffer */
  65. u32 reserved2[508];
  66. u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
  67. u32 reserved3; /* 0xff8 */
  68. u32 tx_pong_tsr; /* 0xffc - Tx status */
  69. u32 rx_ping; /* 0x1000 - Receive Buffer */
  70. u32 reserved4[510];
  71. u32 rx_ping_rsr; /* 0x17fc - Rx status */
  72. u32 rx_pong; /* 0x1800 - Receive Buffer */
  73. u32 reserved5[510];
  74. u32 rx_pong_rsr; /* 0x1ffc - Rx status */
  75. };
  76. struct xemaclite {
  77. bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
  78. u32 txpp; /* TX ping pong buffer */
  79. u32 rxpp; /* RX ping pong buffer */
  80. int phyaddr;
  81. struct emaclite_regs *regs;
  82. struct phy_device *phydev;
  83. struct mii_dev *bus;
  84. };
  85. static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
  86. static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
  87. {
  88. u32 i;
  89. u32 alignbuffer;
  90. u32 *to32ptr;
  91. u32 *from32ptr;
  92. u8 *to8ptr;
  93. u8 *from8ptr;
  94. from32ptr = (u32 *) srcptr;
  95. /* Word aligned buffer, no correction needed. */
  96. to32ptr = (u32 *) destptr;
  97. while (bytecount > 3) {
  98. *to32ptr++ = *from32ptr++;
  99. bytecount -= 4;
  100. }
  101. to8ptr = (u8 *) to32ptr;
  102. alignbuffer = *from32ptr++;
  103. from8ptr = (u8 *) &alignbuffer;
  104. for (i = 0; i < bytecount; i++)
  105. *to8ptr++ = *from8ptr++;
  106. }
  107. static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
  108. {
  109. u32 i;
  110. u32 alignbuffer;
  111. u32 *to32ptr = (u32 *) destptr;
  112. u32 *from32ptr;
  113. u8 *to8ptr;
  114. u8 *from8ptr;
  115. from32ptr = (u32 *) srcptr;
  116. while (bytecount > 3) {
  117. *to32ptr++ = *from32ptr++;
  118. bytecount -= 4;
  119. }
  120. alignbuffer = 0;
  121. to8ptr = (u8 *) &alignbuffer;
  122. from8ptr = (u8 *) from32ptr;
  123. for (i = 0; i < bytecount; i++)
  124. *to8ptr++ = *from8ptr++;
  125. *to32ptr++ = alignbuffer;
  126. }
  127. static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
  128. bool set, unsigned int timeout)
  129. {
  130. u32 val;
  131. unsigned long start = get_timer(0);
  132. while (1) {
  133. val = __raw_readl(reg);
  134. if (!set)
  135. val = ~val;
  136. if ((val & mask) == mask)
  137. return 0;
  138. if (get_timer(start) > timeout)
  139. break;
  140. if (ctrlc()) {
  141. puts("Abort\n");
  142. return -EINTR;
  143. }
  144. udelay(1);
  145. }
  146. debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  147. func, reg, mask, set);
  148. return -ETIMEDOUT;
  149. }
  150. static int mdio_wait(struct emaclite_regs *regs)
  151. {
  152. return wait_for_bit(__func__, &regs->mdioctrl,
  153. XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
  154. }
  155. static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
  156. u16 *data)
  157. {
  158. struct emaclite_regs *regs = emaclite->regs;
  159. if (mdio_wait(regs))
  160. return 1;
  161. u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
  162. __raw_writel(XEL_MDIOADDR_OP_MASK
  163. | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
  164. | registernum), &regs->mdioaddr);
  165. __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
  166. if (mdio_wait(regs))
  167. return 1;
  168. /* Read data */
  169. *data = __raw_readl(&regs->mdiord);
  170. return 0;
  171. }
  172. static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
  173. u16 data)
  174. {
  175. struct emaclite_regs *regs = emaclite->regs;
  176. if (mdio_wait(regs))
  177. return 1;
  178. /*
  179. * Write the PHY address, register number and clear the OP bit in the
  180. * MDIO Address register and then write the value into the MDIO Write
  181. * Data register. Finally, set the Status bit in the MDIO Control
  182. * register to start a MDIO write transaction.
  183. */
  184. u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
  185. __raw_writel(~XEL_MDIOADDR_OP_MASK
  186. & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
  187. | registernum), &regs->mdioaddr);
  188. __raw_writel(data, &regs->mdiowr);
  189. __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
  190. if (mdio_wait(regs))
  191. return 1;
  192. return 0;
  193. }
  194. static void emaclite_stop(struct udevice *dev)
  195. {
  196. debug("eth_stop\n");
  197. }
  198. /* Use MII register 1 (MII status register) to detect PHY */
  199. #define PHY_DETECT_REG 1
  200. /* Mask used to verify certain PHY features (or register contents)
  201. * in the register above:
  202. * 0x1000: 10Mbps full duplex support
  203. * 0x0800: 10Mbps half duplex support
  204. * 0x0008: Auto-negotiation support
  205. */
  206. #define PHY_DETECT_MASK 0x1808
  207. static int setup_phy(struct udevice *dev)
  208. {
  209. int i, ret;
  210. u16 phyreg;
  211. struct xemaclite *emaclite = dev_get_priv(dev);
  212. struct phy_device *phydev;
  213. u32 supported = SUPPORTED_10baseT_Half |
  214. SUPPORTED_10baseT_Full |
  215. SUPPORTED_100baseT_Half |
  216. SUPPORTED_100baseT_Full;
  217. if (emaclite->phyaddr != -1) {
  218. phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
  219. if ((phyreg != 0xFFFF) &&
  220. ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
  221. /* Found a valid PHY address */
  222. debug("Default phy address %d is valid\n",
  223. emaclite->phyaddr);
  224. } else {
  225. debug("PHY address is not setup correctly %d\n",
  226. emaclite->phyaddr);
  227. emaclite->phyaddr = -1;
  228. }
  229. }
  230. if (emaclite->phyaddr == -1) {
  231. /* detect the PHY address */
  232. for (i = 31; i >= 0; i--) {
  233. phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
  234. if ((phyreg != 0xFFFF) &&
  235. ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
  236. /* Found a valid PHY address */
  237. emaclite->phyaddr = i;
  238. debug("emaclite: Found valid phy address, %d\n",
  239. i);
  240. break;
  241. }
  242. }
  243. }
  244. /* interface - look at tsec */
  245. phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
  246. PHY_INTERFACE_MODE_MII);
  247. /*
  248. * Phy can support 1000baseT but device NOT that's why phydev->supported
  249. * must be setup for 1000baseT. phydev->advertising setups what speeds
  250. * will be used for autonegotiation where 1000baseT must be disabled.
  251. */
  252. phydev->supported = supported | SUPPORTED_1000baseT_Half |
  253. SUPPORTED_1000baseT_Full;
  254. phydev->advertising = supported;
  255. emaclite->phydev = phydev;
  256. phy_config(phydev);
  257. ret = phy_startup(phydev);
  258. if (ret)
  259. return ret;
  260. if (!phydev->link) {
  261. printf("%s: No link.\n", phydev->dev->name);
  262. return 0;
  263. }
  264. /* Do not setup anything */
  265. return 1;
  266. }
  267. static int emaclite_start(struct udevice *dev)
  268. {
  269. struct xemaclite *emaclite = dev_get_priv(dev);
  270. struct eth_pdata *pdata = dev_get_plat(dev);
  271. struct emaclite_regs *regs = emaclite->regs;
  272. debug("EmacLite Initialization Started\n");
  273. /*
  274. * TX - TX_PING & TX_PONG initialization
  275. */
  276. /* Restart PING TX */
  277. __raw_writel(0, &regs->tx_ping_tsr);
  278. /* Copy MAC address */
  279. xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
  280. ENET_ADDR_LENGTH);
  281. /* Set the length */
  282. __raw_writel(ENET_ADDR_LENGTH, &regs->tx_ping_tplr);
  283. /* Update the MAC address in the EMAC Lite */
  284. __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_ping_tsr);
  285. /* Wait for EMAC Lite to finish with the MAC address update */
  286. while ((__raw_readl(&regs->tx_ping_tsr) &
  287. XEL_TSR_PROG_MAC_ADDR) != 0)
  288. ;
  289. if (emaclite->txpp) {
  290. /* The same operation with PONG TX */
  291. __raw_writel(0, &regs->tx_pong_tsr);
  292. xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
  293. ENET_ADDR_LENGTH);
  294. __raw_writel(ENET_ADDR_LENGTH, &regs->tx_pong_tplr);
  295. __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_pong_tsr);
  296. while ((__raw_readl(&regs->tx_pong_tsr) &
  297. XEL_TSR_PROG_MAC_ADDR) != 0)
  298. ;
  299. }
  300. /*
  301. * RX - RX_PING & RX_PONG initialization
  302. */
  303. /* Write out the value to flush the RX buffer */
  304. __raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_ping_rsr);
  305. if (emaclite->rxpp)
  306. __raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_pong_rsr);
  307. __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, &regs->mdioctrl);
  308. if (__raw_readl(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
  309. if (!setup_phy(dev))
  310. return -1;
  311. debug("EmacLite Initialization complete\n");
  312. return 0;
  313. }
  314. static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
  315. {
  316. u32 tmp;
  317. struct emaclite_regs *regs = emaclite->regs;
  318. /*
  319. * Read the other buffer register
  320. * and determine if the other buffer is available
  321. */
  322. tmp = ~__raw_readl(&regs->tx_ping_tsr);
  323. if (emaclite->txpp)
  324. tmp |= ~__raw_readl(&regs->tx_pong_tsr);
  325. return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
  326. }
  327. static int emaclite_send(struct udevice *dev, void *ptr, int len)
  328. {
  329. u32 reg;
  330. struct xemaclite *emaclite = dev_get_priv(dev);
  331. struct emaclite_regs *regs = emaclite->regs;
  332. u32 maxtry = 1000;
  333. if (len > PKTSIZE)
  334. len = PKTSIZE;
  335. while (xemaclite_txbufferavailable(emaclite) && maxtry) {
  336. udelay(10);
  337. maxtry--;
  338. }
  339. if (!maxtry) {
  340. printf("Error: Timeout waiting for ethernet TX buffer\n");
  341. /* Restart PING TX */
  342. __raw_writel(0, &regs->tx_ping_tsr);
  343. if (emaclite->txpp) {
  344. __raw_writel(0, &regs->tx_pong_tsr);
  345. }
  346. return -1;
  347. }
  348. /* Determine if the expected buffer address is empty */
  349. reg = __raw_readl(&regs->tx_ping_tsr);
  350. if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
  351. debug("Send packet from tx_ping buffer\n");
  352. /* Write the frame to the buffer */
  353. xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
  354. __raw_writel(len
  355. & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
  356. &regs->tx_ping_tplr);
  357. reg = __raw_readl(&regs->tx_ping_tsr);
  358. reg |= XEL_TSR_XMIT_BUSY_MASK;
  359. __raw_writel(reg, &regs->tx_ping_tsr);
  360. return 0;
  361. }
  362. if (emaclite->txpp) {
  363. /* Determine if the expected buffer address is empty */
  364. reg = __raw_readl(&regs->tx_pong_tsr);
  365. if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
  366. debug("Send packet from tx_pong buffer\n");
  367. /* Write the frame to the buffer */
  368. xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
  369. __raw_writel(len &
  370. (XEL_TPLR_LENGTH_MASK_HI |
  371. XEL_TPLR_LENGTH_MASK_LO),
  372. &regs->tx_pong_tplr);
  373. reg = __raw_readl(&regs->tx_pong_tsr);
  374. reg |= XEL_TSR_XMIT_BUSY_MASK;
  375. __raw_writel(reg, &regs->tx_pong_tsr);
  376. return 0;
  377. }
  378. }
  379. puts("Error while sending frame\n");
  380. return -1;
  381. }
  382. static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
  383. {
  384. u32 length, first_read, reg, attempt = 0;
  385. void *addr, *ack;
  386. struct xemaclite *emaclite = dev->priv;
  387. struct emaclite_regs *regs = emaclite->regs;
  388. struct ethernet_hdr *eth;
  389. struct ip_udp_hdr *ip;
  390. try_again:
  391. if (!emaclite->use_rx_pong_buffer_next) {
  392. reg = __raw_readl(&regs->rx_ping_rsr);
  393. debug("Testing data at rx_ping\n");
  394. if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
  395. debug("Data found in rx_ping buffer\n");
  396. addr = &regs->rx_ping;
  397. ack = &regs->rx_ping_rsr;
  398. } else {
  399. debug("Data not found in rx_ping buffer\n");
  400. /* Pong buffer is not available - return immediately */
  401. if (!emaclite->rxpp)
  402. return -1;
  403. /* Try pong buffer if this is first attempt */
  404. if (attempt++)
  405. return -1;
  406. emaclite->use_rx_pong_buffer_next =
  407. !emaclite->use_rx_pong_buffer_next;
  408. goto try_again;
  409. }
  410. } else {
  411. reg = __raw_readl(&regs->rx_pong_rsr);
  412. debug("Testing data at rx_pong\n");
  413. if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
  414. debug("Data found in rx_pong buffer\n");
  415. addr = &regs->rx_pong;
  416. ack = &regs->rx_pong_rsr;
  417. } else {
  418. debug("Data not found in rx_pong buffer\n");
  419. /* Try ping buffer if this is first attempt */
  420. if (attempt++)
  421. return -1;
  422. emaclite->use_rx_pong_buffer_next =
  423. !emaclite->use_rx_pong_buffer_next;
  424. goto try_again;
  425. }
  426. }
  427. /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
  428. first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
  429. xemaclite_alignedread(addr, etherrxbuff, first_read);
  430. /* Detect real packet size */
  431. eth = (struct ethernet_hdr *)etherrxbuff;
  432. switch (ntohs(eth->et_protlen)) {
  433. case PROT_ARP:
  434. length = first_read;
  435. debug("ARP Packet %x\n", length);
  436. break;
  437. case PROT_IP:
  438. ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
  439. length = ntohs(ip->ip_len);
  440. length += ETHER_HDR_SIZE + ETH_FCS_LEN;
  441. debug("IP Packet %x\n", length);
  442. break;
  443. default:
  444. debug("Other Packet\n");
  445. length = PKTSIZE;
  446. break;
  447. }
  448. /* Read the rest of the packet which is longer then first read */
  449. if (length != first_read)
  450. xemaclite_alignedread(addr + first_read,
  451. etherrxbuff + first_read,
  452. length - first_read);
  453. /* Acknowledge the frame */
  454. reg = __raw_readl(ack);
  455. reg &= ~XEL_RSR_RECV_DONE_MASK;
  456. __raw_writel(reg, ack);
  457. debug("Packet receive from 0x%p, length %dB\n", addr, length);
  458. *packetp = etherrxbuff;
  459. return length;
  460. }
  461. static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
  462. int devad, int reg)
  463. {
  464. u32 ret;
  465. u16 val = 0;
  466. ret = phyread(bus->priv, addr, reg, &val);
  467. debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
  468. return val;
  469. }
  470. static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
  471. int reg, u16 value)
  472. {
  473. debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
  474. return phywrite(bus->priv, addr, reg, value);
  475. }
  476. static int emaclite_probe(struct udevice *dev)
  477. {
  478. struct xemaclite *emaclite = dev_get_priv(dev);
  479. int ret;
  480. emaclite->bus = mdio_alloc();
  481. emaclite->bus->read = emaclite_miiphy_read;
  482. emaclite->bus->write = emaclite_miiphy_write;
  483. emaclite->bus->priv = emaclite;
  484. ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
  485. if (ret)
  486. return ret;
  487. return 0;
  488. }
  489. static int emaclite_remove(struct udevice *dev)
  490. {
  491. struct xemaclite *emaclite = dev_get_priv(dev);
  492. free(emaclite->phydev);
  493. mdio_unregister(emaclite->bus);
  494. mdio_free(emaclite->bus);
  495. return 0;
  496. }
  497. static const struct eth_ops emaclite_ops = {
  498. .start = emaclite_start,
  499. .send = emaclite_send,
  500. .recv = emaclite_recv,
  501. .stop = emaclite_stop,
  502. };
  503. static int emaclite_of_to_plat(struct udevice *dev)
  504. {
  505. struct eth_pdata *pdata = dev_get_plat(dev);
  506. struct xemaclite *emaclite = dev_get_priv(dev);
  507. int offset = 0;
  508. pdata->iobase = dev_read_addr(dev);
  509. emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
  510. 0x10000);
  511. emaclite->phyaddr = -1;
  512. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  513. "phy-handle");
  514. if (offset > 0)
  515. emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
  516. "reg", -1);
  517. emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  518. "xlnx,tx-ping-pong", 0);
  519. emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  520. "xlnx,rx-ping-pong", 0);
  521. printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
  522. emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
  523. return 0;
  524. }
  525. static const struct udevice_id emaclite_ids[] = {
  526. { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
  527. { }
  528. };
  529. U_BOOT_DRIVER(emaclite) = {
  530. .name = "emaclite",
  531. .id = UCLASS_ETH,
  532. .of_match = emaclite_ids,
  533. .of_to_plat = emaclite_of_to_plat,
  534. .probe = emaclite_probe,
  535. .remove = emaclite_remove,
  536. .ops = &emaclite_ops,
  537. .priv_auto = sizeof(struct xemaclite),
  538. .plat_auto = sizeof(struct eth_pdata),
  539. };