fsl_mcdmafec.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2004
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * (C) Copyright 2007 Freescale Semiconductor, Inc.
  7. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  8. *
  9. * Conversion to DM
  10. * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
  11. */
  12. #include <common.h>
  13. #include <env.h>
  14. #include <hang.h>
  15. #include <malloc.h>
  16. #include <command.h>
  17. #include <config.h>
  18. #include <net.h>
  19. #include <miiphy.h>
  20. #include <linux/delay.h>
  21. #include <linux/mii.h>
  22. #include <asm/immap.h>
  23. #include <asm/fsl_mcdmafec.h>
  24. #include "MCD_dma.h"
  25. #undef ET_DEBUG
  26. #undef MII_DEBUG
  27. /* Ethernet Transmit and Receive Buffers */
  28. #define DBUF_LENGTH 1520
  29. #define PKT_MAXBUF_SIZE 1518
  30. #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
  31. /* RxBD bits definitions */
  32. #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
  33. BD_ENET_RX_OV | BD_ENET_RX_TR)
  34. DECLARE_GLOBAL_DATA_PTR;
  35. static void init_eth_info(struct fec_info_dma *info)
  36. {
  37. /* setup Receive and Transmit buffer descriptor */
  38. #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
  39. static u32 tmp;
  40. if (info->index == 0)
  41. tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
  42. else
  43. info->rxbd = (cbd_t *)DBUF_LENGTH;
  44. info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
  45. tmp = (u32)info->rxbd;
  46. info->txbd =
  47. (cbd_t *)((u32)info->txbd + tmp +
  48. (PKTBUFSRX * sizeof(cbd_t)));
  49. tmp = (u32)info->txbd;
  50. info->txbuf =
  51. (char *)((u32)info->txbuf + tmp +
  52. (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
  53. tmp = (u32)info->txbuf;
  54. #else
  55. info->rxbd =
  56. (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
  57. (PKTBUFSRX * sizeof(cbd_t)));
  58. info->txbd =
  59. (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
  60. (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
  61. info->txbuf =
  62. (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
  63. #endif
  64. #ifdef ET_DEBUG
  65. printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
  66. #endif
  67. info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
  68. }
  69. static void fec_halt(struct udevice *dev)
  70. {
  71. struct fec_info_dma *info = dev->priv;
  72. volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
  73. int counter = 0xffff;
  74. /* issue graceful stop command to the FEC transmitter if necessary */
  75. fecp->tcr |= FEC_TCR_GTS;
  76. /* wait for graceful stop to register */
  77. while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
  78. ;
  79. /* Disable DMA tasks */
  80. MCD_killDma(info->tx_task);
  81. MCD_killDma(info->rx_task);
  82. /* Disable the Ethernet Controller */
  83. fecp->ecr &= ~FEC_ECR_ETHER_EN;
  84. /* Clear FIFO status registers */
  85. fecp->rfsr &= FIFO_ERRSTAT;
  86. fecp->tfsr &= FIFO_ERRSTAT;
  87. fecp->frst = 0x01000000;
  88. /* Issue a reset command to the FEC chip */
  89. fecp->ecr |= FEC_ECR_RESET;
  90. /* wait at least 20 clock cycles */
  91. mdelay(10);
  92. #ifdef ET_DEBUG
  93. printf("Ethernet task stopped\n");
  94. #endif
  95. }
  96. #ifdef ET_DEBUG
  97. static void dbg_fec_regs(struct eth_device *dev)
  98. {
  99. struct fec_info_dma *info = dev->priv;
  100. volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
  101. printf("=====\n");
  102. printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
  103. printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
  104. printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
  105. printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
  106. printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
  107. printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
  108. printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
  109. printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
  110. printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
  111. printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
  112. printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
  113. printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
  114. printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
  115. printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
  116. printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
  117. printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
  118. printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
  119. printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
  120. printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
  121. printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
  122. printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
  123. printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
  124. printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
  125. printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
  126. printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
  127. printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
  128. printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
  129. printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
  130. printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
  131. printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
  132. printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
  133. printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
  134. printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
  135. printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
  136. printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
  137. }
  138. #endif
  139. static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
  140. {
  141. struct bd_info *bd = gd->bd;
  142. if ((dup_spd >> 16) == FULL) {
  143. /* Set maximum frame length */
  144. fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
  145. FEC_RCR_PROM | 0x100;
  146. fecp->tcr = FEC_TCR_FDEN;
  147. } else {
  148. /* Half duplex mode */
  149. fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
  150. FEC_RCR_MII_MODE | FEC_RCR_DRT;
  151. fecp->tcr &= ~FEC_TCR_FDEN;
  152. }
  153. if ((dup_spd & 0xFFFF) == _100BASET) {
  154. #ifdef MII_DEBUG
  155. printf("100Mbps\n");
  156. #endif
  157. bd->bi_ethspeed = 100;
  158. } else {
  159. #ifdef MII_DEBUG
  160. printf("10Mbps\n");
  161. #endif
  162. bd->bi_ethspeed = 10;
  163. }
  164. }
  165. static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
  166. {
  167. u8 curr_byte; /* byte for which to compute the CRC */
  168. int byte; /* loop - counter */
  169. int bit; /* loop - counter */
  170. u32 crc = 0xffffffff; /* initial value */
  171. for (byte = 0; byte < 6; byte++) {
  172. curr_byte = mac[byte];
  173. for (bit = 0; bit < 8; bit++) {
  174. if ((curr_byte & 0x01) ^ (crc & 0x01)) {
  175. crc >>= 1;
  176. crc = crc ^ 0xedb88320;
  177. } else {
  178. crc >>= 1;
  179. }
  180. curr_byte >>= 1;
  181. }
  182. }
  183. crc = crc >> 26;
  184. /* Set individual hash table register */
  185. if (crc >= 32) {
  186. fecp->ialr = (1 << (crc - 32));
  187. fecp->iaur = 0;
  188. } else {
  189. fecp->ialr = 0;
  190. fecp->iaur = (1 << crc);
  191. }
  192. /* Set physical address */
  193. fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
  194. fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
  195. /* Clear multicast address hash table */
  196. fecp->gaur = 0;
  197. fecp->galr = 0;
  198. }
  199. static int fec_init(struct udevice *dev)
  200. {
  201. struct fec_info_dma *info = dev->priv;
  202. volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
  203. int rval, i;
  204. uchar enetaddr[6];
  205. #ifdef ET_DEBUG
  206. printf("fec_init: iobase 0x%08x ...\n", info->iobase);
  207. #endif
  208. fecpin_setclear(info, 1);
  209. fec_halt(dev);
  210. #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
  211. defined (CONFIG_SYS_DISCOVER_PHY)
  212. mii_init();
  213. set_fec_duplex_speed(fecp, info->dup_spd);
  214. #else
  215. #ifndef CONFIG_SYS_DISCOVER_PHY
  216. set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
  217. #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
  218. #endif /* CONFIG_CMD_MII || CONFIG_MII */
  219. /* We use strictly polling mode only */
  220. fecp->eimr = 0;
  221. /* Clear any pending interrupt */
  222. fecp->eir = 0xffffffff;
  223. /* Set station address */
  224. if (info->index == 0)
  225. rval = eth_env_get_enetaddr("ethaddr", enetaddr);
  226. else
  227. rval = eth_env_get_enetaddr("eth1addr", enetaddr);
  228. if (!rval) {
  229. puts("Please set a valid MAC address\n");
  230. return -EINVAL;
  231. }
  232. fec_set_hwaddr(fecp, enetaddr);
  233. /* Set Opcode/Pause Duration Register */
  234. fecp->opd = 0x00010020;
  235. /* Setup Buffers and Buffer Descriptors */
  236. info->rx_idx = 0;
  237. info->tx_idx = 0;
  238. /* Setup Receiver Buffer Descriptors (13.14.24.18)
  239. * Settings: Empty, Wrap */
  240. for (i = 0; i < PKTBUFSRX; i++) {
  241. info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  242. info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
  243. info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
  244. }
  245. info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  246. /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  247. * Settings: Last, Tx CRC */
  248. for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
  249. info->txbd[i].cbd_sc = 0;
  250. info->txbd[i].cbd_datlen = 0;
  251. info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
  252. }
  253. info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
  254. info->used_tbd_idx = 0;
  255. info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
  256. /* Set Rx FIFO alarm and granularity value */
  257. fecp->rfcr = 0x0c000000;
  258. fecp->rfar = 0x0000030c;
  259. /* Set Tx FIFO granularity value */
  260. fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
  261. fecp->tfar = 0x00000080;
  262. fecp->tfwr = 0x2;
  263. fecp->ctcwr = 0x03000000;
  264. /* Enable DMA receive task */
  265. MCD_startDma(info->rx_task,
  266. (s8 *)info->rxbd,
  267. 0,
  268. (s8 *)&fecp->rfdr,
  269. 4,
  270. 0,
  271. 4,
  272. info->rx_init,
  273. info->rx_pri,
  274. (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
  275. (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
  276. );
  277. /* Enable DMA tx task with no ready buffer descriptors */
  278. MCD_startDma(info->tx_task,
  279. (s8 *)info->txbd,
  280. 0,
  281. (s8 *)&fecp->tfdr,
  282. 4,
  283. 0,
  284. 4,
  285. info->tx_init,
  286. info->tx_pri,
  287. (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
  288. (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
  289. );
  290. /* Now enable the transmit and receive processing */
  291. fecp->ecr |= FEC_ECR_ETHER_EN;
  292. return 0;
  293. }
  294. static int mcdmafec_init(struct udevice *dev)
  295. {
  296. return fec_init(dev);
  297. }
  298. static int mcdmafec_send(struct udevice *dev, void *packet, int length)
  299. {
  300. struct fec_info_dma *info = dev->priv;
  301. cbd_t *p_tbd, *p_used_tbd;
  302. u16 phy_status;
  303. miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
  304. /* process all the consumed TBDs */
  305. while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
  306. p_used_tbd = &info->txbd[info->used_tbd_idx];
  307. if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
  308. #ifdef ET_DEBUG
  309. printf("Cannot clean TBD %d, in use\n",
  310. info->clean_tbd_num);
  311. #endif
  312. return 0;
  313. }
  314. /* clean this buffer descriptor */
  315. if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
  316. p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
  317. else
  318. p_used_tbd->cbd_sc = 0;
  319. /* update some indeces for a correct handling of TBD ring */
  320. info->clean_tbd_num++;
  321. info->used_tbd_idx = (info->used_tbd_idx + 1)
  322. % CONFIG_SYS_TX_ETH_BUFFER;
  323. }
  324. /* Check for valid length of data. */
  325. if (length > 1500 || length <= 0)
  326. return -1;
  327. /* Check the number of vacant TxBDs. */
  328. if (info->clean_tbd_num < 1) {
  329. printf("No available TxBDs ...\n");
  330. return -1;
  331. }
  332. /* Get the first TxBD to send the mac header */
  333. p_tbd = &info->txbd[info->tx_idx];
  334. p_tbd->cbd_datlen = length;
  335. p_tbd->cbd_bufaddr = (u32)packet;
  336. p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
  337. info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
  338. /* Enable DMA transmit task */
  339. MCD_continDma(info->tx_task);
  340. info->clean_tbd_num -= 1;
  341. /* wait until frame is sent . */
  342. while (p_tbd->cbd_sc & BD_ENET_TX_READY)
  343. udelay(10);
  344. return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
  345. }
  346. static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
  347. {
  348. struct fec_info_dma *info = dev->priv;
  349. volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
  350. cbd_t *prbd = &info->rxbd[info->rx_idx];
  351. u32 ievent;
  352. int frame_length, len = 0;
  353. /* Check if any critical events have happened */
  354. ievent = fecp->eir;
  355. if (ievent != 0) {
  356. fecp->eir = ievent;
  357. if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
  358. printf("fec_recv: error\n");
  359. fec_halt(dev);
  360. fec_init(dev);
  361. return 0;
  362. }
  363. if (ievent & FEC_EIR_HBERR) {
  364. /* Heartbeat error */
  365. fecp->tcr |= FEC_TCR_GTS;
  366. }
  367. if (ievent & FEC_EIR_GRA) {
  368. /* Graceful stop complete */
  369. if (fecp->tcr & FEC_TCR_GTS) {
  370. printf("fec_recv: tcr_gts\n");
  371. fec_halt(dev);
  372. fecp->tcr &= ~FEC_TCR_GTS;
  373. fec_init(dev);
  374. }
  375. }
  376. }
  377. if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
  378. if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
  379. !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
  380. ((prbd->cbd_datlen - 4) > 14)) {
  381. /* Get buffer address and size */
  382. frame_length = prbd->cbd_datlen - 4;
  383. /* Fill the buffer and pass it to upper layers */
  384. net_process_received_packet((uchar *)prbd->cbd_bufaddr,
  385. frame_length);
  386. len = frame_length;
  387. }
  388. /* Reset buffer descriptor as empty */
  389. if (info->rx_idx == (PKTBUFSRX - 1))
  390. prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  391. else
  392. prbd->cbd_sc = BD_ENET_RX_EMPTY;
  393. prbd->cbd_datlen = PKTSIZE_ALIGN;
  394. /* Now, we have an empty RxBD, restart the DMA receive task */
  395. MCD_continDma(info->rx_task);
  396. /* Increment BD count */
  397. info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
  398. }
  399. return len;
  400. }
  401. static void mcdmafec_halt(struct udevice *dev)
  402. {
  403. fec_halt(dev);
  404. }
  405. static const struct eth_ops mcdmafec_ops = {
  406. .start = mcdmafec_init,
  407. .send = mcdmafec_send,
  408. .recv = mcdmafec_recv,
  409. .stop = mcdmafec_halt,
  410. };
  411. /*
  412. * Boot sequence, called just after mcffec_of_to_plat,
  413. * as DM way, it replaces old mcffec_initialize.
  414. */
  415. static int mcdmafec_probe(struct udevice *dev)
  416. {
  417. struct fec_info_dma *info = dev->priv;
  418. struct eth_pdata *pdata = dev_get_plat(dev);
  419. int node = dev_of_offset(dev);
  420. int retval;
  421. const u32 *val;
  422. info->index = dev_seq(dev);
  423. info->iobase = pdata->iobase;
  424. info->miibase = pdata->iobase;
  425. info->phy_addr = -1;
  426. val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
  427. if (val)
  428. info->rx_task = fdt32_to_cpu(*val);
  429. val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
  430. if (val)
  431. info->tx_task = fdt32_to_cpu(*val);
  432. val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
  433. if (val)
  434. info->rx_pri = fdt32_to_cpu(*val);
  435. val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
  436. if (val)
  437. info->tx_pri = fdt32_to_cpu(*val);
  438. val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
  439. if (val)
  440. info->rx_init = fdt32_to_cpu(*val);
  441. val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
  442. if (val)
  443. info->tx_init = fdt32_to_cpu(*val);
  444. #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
  445. u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
  446. #endif
  447. init_eth_info(info);
  448. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  449. info->bus = mdio_alloc();
  450. if (!info->bus)
  451. return -ENOMEM;
  452. strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
  453. info->bus->read = mcffec_miiphy_read;
  454. info->bus->write = mcffec_miiphy_write;
  455. retval = mdio_register(info->bus);
  456. if (retval < 0)
  457. return retval;
  458. #endif
  459. return 0;
  460. }
  461. static int mcdmafec_remove(struct udevice *dev)
  462. {
  463. struct fec_info_dma *priv = dev_get_priv(dev);
  464. mdio_unregister(priv->bus);
  465. mdio_free(priv->bus);
  466. return 0;
  467. }
  468. /*
  469. * Boot sequence, called 1st
  470. */
  471. static int mcdmafec_of_to_plat(struct udevice *dev)
  472. {
  473. struct eth_pdata *pdata = dev_get_plat(dev);
  474. const u32 *val;
  475. pdata->iobase = dev_read_addr(dev);
  476. /* Default to 10Mbit/s */
  477. pdata->max_speed = 10;
  478. val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
  479. if (val)
  480. pdata->max_speed = fdt32_to_cpu(*val);
  481. return 0;
  482. }
  483. static const struct udevice_id mcdmafec_ids[] = {
  484. { .compatible = "fsl,mcf-dma-fec" },
  485. { }
  486. };
  487. U_BOOT_DRIVER(mcffec) = {
  488. .name = "mcdmafec",
  489. .id = UCLASS_ETH,
  490. .of_match = mcdmafec_ids,
  491. .of_to_plat = mcdmafec_of_to_plat,
  492. .probe = mcdmafec_probe,
  493. .remove = mcdmafec_remove,
  494. .ops = &mcdmafec_ops,
  495. .priv_auto = sizeof(struct fec_info_dma),
  496. .plat_auto = sizeof(struct eth_pdata),
  497. };