spi-nor-tiny.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
  4. * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
  5. *
  6. * Copyright (C) 2005, Intec Automation Inc.
  7. * Copyright (C) 2014, Freescale Semiconductor, Inc.
  8. *
  9. * Synced from Linux v4.19
  10. */
  11. #include <common.h>
  12. #include <log.h>
  13. #include <dm/device_compat.h>
  14. #include <linux/err.h>
  15. #include <linux/errno.h>
  16. #include <linux/log2.h>
  17. #include <linux/math64.h>
  18. #include <linux/sizes.h>
  19. #include <linux/mtd/mtd.h>
  20. #include <linux/mtd/spi-nor.h>
  21. #include <spi-mem.h>
  22. #include <spi.h>
  23. #include "sf_internal.h"
  24. /* Define max times to check status register before we give up. */
  25. /*
  26. * For everything but full-chip erase; probably could be much smaller, but kept
  27. * around for safety for now
  28. */
  29. #define HZ CONFIG_SYS_HZ
  30. #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
  31. static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
  32. *op, void *buf)
  33. {
  34. if (op->data.dir == SPI_MEM_DATA_IN)
  35. op->data.buf.in = buf;
  36. else
  37. op->data.buf.out = buf;
  38. return spi_mem_exec_op(nor->spi, op);
  39. }
  40. static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
  41. {
  42. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
  43. SPI_MEM_OP_NO_ADDR,
  44. SPI_MEM_OP_NO_DUMMY,
  45. SPI_MEM_OP_DATA_IN(len, NULL, 1));
  46. int ret;
  47. ret = spi_nor_read_write_reg(nor, &op, val);
  48. if (ret < 0) {
  49. /*
  50. * spi_slave does not have a struct udevice member without DM,
  51. * so use the bus and cs instead.
  52. */
  53. #if CONFIG_IS_ENABLED(DM_SPI)
  54. dev_dbg(nor->spi->dev, "error %d reading %x\n", ret,
  55. code);
  56. #else
  57. log_debug("spi%u.%u: error %d reading %x\n",
  58. nor->spi->bus, nor->spi->cs, ret, code);
  59. #endif
  60. }
  61. return ret;
  62. }
  63. static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  64. {
  65. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
  66. SPI_MEM_OP_NO_ADDR,
  67. SPI_MEM_OP_NO_DUMMY,
  68. SPI_MEM_OP_DATA_OUT(len, NULL, 1));
  69. return spi_nor_read_write_reg(nor, &op, buf);
  70. }
  71. static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
  72. u_char *buf)
  73. {
  74. struct spi_mem_op op =
  75. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
  76. SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
  77. SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
  78. SPI_MEM_OP_DATA_IN(len, buf, 1));
  79. size_t remaining = len;
  80. int ret;
  81. /* get transfer protocols. */
  82. op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
  83. op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
  84. op.dummy.buswidth = op.addr.buswidth;
  85. op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
  86. /* convert the dummy cycles to the number of bytes */
  87. op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
  88. while (remaining) {
  89. op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
  90. ret = spi_mem_adjust_op_size(nor->spi, &op);
  91. if (ret)
  92. return ret;
  93. ret = spi_mem_exec_op(nor->spi, &op);
  94. if (ret)
  95. return ret;
  96. op.addr.val += op.data.nbytes;
  97. remaining -= op.data.nbytes;
  98. op.data.buf.in += op.data.nbytes;
  99. }
  100. return len;
  101. }
  102. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  103. /*
  104. * Read configuration register, returning its value in the
  105. * location. Return the configuration register value.
  106. * Returns negative if error occurred.
  107. */
  108. static int read_cr(struct spi_nor *nor)
  109. {
  110. int ret;
  111. u8 val;
  112. ret = spi_nor_read_reg(nor, SPINOR_OP_RDCR, &val, 1);
  113. if (ret < 0) {
  114. dev_dbg(nor->dev, "error %d reading CR\n", ret);
  115. return ret;
  116. }
  117. return val;
  118. }
  119. #endif
  120. /*
  121. * Write status register 1 byte
  122. * Returns negative if error occurred.
  123. */
  124. static inline int write_sr(struct spi_nor *nor, u8 val)
  125. {
  126. nor->cmd_buf[0] = val;
  127. return spi_nor_write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
  128. }
  129. /*
  130. * Set write enable latch with Write Enable command.
  131. * Returns negative if error occurred.
  132. */
  133. static inline int write_enable(struct spi_nor *nor)
  134. {
  135. return spi_nor_write_reg(nor, SPINOR_OP_WREN, NULL, 0);
  136. }
  137. /*
  138. * Send write disable instruction to the chip.
  139. */
  140. static inline int write_disable(struct spi_nor *nor)
  141. {
  142. return spi_nor_write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
  143. }
  144. static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
  145. {
  146. return mtd->priv;
  147. }
  148. static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
  149. {
  150. size_t i;
  151. for (i = 0; i < size; i++)
  152. if (table[i][0] == opcode)
  153. return table[i][1];
  154. /* No conversion found, keep input op code. */
  155. return opcode;
  156. }
  157. static inline u8 spi_nor_convert_3to4_read(u8 opcode)
  158. {
  159. static const u8 spi_nor_3to4_read[][2] = {
  160. { SPINOR_OP_READ, SPINOR_OP_READ_4B },
  161. { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
  162. { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
  163. { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
  164. { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
  165. { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
  166. };
  167. return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
  168. ARRAY_SIZE(spi_nor_3to4_read));
  169. }
  170. static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
  171. const struct flash_info *info)
  172. {
  173. nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
  174. }
  175. /* Enable/disable 4-byte addressing mode. */
  176. static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
  177. int enable)
  178. {
  179. int status;
  180. bool need_wren = false;
  181. u8 cmd;
  182. switch (JEDEC_MFR(info)) {
  183. case SNOR_MFR_ST:
  184. case SNOR_MFR_MICRON:
  185. /* Some Micron need WREN command; all will accept it */
  186. need_wren = true;
  187. case SNOR_MFR_MACRONIX:
  188. case SNOR_MFR_WINBOND:
  189. if (need_wren)
  190. write_enable(nor);
  191. cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
  192. status = spi_nor_write_reg(nor, cmd, NULL, 0);
  193. if (need_wren)
  194. write_disable(nor);
  195. if (!status && !enable &&
  196. JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
  197. /*
  198. * On Winbond W25Q256FV, leaving 4byte mode causes
  199. * the Extended Address Register to be set to 1, so all
  200. * 3-byte-address reads come from the second 16M.
  201. * We must clear the register to enable normal behavior.
  202. */
  203. write_enable(nor);
  204. nor->cmd_buf[0] = 0;
  205. spi_nor_write_reg(nor, SPINOR_OP_WREAR,
  206. nor->cmd_buf, 1);
  207. write_disable(nor);
  208. }
  209. return status;
  210. default:
  211. /* Spansion style */
  212. nor->cmd_buf[0] = enable << 7;
  213. return spi_nor_write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
  214. }
  215. }
  216. #if defined(CONFIG_SPI_FLASH_SPANSION) || \
  217. defined(CONFIG_SPI_FLASH_WINBOND) || \
  218. defined(CONFIG_SPI_FLASH_MACRONIX)
  219. /*
  220. * Read the status register, returning its value in the location
  221. * Return the status register value.
  222. * Returns negative if error occurred.
  223. */
  224. static int read_sr(struct spi_nor *nor)
  225. {
  226. int ret;
  227. u8 val;
  228. ret = spi_nor_read_reg(nor, SPINOR_OP_RDSR, &val, 1);
  229. if (ret < 0) {
  230. pr_debug("error %d reading SR\n", (int)ret);
  231. return ret;
  232. }
  233. return val;
  234. }
  235. /*
  236. * Read the flag status register, returning its value in the location
  237. * Return the status register value.
  238. * Returns negative if error occurred.
  239. */
  240. static int read_fsr(struct spi_nor *nor)
  241. {
  242. int ret;
  243. u8 val;
  244. ret = spi_nor_read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
  245. if (ret < 0) {
  246. pr_debug("error %d reading FSR\n", ret);
  247. return ret;
  248. }
  249. return val;
  250. }
  251. static int spi_nor_sr_ready(struct spi_nor *nor)
  252. {
  253. int sr = read_sr(nor);
  254. if (sr < 0)
  255. return sr;
  256. return !(sr & SR_WIP);
  257. }
  258. static int spi_nor_fsr_ready(struct spi_nor *nor)
  259. {
  260. int fsr = read_fsr(nor);
  261. if (fsr < 0)
  262. return fsr;
  263. return fsr & FSR_READY;
  264. }
  265. static int spi_nor_ready(struct spi_nor *nor)
  266. {
  267. int sr, fsr;
  268. sr = spi_nor_sr_ready(nor);
  269. if (sr < 0)
  270. return sr;
  271. fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
  272. if (fsr < 0)
  273. return fsr;
  274. return sr && fsr;
  275. }
  276. /*
  277. * Service routine to read status register until ready, or timeout occurs.
  278. * Returns non-zero if error.
  279. */
  280. static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
  281. unsigned long timeout)
  282. {
  283. unsigned long timebase;
  284. int ret;
  285. timebase = get_timer(0);
  286. while (get_timer(timebase) < timeout) {
  287. ret = spi_nor_ready(nor);
  288. if (ret < 0)
  289. return ret;
  290. if (ret)
  291. return 0;
  292. }
  293. dev_err(nor->dev, "flash operation timed out\n");
  294. return -ETIMEDOUT;
  295. }
  296. static int spi_nor_wait_till_ready(struct spi_nor *nor)
  297. {
  298. return spi_nor_wait_till_ready_with_timeout(nor,
  299. DEFAULT_READY_WAIT_JIFFIES);
  300. }
  301. #endif /* CONFIG_SPI_FLASH_SPANSION */
  302. /*
  303. * Erase an address range on the nor chip. The address range may extend
  304. * one or more erase sectors. Return an error is there is a problem erasing.
  305. */
  306. static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
  307. {
  308. return -ENOTSUPP;
  309. }
  310. static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
  311. {
  312. int tmp;
  313. u8 id[SPI_NOR_MAX_ID_LEN];
  314. const struct flash_info *info;
  315. tmp = spi_nor_read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
  316. if (tmp < 0) {
  317. dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
  318. return ERR_PTR(tmp);
  319. }
  320. info = spi_nor_ids;
  321. for (; info->sector_size != 0; info++) {
  322. if (info->id_len) {
  323. if (!memcmp(info->id, id, info->id_len))
  324. return info;
  325. }
  326. }
  327. dev_dbg(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
  328. id[0], id[1], id[2]);
  329. return ERR_PTR(-EMEDIUMTYPE);
  330. }
  331. static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
  332. size_t *retlen, u_char *buf)
  333. {
  334. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  335. int ret;
  336. dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
  337. while (len) {
  338. loff_t addr = from;
  339. ret = spi_nor_read_data(nor, addr, len, buf);
  340. if (ret == 0) {
  341. /* We shouldn't see 0-length reads */
  342. ret = -EIO;
  343. goto read_err;
  344. }
  345. if (ret < 0)
  346. goto read_err;
  347. *retlen += ret;
  348. buf += ret;
  349. from += ret;
  350. len -= ret;
  351. }
  352. ret = 0;
  353. read_err:
  354. return ret;
  355. }
  356. /*
  357. * Write an address range to the nor chip. Data must be written in
  358. * FLASH_PAGESIZE chunks. The address range may be any size provided
  359. * it is within the physical boundaries.
  360. */
  361. static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
  362. size_t *retlen, const u_char *buf)
  363. {
  364. return -ENOTSUPP;
  365. }
  366. #ifdef CONFIG_SPI_FLASH_MACRONIX
  367. /**
  368. * macronix_quad_enable() - set QE bit in Status Register.
  369. * @nor: pointer to a 'struct spi_nor'
  370. *
  371. * Set the Quad Enable (QE) bit in the Status Register.
  372. *
  373. * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
  374. *
  375. * Return: 0 on success, -errno otherwise.
  376. */
  377. static int macronix_quad_enable(struct spi_nor *nor)
  378. {
  379. int ret, val;
  380. val = read_sr(nor);
  381. if (val < 0)
  382. return val;
  383. if (val & SR_QUAD_EN_MX)
  384. return 0;
  385. write_enable(nor);
  386. write_sr(nor, val | SR_QUAD_EN_MX);
  387. ret = spi_nor_wait_till_ready(nor);
  388. if (ret)
  389. return ret;
  390. ret = read_sr(nor);
  391. if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
  392. dev_err(nor->dev, "Macronix Quad bit not set\n");
  393. return -EINVAL;
  394. }
  395. return 0;
  396. }
  397. #endif
  398. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  399. /*
  400. * Write status Register and configuration register with 2 bytes
  401. * The first byte will be written to the status register, while the
  402. * second byte will be written to the configuration register.
  403. * Return negative if error occurred.
  404. */
  405. static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
  406. {
  407. int ret;
  408. write_enable(nor);
  409. ret = spi_nor_write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
  410. if (ret < 0) {
  411. dev_dbg(nor->dev,
  412. "error while writing configuration register\n");
  413. return -EINVAL;
  414. }
  415. ret = spi_nor_wait_till_ready(nor);
  416. if (ret) {
  417. dev_dbg(nor->dev,
  418. "timeout while writing configuration register\n");
  419. return ret;
  420. }
  421. return 0;
  422. }
  423. /**
  424. * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
  425. * @nor: pointer to a 'struct spi_nor'
  426. *
  427. * Set the Quad Enable (QE) bit in the Configuration Register.
  428. * This function should be used with QSPI memories supporting the Read
  429. * Configuration Register (35h) instruction.
  430. *
  431. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  432. * memories.
  433. *
  434. * Return: 0 on success, -errno otherwise.
  435. */
  436. static int spansion_read_cr_quad_enable(struct spi_nor *nor)
  437. {
  438. u8 sr_cr[2];
  439. int ret;
  440. /* Check current Quad Enable bit value. */
  441. ret = read_cr(nor);
  442. if (ret < 0) {
  443. dev_dbg(nor->dev,
  444. "error while reading configuration register\n");
  445. return -EINVAL;
  446. }
  447. if (ret & CR_QUAD_EN_SPAN)
  448. return 0;
  449. sr_cr[1] = ret | CR_QUAD_EN_SPAN;
  450. /* Keep the current value of the Status Register. */
  451. ret = read_sr(nor);
  452. if (ret < 0) {
  453. dev_dbg(nor->dev, "error while reading status register\n");
  454. return -EINVAL;
  455. }
  456. sr_cr[0] = ret;
  457. ret = write_sr_cr(nor, sr_cr);
  458. if (ret)
  459. return ret;
  460. /* Read back and check it. */
  461. ret = read_cr(nor);
  462. if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
  463. dev_dbg(nor->dev, "Spansion Quad bit not set\n");
  464. return -EINVAL;
  465. }
  466. return 0;
  467. }
  468. #endif /* CONFIG_SPI_FLASH_SPANSION */
  469. struct spi_nor_read_command {
  470. u8 num_mode_clocks;
  471. u8 num_wait_states;
  472. u8 opcode;
  473. enum spi_nor_protocol proto;
  474. };
  475. enum spi_nor_read_command_index {
  476. SNOR_CMD_READ,
  477. SNOR_CMD_READ_FAST,
  478. /* Quad SPI */
  479. SNOR_CMD_READ_1_1_4,
  480. SNOR_CMD_READ_MAX
  481. };
  482. struct spi_nor_flash_parameter {
  483. struct spi_nor_hwcaps hwcaps;
  484. struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
  485. };
  486. static void
  487. spi_nor_set_read_settings(struct spi_nor_read_command *read,
  488. u8 num_mode_clocks,
  489. u8 num_wait_states,
  490. u8 opcode,
  491. enum spi_nor_protocol proto)
  492. {
  493. read->num_mode_clocks = num_mode_clocks;
  494. read->num_wait_states = num_wait_states;
  495. read->opcode = opcode;
  496. read->proto = proto;
  497. }
  498. static int spi_nor_init_params(struct spi_nor *nor,
  499. const struct flash_info *info,
  500. struct spi_nor_flash_parameter *params)
  501. {
  502. /* (Fast) Read settings. */
  503. params->hwcaps.mask = SNOR_HWCAPS_READ;
  504. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
  505. 0, 0, SPINOR_OP_READ,
  506. SNOR_PROTO_1_1_1);
  507. if (!(info->flags & SPI_NOR_NO_FR)) {
  508. params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
  509. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
  510. 0, 8, SPINOR_OP_READ_FAST,
  511. SNOR_PROTO_1_1_1);
  512. }
  513. if (info->flags & SPI_NOR_QUAD_READ) {
  514. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  515. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
  516. 0, 8, SPINOR_OP_READ_1_1_4,
  517. SNOR_PROTO_1_1_4);
  518. }
  519. return 0;
  520. }
  521. static int spi_nor_select_read(struct spi_nor *nor,
  522. const struct spi_nor_flash_parameter *params,
  523. u32 shared_hwcaps)
  524. {
  525. int best_match = shared_hwcaps & SNOR_HWCAPS_READ_MASK;
  526. int cmd;
  527. const struct spi_nor_read_command *read;
  528. if (best_match < 0)
  529. return -EINVAL;
  530. if (best_match & SNOR_HWCAPS_READ_1_1_4)
  531. cmd = SNOR_CMD_READ_1_1_4;
  532. else if (best_match & SNOR_HWCAPS_READ_FAST)
  533. cmd = SNOR_CMD_READ_FAST;
  534. else
  535. cmd = SNOR_CMD_READ;
  536. read = &params->reads[cmd];
  537. nor->read_opcode = read->opcode;
  538. nor->read_proto = read->proto;
  539. /*
  540. * In the spi-nor framework, we don't need to make the difference
  541. * between mode clock cycles and wait state clock cycles.
  542. * Indeed, the value of the mode clock cycles is used by a QSPI
  543. * flash memory to know whether it should enter or leave its 0-4-4
  544. * (Continuous Read / XIP) mode.
  545. * eXecution In Place is out of the scope of the mtd sub-system.
  546. * Hence we choose to merge both mode and wait state clock cycles
  547. * into the so called dummy clock cycles.
  548. */
  549. nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
  550. return 0;
  551. }
  552. static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
  553. const struct spi_nor_flash_parameter *params,
  554. const struct spi_nor_hwcaps *hwcaps)
  555. {
  556. u32 shared_mask;
  557. int err;
  558. /*
  559. * Keep only the hardware capabilities supported by both the SPI
  560. * controller and the SPI flash memory.
  561. */
  562. shared_mask = hwcaps->mask & params->hwcaps.mask;
  563. /* Select the (Fast) Read command. */
  564. err = spi_nor_select_read(nor, params, shared_mask);
  565. if (err) {
  566. dev_dbg(nor->dev,
  567. "can't select read settings supported by both the SPI controller and memory.\n");
  568. return err;
  569. }
  570. /* Enable Quad I/O if needed. */
  571. if (spi_nor_get_protocol_width(nor->read_proto) == 4) {
  572. switch (JEDEC_MFR(info)) {
  573. #ifdef CONFIG_SPI_FLASH_MACRONIX
  574. case SNOR_MFR_MACRONIX:
  575. err = macronix_quad_enable(nor);
  576. break;
  577. #endif
  578. case SNOR_MFR_ST:
  579. case SNOR_MFR_MICRON:
  580. break;
  581. default:
  582. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  583. /* Kept only for backward compatibility purpose. */
  584. err = spansion_read_cr_quad_enable(nor);
  585. #endif
  586. break;
  587. }
  588. }
  589. if (err) {
  590. dev_dbg(nor->dev, "quad mode not supported\n");
  591. return err;
  592. }
  593. return 0;
  594. }
  595. static int spi_nor_init(struct spi_nor *nor)
  596. {
  597. if (nor->addr_width == 4 &&
  598. (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
  599. !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
  600. /*
  601. * If the RESET# pin isn't hooked up properly, or the system
  602. * otherwise doesn't perform a reset command in the boot
  603. * sequence, it's impossible to 100% protect against unexpected
  604. * reboots (e.g., crashes). Warn the user (or hopefully, system
  605. * designer) that this is bad.
  606. */
  607. if (nor->flags & SNOR_F_BROKEN_RESET)
  608. printf("enabling reset hack; may not recover from unexpected reboots\n");
  609. set_4byte(nor, nor->info, 1);
  610. }
  611. return 0;
  612. }
  613. int spi_nor_scan(struct spi_nor *nor)
  614. {
  615. struct spi_nor_flash_parameter params;
  616. const struct flash_info *info = NULL;
  617. struct mtd_info *mtd = &nor->mtd;
  618. struct spi_nor_hwcaps hwcaps = {
  619. .mask = SNOR_HWCAPS_READ |
  620. SNOR_HWCAPS_READ_FAST
  621. };
  622. struct spi_slave *spi = nor->spi;
  623. int ret;
  624. /* Reset SPI protocol for all commands. */
  625. nor->reg_proto = SNOR_PROTO_1_1_1;
  626. nor->read_proto = SNOR_PROTO_1_1_1;
  627. nor->write_proto = SNOR_PROTO_1_1_1;
  628. if (spi->mode & SPI_RX_QUAD)
  629. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  630. info = spi_nor_read_id(nor);
  631. if (IS_ERR_OR_NULL(info))
  632. return PTR_ERR(info);
  633. /* Parse the Serial Flash Discoverable Parameters table. */
  634. ret = spi_nor_init_params(nor, info, &params);
  635. if (ret)
  636. return ret;
  637. mtd->name = "spi-flash";
  638. mtd->priv = nor;
  639. mtd->type = MTD_NORFLASH;
  640. mtd->writesize = 1;
  641. mtd->flags = MTD_CAP_NORFLASH;
  642. mtd->size = info->sector_size * info->n_sectors;
  643. mtd->_erase = spi_nor_erase;
  644. mtd->_read = spi_nor_read;
  645. mtd->_write = spi_nor_write;
  646. nor->size = mtd->size;
  647. if (info->flags & USE_FSR)
  648. nor->flags |= SNOR_F_USE_FSR;
  649. if (info->flags & USE_CLSR)
  650. nor->flags |= SNOR_F_USE_CLSR;
  651. if (info->flags & SPI_NOR_NO_FR)
  652. params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
  653. /*
  654. * Configure the SPI memory:
  655. * - select op codes for (Fast) Read, Page Program and Sector Erase.
  656. * - set the number of dummy cycles (mode cycles + wait states).
  657. * - set the SPI protocols for register and memory accesses.
  658. * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
  659. */
  660. ret = spi_nor_setup(nor, info, &params, &hwcaps);
  661. if (ret)
  662. return ret;
  663. if (nor->addr_width) {
  664. /* already configured from SFDP */
  665. } else if (info->addr_width) {
  666. nor->addr_width = info->addr_width;
  667. } else if (mtd->size > 0x1000000) {
  668. /* enable 4-byte addressing if the device exceeds 16MiB */
  669. nor->addr_width = 4;
  670. if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
  671. info->flags & SPI_NOR_4B_OPCODES)
  672. spi_nor_set_4byte_opcodes(nor, info);
  673. } else {
  674. nor->addr_width = 3;
  675. }
  676. if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
  677. dev_dbg(nor->dev, "address width is too large: %u\n",
  678. nor->addr_width);
  679. return -EINVAL;
  680. }
  681. /* Send all the required SPI flash commands to initialize device */
  682. nor->info = info;
  683. ret = spi_nor_init(nor);
  684. if (ret)
  685. return ret;
  686. return 0;
  687. }