renesas_rpc_hf.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas RCar Gen3 RPC HyperFlash driver
  4. *
  5. * Copyright (C) 2016 Renesas Electronics Corporation
  6. * Copyright (C) 2016 Cogent Embedded, Inc.
  7. * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  8. */
  9. #include <common.h>
  10. #include <malloc.h>
  11. #include <asm/io.h>
  12. #include <clk.h>
  13. #include <dm.h>
  14. #include <dm/device_compat.h>
  15. #include <dm/of_access.h>
  16. #include <errno.h>
  17. #include <fdt_support.h>
  18. #include <flash.h>
  19. #include <mtd.h>
  20. #include <wait_bit.h>
  21. #include <linux/bitops.h>
  22. #include <mtd/cfi_flash.h>
  23. #define RPC_CMNCR 0x0000 /* R/W */
  24. #define RPC_CMNCR_MD BIT(31)
  25. #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
  26. #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
  27. #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
  28. #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
  29. #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
  30. RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
  31. #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
  32. #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
  33. #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
  34. #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
  35. RPC_CMNCR_IO3FV(3))
  36. #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
  37. #define RPC_SSLDR 0x0004 /* R/W */
  38. #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
  39. #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
  40. #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
  41. #define RPC_DRCR 0x000C /* R/W */
  42. #define RPC_DRCR_SSLN BIT(24)
  43. #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
  44. #define RPC_DRCR_RCF BIT(9)
  45. #define RPC_DRCR_RBE BIT(8)
  46. #define RPC_DRCR_SSLE BIT(0)
  47. #define RPC_DRCMR 0x0010 /* R/W */
  48. #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
  49. #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
  50. #define RPC_DREAR 0x0014 /* R/W */
  51. #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
  52. #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
  53. #define RPC_DROPR 0x0018 /* R/W */
  54. #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
  55. #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
  56. #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
  57. #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
  58. #define RPC_DRENR 0x001C /* R/W */
  59. #define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
  60. #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
  61. #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
  62. #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
  63. #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
  64. #define RPC_DRENR_DME BIT(15)
  65. #define RPC_DRENR_CDE BIT(14)
  66. #define RPC_DRENR_OCDE BIT(12)
  67. #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
  68. #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
  69. #define RPC_SMCR 0x0020 /* R/W */
  70. #define RPC_SMCR_SSLKP BIT(8)
  71. #define RPC_SMCR_SPIRE BIT(2)
  72. #define RPC_SMCR_SPIWE BIT(1)
  73. #define RPC_SMCR_SPIE BIT(0)
  74. #define RPC_SMCMR 0x0024 /* R/W */
  75. #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
  76. #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
  77. #define RPC_SMADR 0x0028 /* R/W */
  78. #define RPC_SMOPR 0x002C /* R/W */
  79. #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
  80. #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
  81. #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
  82. #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
  83. #define RPC_SMENR 0x0030 /* R/W */
  84. #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
  85. #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
  86. #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
  87. #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
  88. #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
  89. #define RPC_SMENR_DME BIT(15)
  90. #define RPC_SMENR_CDE BIT(14)
  91. #define RPC_SMENR_OCDE BIT(12)
  92. #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
  93. #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
  94. #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
  95. #define RPC_SMRDR0 0x0038 /* R */
  96. #define RPC_SMRDR1 0x003C /* R */
  97. #define RPC_SMWDR0 0x0040 /* R/W */
  98. #define RPC_SMWDR1 0x0044 /* R/W */
  99. #define RPC_CMNSR 0x0048 /* R */
  100. #define RPC_CMNSR_SSLF BIT(1)
  101. #define RPC_CMNSR_TEND BIT(0)
  102. #define RPC_DRDMCR 0x0058 /* R/W */
  103. #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
  104. #define RPC_DRDRENR 0x005C /* R/W */
  105. #define RPC_DRDRENR_HYPE (0x5 << 12)
  106. #define RPC_DRDRENR_ADDRE BIT(8)
  107. #define RPC_DRDRENR_OPDRE BIT(4)
  108. #define RPC_DRDRENR_DRDRE BIT(0)
  109. #define RPC_SMDMCR 0x0060 /* R/W */
  110. #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
  111. #define RPC_SMDRENR 0x0064 /* R/W */
  112. #define RPC_SMDRENR_HYPE (0x5 << 12)
  113. #define RPC_SMDRENR_ADDRE BIT(8)
  114. #define RPC_SMDRENR_OPDRE BIT(4)
  115. #define RPC_SMDRENR_SPIDRE BIT(0)
  116. #define RPC_PHYCNT 0x007C /* R/W */
  117. #define RPC_PHYCNT_CAL BIT(31)
  118. #define PRC_PHYCNT_OCTA_AA BIT(22)
  119. #define PRC_PHYCNT_OCTA_SA BIT(23)
  120. #define PRC_PHYCNT_EXDS BIT(21)
  121. #define RPC_PHYCNT_OCT BIT(20)
  122. #define RPC_PHYCNT_WBUF2 BIT(4)
  123. #define RPC_PHYCNT_WBUF BIT(2)
  124. #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
  125. #define RPC_PHYINT 0x0088 /* R/W */
  126. #define RPC_PHYINT_RSTEN BIT(18)
  127. #define RPC_PHYINT_WPEN BIT(17)
  128. #define RPC_PHYINT_INTEN BIT(16)
  129. #define RPC_PHYINT_RST BIT(2)
  130. #define RPC_PHYINT_WP BIT(1)
  131. #define RPC_PHYINT_INT BIT(0)
  132. #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
  133. #define RPC_WBUF_SIZE 0x100
  134. static phys_addr_t rpc_base;
  135. enum rpc_hf_size {
  136. RPC_HF_SIZE_16BIT = RPC_SMENR_SPIDE(0x8),
  137. RPC_HF_SIZE_32BIT = RPC_SMENR_SPIDE(0xC),
  138. RPC_HF_SIZE_64BIT = RPC_SMENR_SPIDE(0xF),
  139. };
  140. static int rpc_hf_wait_tend(void)
  141. {
  142. void __iomem *reg = (void __iomem *)rpc_base + RPC_CMNSR;
  143. return wait_for_bit_le32(reg, RPC_CMNSR_TEND, true, 1000, 0);
  144. }
  145. static int rpc_hf_mode(bool man)
  146. {
  147. int ret;
  148. ret = rpc_hf_wait_tend();
  149. if (ret)
  150. return ret;
  151. clrsetbits_le32(rpc_base + RPC_PHYCNT,
  152. RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 |
  153. RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3),
  154. RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3));
  155. clrsetbits_le32(rpc_base + RPC_CMNCR,
  156. RPC_CMNCR_MD | RPC_CMNCR_BSZ(3),
  157. RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ |
  158. (man ? RPC_CMNCR_MD : 0) | RPC_CMNCR_BSZ(1));
  159. if (man)
  160. return 0;
  161. writel(RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF | RPC_DRCR_RBE,
  162. rpc_base + RPC_DRCR);
  163. writel(RPC_DRCMR_CMD(0xA0), rpc_base + RPC_DRCMR);
  164. writel(RPC_DRENR_CDB(2) | RPC_DRENR_OCDB(2) | RPC_DRENR_ADB(2) |
  165. RPC_DRENR_SPIDB(2) | RPC_DRENR_CDE | RPC_DRENR_OCDE |
  166. RPC_DRENR_ADE(4), rpc_base + RPC_DRENR);
  167. writel(RPC_DRDMCR_DMCYC(0xE), rpc_base + RPC_DRDMCR);
  168. writel(RPC_DRDRENR_HYPE | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE,
  169. rpc_base + RPC_DRDRENR);
  170. /* Dummy read */
  171. readl(rpc_base + RPC_DRCR);
  172. return 0;
  173. }
  174. static int rpc_hf_xfer(void *addr, u64 wdata, u64 *rdata,
  175. enum rpc_hf_size size, bool write)
  176. {
  177. int ret;
  178. u32 val;
  179. ret = rpc_hf_mode(1);
  180. if (ret)
  181. return ret;
  182. /* Submit HF address, SMCMR CMD[7] ~= CA Bit# 47 (R/nW) */
  183. writel(write ? 0 : RPC_SMCMR_CMD(0x80), rpc_base + RPC_SMCMR);
  184. writel((uintptr_t)addr >> 1, rpc_base + RPC_SMADR);
  185. writel(0x0, rpc_base + RPC_SMOPR);
  186. writel(RPC_SMDRENR_HYPE | RPC_SMDRENR_ADDRE | RPC_SMDRENR_SPIDRE,
  187. rpc_base + RPC_SMDRENR);
  188. val = RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) |
  189. RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) |
  190. RPC_SMENR_CDE | RPC_SMENR_OCDE | RPC_SMENR_ADE(4) | size;
  191. if (write) {
  192. writel(val, rpc_base + RPC_SMENR);
  193. if (size == RPC_HF_SIZE_64BIT)
  194. writeq(cpu_to_be64(wdata), rpc_base + RPC_SMWDR0);
  195. else
  196. writel(cpu_to_be32(wdata), rpc_base + RPC_SMWDR0);
  197. writel(RPC_SMCR_SPIWE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR);
  198. } else {
  199. val |= RPC_SMENR_DME;
  200. writel(RPC_SMDMCR_DMCYC(0xE), rpc_base + RPC_SMDMCR);
  201. writel(val, rpc_base + RPC_SMENR);
  202. writel(RPC_SMCR_SPIRE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR);
  203. ret = rpc_hf_wait_tend();
  204. if (ret)
  205. return ret;
  206. if (size == RPC_HF_SIZE_64BIT)
  207. *rdata = be64_to_cpu(readq(rpc_base + RPC_SMRDR0));
  208. else
  209. *rdata = be32_to_cpu(readl(rpc_base + RPC_SMRDR0));
  210. }
  211. return rpc_hf_mode(0);
  212. }
  213. static void rpc_hf_write_cmd(void *addr, u64 wdata, enum rpc_hf_size size)
  214. {
  215. int ret;
  216. ret = rpc_hf_xfer(addr, wdata, NULL, size, 1);
  217. if (ret)
  218. printf("RPC: Write failed, ret=%i\n", ret);
  219. }
  220. static u64 rpc_hf_read_reg(void *addr, enum rpc_hf_size size)
  221. {
  222. u64 rdata = 0;
  223. int ret;
  224. ret = rpc_hf_xfer(addr, 0, &rdata, size, 0);
  225. if (ret)
  226. printf("RPC: Read failed, ret=%i\n", ret);
  227. return rdata;
  228. }
  229. void flash_write8(u8 value, void *addr)
  230. {
  231. rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT);
  232. }
  233. void flash_write16(u16 value, void *addr)
  234. {
  235. rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT);
  236. }
  237. void flash_write32(u32 value, void *addr)
  238. {
  239. rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_32BIT);
  240. }
  241. void flash_write64(u64 value, void *addr)
  242. {
  243. rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_64BIT);
  244. }
  245. u8 flash_read8(void *addr)
  246. {
  247. return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT);
  248. }
  249. u16 flash_read16(void *addr)
  250. {
  251. return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT);
  252. }
  253. u32 flash_read32(void *addr)
  254. {
  255. return rpc_hf_read_reg(addr, RPC_HF_SIZE_32BIT);
  256. }
  257. u64 flash_read64(void *addr)
  258. {
  259. return rpc_hf_read_reg(addr, RPC_HF_SIZE_64BIT);
  260. }
  261. static int rpc_hf_bind(struct udevice *parent)
  262. {
  263. const void *fdt = gd->fdt_blob;
  264. ofnode node;
  265. int ret, off;
  266. /*
  267. * Check if there are any SPI NOR child nodes, if so, do NOT bind
  268. * as this controller will be operated by the QSPI driver instead.
  269. */
  270. dev_for_each_subnode(node, parent) {
  271. off = ofnode_to_offset(node);
  272. ret = fdt_node_check_compatible(fdt, off, "spi-flash");
  273. if (!ret)
  274. return -ENODEV;
  275. ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor");
  276. if (!ret)
  277. return -ENODEV;
  278. }
  279. return 0;
  280. }
  281. static int rpc_hf_probe(struct udevice *dev)
  282. {
  283. void *blob = (void *)gd->fdt_blob;
  284. const fdt32_t *cell;
  285. int node = dev_of_offset(dev);
  286. int parent, addrc, sizec, len, ret;
  287. struct clk clk;
  288. phys_addr_t flash_base;
  289. parent = fdt_parent_offset(blob, node);
  290. fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
  291. cell = fdt_getprop(blob, node, "reg", &len);
  292. if (!cell)
  293. return -ENOENT;
  294. if (addrc != 2 || sizec != 2)
  295. return -EINVAL;
  296. ret = clk_get_by_index(dev, 0, &clk);
  297. if (ret < 0) {
  298. dev_err(dev, "Failed to get RPC clock\n");
  299. return ret;
  300. }
  301. ret = clk_enable(&clk);
  302. clk_free(&clk);
  303. if (ret) {
  304. dev_err(dev, "Failed to enable RPC clock\n");
  305. return ret;
  306. }
  307. rpc_base = fdt_translate_address(blob, node, cell);
  308. flash_base = fdt_translate_address(blob, node, cell + addrc + sizec);
  309. flash_info[0].dev = dev;
  310. flash_info[0].base = flash_base;
  311. cfi_flash_num_flash_banks = 1;
  312. gd->bd->bi_flashstart = flash_base;
  313. return 0;
  314. }
  315. static const struct udevice_id rpc_hf_ids[] = {
  316. { .compatible = "renesas,rpc" },
  317. {}
  318. };
  319. U_BOOT_DRIVER(rpc_hf) = {
  320. .name = "rpc_hf",
  321. .id = UCLASS_MTD,
  322. .of_match = rpc_hf_ids,
  323. .bind = rpc_hf_bind,
  324. .probe = rpc_hf_probe,
  325. };