tegra_i2c.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
  4. * Copyright (c) 2010-2011 NVIDIA Corporation
  5. * NVIDIA Corporation <www.nvidia.com>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <i2c.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <clk.h>
  14. #include <reset.h>
  15. #ifndef CONFIG_TEGRA186
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/funcmux.h>
  18. #endif
  19. #include <asm/arch/gpio.h>
  20. #include <asm/arch-tegra/tegra_i2c.h>
  21. #include <linux/delay.h>
  22. #include <linux/err.h>
  23. enum i2c_type {
  24. TYPE_114,
  25. TYPE_STD,
  26. TYPE_DVC,
  27. };
  28. /* Information about i2c controller */
  29. struct i2c_bus {
  30. int id;
  31. struct reset_ctl reset_ctl;
  32. struct clk clk;
  33. int speed;
  34. int pinmux_config;
  35. struct i2c_control *control;
  36. struct i2c_ctlr *regs;
  37. enum i2c_type type;
  38. int inited; /* bus is inited */
  39. };
  40. static void set_packet_mode(struct i2c_bus *i2c_bus)
  41. {
  42. u32 config;
  43. config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
  44. if (i2c_bus->type == TYPE_DVC) {
  45. struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
  46. writel(config, &dvc->cnfg);
  47. } else {
  48. writel(config, &i2c_bus->regs->cnfg);
  49. /*
  50. * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
  51. * issues, i.e., some slaves may be wrongly detected.
  52. */
  53. setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
  54. }
  55. }
  56. static void i2c_reset_controller(struct i2c_bus *i2c_bus)
  57. {
  58. /* Reset I2C controller. */
  59. reset_assert(&i2c_bus->reset_ctl);
  60. udelay(1);
  61. reset_deassert(&i2c_bus->reset_ctl);
  62. udelay(1);
  63. /* re-program config register to packet mode */
  64. set_packet_mode(i2c_bus);
  65. }
  66. static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
  67. {
  68. int ret;
  69. ret = reset_assert(&i2c_bus->reset_ctl);
  70. if (ret)
  71. return ret;
  72. ret = clk_enable(&i2c_bus->clk);
  73. if (ret)
  74. return ret;
  75. ret = clk_set_rate(&i2c_bus->clk, rate);
  76. if (IS_ERR_VALUE(ret))
  77. return ret;
  78. ret = reset_deassert(&i2c_bus->reset_ctl);
  79. if (ret)
  80. return ret;
  81. return 0;
  82. }
  83. static void i2c_init_controller(struct i2c_bus *i2c_bus)
  84. {
  85. if (!i2c_bus->speed)
  86. return;
  87. debug("%s: speed=%d\n", __func__, i2c_bus->speed);
  88. /*
  89. * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
  90. * here, in section 23.3.1, but in fact we seem to need a factor of
  91. * 16 to get the right frequency.
  92. */
  93. i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
  94. if (i2c_bus->type == TYPE_114) {
  95. /*
  96. * T114 I2C went to a single clock source for standard/fast and
  97. * HS clock speeds. The new clock rate setting calculation is:
  98. * SCL = CLK_SOURCE.I2C /
  99. * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
  100. * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
  101. *
  102. * NOTE: We do this here, after the initial clock/pll start,
  103. * because if we read the clk_div reg before the controller
  104. * is running, we hang, and we need it for the new calc.
  105. */
  106. int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
  107. unsigned rate = CLK_MULT_STD_FAST_MODE *
  108. (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
  109. debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
  110. clk_div_stdfst_mode);
  111. i2c_init_clock(i2c_bus, rate);
  112. }
  113. /* Reset I2C controller. */
  114. i2c_reset_controller(i2c_bus);
  115. /* Configure I2C controller. */
  116. if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
  117. struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
  118. setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
  119. }
  120. #ifndef CONFIG_TEGRA186
  121. funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
  122. #endif
  123. }
  124. static void send_packet_headers(
  125. struct i2c_bus *i2c_bus,
  126. struct i2c_trans_info *trans,
  127. u32 packet_id,
  128. bool end_with_repeated_start)
  129. {
  130. u32 data;
  131. /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
  132. data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
  133. data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
  134. data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
  135. writel(data, &i2c_bus->control->tx_fifo);
  136. debug("pkt header 1 sent (0x%x)\n", data);
  137. /* prepare header2 */
  138. data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
  139. writel(data, &i2c_bus->control->tx_fifo);
  140. debug("pkt header 2 sent (0x%x)\n", data);
  141. /* prepare IO specific header: configure the slave address */
  142. data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
  143. /* Enable Read if it is not a write transaction */
  144. if (!(trans->flags & I2C_IS_WRITE))
  145. data |= PKT_HDR3_READ_MODE_MASK;
  146. if (end_with_repeated_start)
  147. data |= PKT_HDR3_REPEAT_START_MASK;
  148. /* Write I2C specific header */
  149. writel(data, &i2c_bus->control->tx_fifo);
  150. debug("pkt header 3 sent (0x%x)\n", data);
  151. }
  152. static int wait_for_tx_fifo_empty(struct i2c_control *control)
  153. {
  154. u32 count;
  155. int timeout_us = I2C_TIMEOUT_USEC;
  156. while (timeout_us >= 0) {
  157. count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
  158. >> TX_FIFO_EMPTY_CNT_SHIFT;
  159. if (count == I2C_FIFO_DEPTH)
  160. return 1;
  161. udelay(10);
  162. timeout_us -= 10;
  163. }
  164. return 0;
  165. }
  166. static int wait_for_rx_fifo_notempty(struct i2c_control *control)
  167. {
  168. u32 count;
  169. int timeout_us = I2C_TIMEOUT_USEC;
  170. while (timeout_us >= 0) {
  171. count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
  172. >> TX_FIFO_FULL_CNT_SHIFT;
  173. if (count)
  174. return 1;
  175. udelay(10);
  176. timeout_us -= 10;
  177. }
  178. return 0;
  179. }
  180. static int wait_for_transfer_complete(struct i2c_control *control)
  181. {
  182. int int_status;
  183. int timeout_us = I2C_TIMEOUT_USEC;
  184. while (timeout_us >= 0) {
  185. int_status = readl(&control->int_status);
  186. if (int_status & I2C_INT_NO_ACK_MASK)
  187. return -int_status;
  188. if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
  189. return -int_status;
  190. if (int_status & I2C_INT_XFER_COMPLETE_MASK)
  191. return 0;
  192. udelay(10);
  193. timeout_us -= 10;
  194. }
  195. return -1;
  196. }
  197. static int send_recv_packets(struct i2c_bus *i2c_bus,
  198. struct i2c_trans_info *trans)
  199. {
  200. struct i2c_control *control = i2c_bus->control;
  201. u32 int_status;
  202. u32 words;
  203. u8 *dptr;
  204. u32 local;
  205. uchar last_bytes;
  206. int error = 0;
  207. int is_write = trans->flags & I2C_IS_WRITE;
  208. /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
  209. int_status = readl(&control->int_status);
  210. writel(int_status, &control->int_status);
  211. send_packet_headers(i2c_bus, trans, 1,
  212. trans->flags & I2C_USE_REPEATED_START);
  213. words = DIV_ROUND_UP(trans->num_bytes, 4);
  214. last_bytes = trans->num_bytes & 3;
  215. dptr = trans->buf;
  216. while (words) {
  217. u32 *wptr = (u32 *)dptr;
  218. if (is_write) {
  219. /* deal with word alignment */
  220. if ((words == 1) && last_bytes) {
  221. local = 0;
  222. memcpy(&local, dptr, last_bytes);
  223. } else if ((unsigned long)dptr & 3) {
  224. memcpy(&local, dptr, sizeof(u32));
  225. } else {
  226. local = *wptr;
  227. }
  228. writel(local, &control->tx_fifo);
  229. debug("pkt data sent (0x%x)\n", local);
  230. if (!wait_for_tx_fifo_empty(control)) {
  231. error = -1;
  232. goto exit;
  233. }
  234. } else {
  235. if (!wait_for_rx_fifo_notempty(control)) {
  236. error = -1;
  237. goto exit;
  238. }
  239. /*
  240. * for the last word, we read into our local buffer,
  241. * in case that caller did not provide enough buffer.
  242. */
  243. local = readl(&control->rx_fifo);
  244. if ((words == 1) && last_bytes)
  245. memcpy(dptr, (char *)&local, last_bytes);
  246. else if ((unsigned long)dptr & 3)
  247. memcpy(dptr, &local, sizeof(u32));
  248. else
  249. *wptr = local;
  250. debug("pkt data received (0x%x)\n", local);
  251. }
  252. words--;
  253. dptr += sizeof(u32);
  254. }
  255. if (wait_for_transfer_complete(control)) {
  256. error = -1;
  257. goto exit;
  258. }
  259. return 0;
  260. exit:
  261. /* error, reset the controller. */
  262. i2c_reset_controller(i2c_bus);
  263. return error;
  264. }
  265. static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
  266. u32 len, bool end_with_repeated_start)
  267. {
  268. int error;
  269. struct i2c_trans_info trans_info;
  270. trans_info.address = addr;
  271. trans_info.buf = data;
  272. trans_info.flags = I2C_IS_WRITE;
  273. if (end_with_repeated_start)
  274. trans_info.flags |= I2C_USE_REPEATED_START;
  275. trans_info.num_bytes = len;
  276. trans_info.is_10bit_address = 0;
  277. error = send_recv_packets(i2c_bus, &trans_info);
  278. if (error)
  279. debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
  280. return error;
  281. }
  282. static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
  283. u32 len)
  284. {
  285. int error;
  286. struct i2c_trans_info trans_info;
  287. trans_info.address = addr | 1;
  288. trans_info.buf = data;
  289. trans_info.flags = 0;
  290. trans_info.num_bytes = len;
  291. trans_info.is_10bit_address = 0;
  292. error = send_recv_packets(i2c_bus, &trans_info);
  293. if (error)
  294. debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
  295. return error;
  296. }
  297. static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  298. {
  299. struct i2c_bus *i2c_bus = dev_get_priv(dev);
  300. i2c_bus->speed = speed;
  301. i2c_init_controller(i2c_bus);
  302. return 0;
  303. }
  304. static int tegra_i2c_probe(struct udevice *dev)
  305. {
  306. struct i2c_bus *i2c_bus = dev_get_priv(dev);
  307. int ret;
  308. bool is_dvc;
  309. i2c_bus->id = dev_seq(dev);
  310. i2c_bus->type = dev_get_driver_data(dev);
  311. i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
  312. if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
  313. debug("%s: Cannot get regs address\n", __func__);
  314. return -EINVAL;
  315. }
  316. ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
  317. if (ret) {
  318. pr_err("reset_get_by_name() failed: %d\n", ret);
  319. return ret;
  320. }
  321. ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
  322. if (ret) {
  323. pr_err("clk_get_by_name() failed: %d\n", ret);
  324. return ret;
  325. }
  326. #ifndef CONFIG_TEGRA186
  327. /*
  328. * We don't have a binding for pinmux yet. Leave it out for now. So
  329. * far no one needs anything other than the default.
  330. */
  331. i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
  332. /*
  333. * We can't specify the pinmux config in the fdt, so I2C2 will not
  334. * work on Seaboard. It normally has no devices on it anyway.
  335. * You could add in this little hack if you need to use it.
  336. * The correct solution is a pinmux binding in the fdt.
  337. *
  338. * if (i2c_bus->clk.id == PERIPH_ID_I2C2)
  339. * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
  340. */
  341. #endif
  342. is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
  343. if (is_dvc) {
  344. i2c_bus->control =
  345. &((struct dvc_ctlr *)i2c_bus->regs)->control;
  346. } else {
  347. i2c_bus->control = &i2c_bus->regs->control;
  348. }
  349. i2c_init_controller(i2c_bus);
  350. debug("%s: controller bus %d at %p, speed %d: ",
  351. is_dvc ? "dvc" : "i2c", dev_seq(dev), i2c_bus->regs,
  352. i2c_bus->speed);
  353. return 0;
  354. }
  355. /* i2c write version without the register address */
  356. static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
  357. int len, bool end_with_repeated_start)
  358. {
  359. int rc;
  360. debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
  361. debug("write_data: ");
  362. /* use rc for counter */
  363. for (rc = 0; rc < len; ++rc)
  364. debug(" 0x%02x", buffer[rc]);
  365. debug("\n");
  366. /* Shift 7-bit address over for lower-level i2c functions */
  367. rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
  368. end_with_repeated_start);
  369. if (rc)
  370. debug("i2c_write_data(): rc=%d\n", rc);
  371. return rc;
  372. }
  373. /* i2c read version without the register address */
  374. static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
  375. int len)
  376. {
  377. int rc;
  378. debug("inside i2c_read_data():\n");
  379. /* Shift 7-bit address over for lower-level i2c functions */
  380. rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
  381. if (rc) {
  382. debug("i2c_read_data(): rc=%d\n", rc);
  383. return rc;
  384. }
  385. debug("i2c_read_data: ");
  386. /* reuse rc for counter*/
  387. for (rc = 0; rc < len; ++rc)
  388. debug(" 0x%02x", buffer[rc]);
  389. debug("\n");
  390. return 0;
  391. }
  392. /* Probe to see if a chip is present. */
  393. static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  394. uint chip_flags)
  395. {
  396. struct i2c_bus *i2c_bus = dev_get_priv(bus);
  397. int rc;
  398. u8 reg;
  399. /* Shift 7-bit address over for lower-level i2c functions */
  400. rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
  401. false);
  402. return rc;
  403. }
  404. static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  405. int nmsgs)
  406. {
  407. struct i2c_bus *i2c_bus = dev_get_priv(bus);
  408. int ret;
  409. debug("i2c_xfer: %d messages\n", nmsgs);
  410. for (; nmsgs > 0; nmsgs--, msg++) {
  411. bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
  412. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  413. if (msg->flags & I2C_M_RD) {
  414. ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
  415. msg->len);
  416. } else {
  417. ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
  418. msg->len, next_is_read);
  419. }
  420. if (ret) {
  421. debug("i2c_write: error sending\n");
  422. return -EREMOTEIO;
  423. }
  424. }
  425. return 0;
  426. }
  427. int tegra_i2c_get_dvc_bus(struct udevice **busp)
  428. {
  429. return uclass_first_device_drvdata(UCLASS_I2C, TYPE_DVC, busp);
  430. }
  431. static const struct dm_i2c_ops tegra_i2c_ops = {
  432. .xfer = tegra_i2c_xfer,
  433. .probe_chip = tegra_i2c_probe_chip,
  434. .set_bus_speed = tegra_i2c_set_bus_speed,
  435. };
  436. static const struct udevice_id tegra_i2c_ids[] = {
  437. { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
  438. { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
  439. { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
  440. { }
  441. };
  442. U_BOOT_DRIVER(i2c_tegra) = {
  443. .name = "i2c_tegra",
  444. .id = UCLASS_I2C,
  445. .of_match = tegra_i2c_ids,
  446. .probe = tegra_i2c_probe,
  447. .priv_auto = sizeof(struct i2c_bus),
  448. .ops = &tegra_i2c_ops,
  449. };