s3c24x0_i2c.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  11. #include <log.h>
  12. #include <asm/arch/clk.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/pinmux.h>
  15. #else
  16. #include <asm/arch/s3c24x0_cpu.h>
  17. #endif
  18. #include <asm/io.h>
  19. #include <i2c.h>
  20. #include "s3c24x0_i2c.h"
  21. #ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
  22. #define SYS_I2C_S3C24X0_SLAVE_ADDR 0
  23. #else
  24. #define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
  25. #endif
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /*
  28. * Wait til the byte transfer is completed.
  29. *
  30. * @param i2c- pointer to the appropriate i2c register bank.
  31. * @return I2C_OK, if transmission was ACKED
  32. * I2C_NACK, if transmission was NACKED
  33. * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
  34. */
  35. static int WaitForXfer(struct s3c24x0_i2c *i2c)
  36. {
  37. ulong start_time = get_timer(0);
  38. do {
  39. if (readl(&i2c->iiccon) & I2CCON_IRPND)
  40. return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
  41. I2C_NACK : I2C_OK;
  42. } while (get_timer(start_time) < I2C_TIMEOUT_MS);
  43. return I2C_NOK_TOUT;
  44. }
  45. static void read_write_byte(struct s3c24x0_i2c *i2c)
  46. {
  47. clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
  48. }
  49. static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
  50. {
  51. ulong freq, pres = 16, div;
  52. #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  53. freq = get_i2c_clk();
  54. #else
  55. freq = get_PCLK();
  56. #endif
  57. /* calculate prescaler and divisor values */
  58. if ((freq / pres / (16 + 1)) > speed)
  59. /* set prescaler to 512 */
  60. pres = 512;
  61. div = 0;
  62. while ((freq / pres / (div + 1)) > speed)
  63. div++;
  64. /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
  65. writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
  66. /* init to SLAVE REVEIVE and set slaveaddr */
  67. writel(0, &i2c->iicstat);
  68. writel(slaveadd, &i2c->iicadd);
  69. /* program Master Transmit (and implicit STOP) */
  70. writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
  71. }
  72. static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  73. {
  74. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  75. i2c_bus->clock_frequency = speed;
  76. i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
  77. SYS_I2C_S3C24X0_SLAVE_ADDR);
  78. return 0;
  79. }
  80. /*
  81. * cmd_type is 0 for write, 1 for read.
  82. *
  83. * addr_len can take any value from 0-255, it is only limited
  84. * by the char, we could make it larger if needed. If it is
  85. * 0 we skip the address write cycle.
  86. */
  87. static int i2c_transfer(struct s3c24x0_i2c *i2c,
  88. unsigned char cmd_type,
  89. unsigned char chip,
  90. unsigned char addr[],
  91. unsigned char addr_len,
  92. unsigned char data[],
  93. unsigned short data_len)
  94. {
  95. int i = 0, result;
  96. ulong start_time = get_timer(0);
  97. if (data == 0 || data_len == 0) {
  98. /*Don't support data transfer of no length or to address 0 */
  99. debug("i2c_transfer: bad call\n");
  100. return I2C_NOK;
  101. }
  102. while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
  103. if (get_timer(start_time) > I2C_TIMEOUT_MS)
  104. return I2C_NOK_TOUT;
  105. }
  106. writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
  107. /* Get the slave chip address going */
  108. writel(chip, &i2c->iicds);
  109. if ((cmd_type == I2C_WRITE) || (addr && addr_len))
  110. writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
  111. &i2c->iicstat);
  112. else
  113. writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
  114. &i2c->iicstat);
  115. /* Wait for chip address to transmit. */
  116. result = WaitForXfer(i2c);
  117. if (result != I2C_OK)
  118. goto bailout;
  119. /* If register address needs to be transmitted - do it now. */
  120. if (addr && addr_len) {
  121. while ((i < addr_len) && (result == I2C_OK)) {
  122. writel(addr[i++], &i2c->iicds);
  123. read_write_byte(i2c);
  124. result = WaitForXfer(i2c);
  125. }
  126. i = 0;
  127. if (result != I2C_OK)
  128. goto bailout;
  129. }
  130. switch (cmd_type) {
  131. case I2C_WRITE:
  132. while ((i < data_len) && (result == I2C_OK)) {
  133. writel(data[i++], &i2c->iicds);
  134. read_write_byte(i2c);
  135. result = WaitForXfer(i2c);
  136. }
  137. break;
  138. case I2C_READ:
  139. if (addr && addr_len) {
  140. /*
  141. * Register address has been sent, now send slave chip
  142. * address again to start the actual read transaction.
  143. */
  144. writel(chip, &i2c->iicds);
  145. /* Generate a re-START. */
  146. writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
  147. &i2c->iicstat);
  148. read_write_byte(i2c);
  149. result = WaitForXfer(i2c);
  150. if (result != I2C_OK)
  151. goto bailout;
  152. }
  153. while ((i < data_len) && (result == I2C_OK)) {
  154. /* disable ACK for final READ */
  155. if (i == data_len - 1)
  156. writel(readl(&i2c->iiccon)
  157. & ~I2CCON_ACKGEN,
  158. &i2c->iiccon);
  159. read_write_byte(i2c);
  160. result = WaitForXfer(i2c);
  161. data[i++] = readl(&i2c->iicds);
  162. }
  163. if (result == I2C_NACK)
  164. result = I2C_OK; /* Normal terminated read. */
  165. break;
  166. default:
  167. debug("i2c_transfer: bad call\n");
  168. result = I2C_NOK;
  169. break;
  170. }
  171. bailout:
  172. /* Send STOP. */
  173. writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
  174. read_write_byte(i2c);
  175. return result;
  176. }
  177. static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
  178. {
  179. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  180. uchar buf[1];
  181. int ret;
  182. buf[0] = 0;
  183. /*
  184. * What is needed is to send the chip address and verify that the
  185. * address was <ACK>ed (i.e. there was a chip at that address which
  186. * drove the data line low).
  187. */
  188. ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
  189. return ret != I2C_OK;
  190. }
  191. static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
  192. int seq)
  193. {
  194. struct s3c24x0_i2c *i2c = i2c_bus->regs;
  195. bool is_read = msg->flags & I2C_M_RD;
  196. uint status;
  197. uint addr;
  198. int ret, i;
  199. if (!seq)
  200. setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
  201. /* Get the slave chip address going */
  202. addr = msg->addr << 1;
  203. writel(addr, &i2c->iicds);
  204. status = I2C_TXRX_ENA | I2C_START_STOP;
  205. if (is_read)
  206. status |= I2C_MODE_MR;
  207. else
  208. status |= I2C_MODE_MT;
  209. writel(status, &i2c->iicstat);
  210. if (seq)
  211. read_write_byte(i2c);
  212. /* Wait for chip address to transmit */
  213. ret = WaitForXfer(i2c);
  214. if (ret)
  215. goto err;
  216. if (is_read) {
  217. for (i = 0; !ret && i < msg->len; i++) {
  218. /* disable ACK for final READ */
  219. if (i == msg->len - 1)
  220. clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
  221. read_write_byte(i2c);
  222. ret = WaitForXfer(i2c);
  223. msg->buf[i] = readl(&i2c->iicds);
  224. }
  225. if (ret == I2C_NACK)
  226. ret = I2C_OK; /* Normal terminated read */
  227. } else {
  228. for (i = 0; !ret && i < msg->len; i++) {
  229. writel(msg->buf[i], &i2c->iicds);
  230. read_write_byte(i2c);
  231. ret = WaitForXfer(i2c);
  232. }
  233. }
  234. err:
  235. return ret;
  236. }
  237. static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
  238. int nmsgs)
  239. {
  240. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  241. struct s3c24x0_i2c *i2c = i2c_bus->regs;
  242. ulong start_time;
  243. int ret, i;
  244. start_time = get_timer(0);
  245. while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
  246. if (get_timer(start_time) > I2C_TIMEOUT_MS) {
  247. debug("Timeout\n");
  248. return -ETIMEDOUT;
  249. }
  250. }
  251. for (ret = 0, i = 0; !ret && i < nmsgs; i++)
  252. ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
  253. /* Send STOP */
  254. writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
  255. read_write_byte(i2c);
  256. return ret ? -EREMOTEIO : 0;
  257. }
  258. static int s3c_i2c_of_to_plat(struct udevice *dev)
  259. {
  260. const void *blob = gd->fdt_blob;
  261. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  262. int node;
  263. node = dev_of_offset(dev);
  264. i2c_bus->regs = dev_read_addr_ptr(dev);
  265. i2c_bus->id = pinmux_decode_periph_id(blob, node);
  266. i2c_bus->clock_frequency =
  267. dev_read_u32_default(dev, "clock-frequency",
  268. I2C_SPEED_STANDARD_RATE);
  269. i2c_bus->node = node;
  270. i2c_bus->bus_num = dev_seq(dev);
  271. exynos_pinmux_config(i2c_bus->id, 0);
  272. i2c_bus->active = true;
  273. return 0;
  274. }
  275. static const struct dm_i2c_ops s3c_i2c_ops = {
  276. .xfer = s3c24x0_i2c_xfer,
  277. .probe_chip = s3c24x0_i2c_probe,
  278. .set_bus_speed = s3c24x0_i2c_set_bus_speed,
  279. };
  280. static const struct udevice_id s3c_i2c_ids[] = {
  281. { .compatible = "samsung,s3c2440-i2c" },
  282. { }
  283. };
  284. U_BOOT_DRIVER(i2c_s3c) = {
  285. .name = "i2c_s3c",
  286. .id = UCLASS_I2C,
  287. .of_match = s3c_i2c_ids,
  288. .of_to_plat = s3c_i2c_of_to_plat,
  289. .priv_auto = sizeof(struct s3c24x0_i2c_bus),
  290. .ops = &s3c_i2c_ops,
  291. };