octeon_i2c.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Marvell International Ltd.
  4. */
  5. #include <clk.h>
  6. #include <dm.h>
  7. #include <i2c.h>
  8. #include <time.h>
  9. #include <asm/io.h>
  10. #include <linux/bitfield.h>
  11. #include <linux/compat.h>
  12. #include <linux/delay.h>
  13. #define TWSI_SW_TWSI 0x00
  14. #define TWSI_TWSI_SW 0x08
  15. #define TWSI_INT 0x10
  16. #define TWSI_SW_TWSI_EXT 0x18
  17. #define TWSI_SW_DATA_MASK GENMASK_ULL(31, 0)
  18. #define TWSI_SW_EOP_IA_MASK GENMASK_ULL(34, 32)
  19. #define TWSI_SW_IA_MASK GENMASK_ULL(39, 35)
  20. #define TWSI_SW_ADDR_MASK GENMASK_ULL(49, 40)
  21. #define TWSI_SW_SCR_MASK GENMASK_ULL(51, 50)
  22. #define TWSI_SW_SIZE_MASK GENMASK_ULL(54, 52)
  23. #define TWSI_SW_SOVR BIT_ULL(55)
  24. #define TWSI_SW_R BIT_ULL(56)
  25. #define TWSI_SW_OP_MASK GENMASK_ULL(60, 57)
  26. #define TWSI_SW_EIA GENMASK_ULL(61)
  27. #define TWSI_SW_SLONLY BIT_ULL(62)
  28. #define TWSI_SW_V BIT_ULL(63)
  29. #define TWSI_INT_SDA_OVR BIT_ULL(8)
  30. #define TWSI_INT_SCL_OVR BIT_ULL(9)
  31. #define TWSI_INT_SDA BIT_ULL(10)
  32. #define TWSI_INT_SCL BIT_ULL(11)
  33. enum {
  34. TWSI_OP_WRITE = 0,
  35. TWSI_OP_READ = 1,
  36. };
  37. enum {
  38. TWSI_EOP_SLAVE_ADDR = 0,
  39. TWSI_EOP_CLK_CTL = 3,
  40. TWSI_SW_EOP_IA = 6,
  41. };
  42. enum {
  43. TWSI_SLAVEADD = 0,
  44. TWSI_DATA = 1,
  45. TWSI_CTL = 2,
  46. TWSI_CLKCTL = 3,
  47. TWSI_STAT = 3,
  48. TWSI_SLAVEADD_EXT = 4,
  49. TWSI_RST = 7,
  50. };
  51. enum {
  52. TWSI_CTL_AAK = BIT(2),
  53. TWSI_CTL_IFLG = BIT(3),
  54. TWSI_CTL_STP = BIT(4),
  55. TWSI_CTL_STA = BIT(5),
  56. TWSI_CTL_ENAB = BIT(6),
  57. TWSI_CTL_CE = BIT(7),
  58. };
  59. /*
  60. * Internal errors. When debugging is enabled, the driver will report the
  61. * error number and the user / developer can check the table below for the
  62. * detailed error description.
  63. */
  64. enum {
  65. /** Bus error */
  66. TWSI_STAT_BUS_ERROR = 0x00,
  67. /** Start condition transmitted */
  68. TWSI_STAT_START = 0x08,
  69. /** Repeat start condition transmitted */
  70. TWSI_STAT_RSTART = 0x10,
  71. /** Address + write bit transmitted, ACK received */
  72. TWSI_STAT_TXADDR_ACK = 0x18,
  73. /** Address + write bit transmitted, /ACK received */
  74. TWSI_STAT_TXADDR_NAK = 0x20,
  75. /** Data byte transmitted in master mode, ACK received */
  76. TWSI_STAT_TXDATA_ACK = 0x28,
  77. /** Data byte transmitted in master mode, ACK received */
  78. TWSI_STAT_TXDATA_NAK = 0x30,
  79. /** Arbitration lost in address or data byte */
  80. TWSI_STAT_TX_ARB_LOST = 0x38,
  81. /** Address + read bit transmitted, ACK received */
  82. TWSI_STAT_RXADDR_ACK = 0x40,
  83. /** Address + read bit transmitted, /ACK received */
  84. TWSI_STAT_RXADDR_NAK = 0x48,
  85. /** Data byte received in master mode, ACK transmitted */
  86. TWSI_STAT_RXDATA_ACK_SENT = 0x50,
  87. /** Data byte received, NACK transmitted */
  88. TWSI_STAT_RXDATA_NAK_SENT = 0x58,
  89. /** Slave address received, sent ACK */
  90. TWSI_STAT_SLAVE_RXADDR_ACK = 0x60,
  91. /**
  92. * Arbitration lost in address as master, slave address + write bit
  93. * received, ACK transmitted
  94. */
  95. TWSI_STAT_TX_ACK_ARB_LOST = 0x68,
  96. /** General call address received, ACK transmitted */
  97. TWSI_STAT_RX_GEN_ADDR_ACK = 0x70,
  98. /**
  99. * Arbitration lost in address as master, general call address
  100. * received, ACK transmitted
  101. */
  102. TWSI_STAT_RX_GEN_ADDR_ARB_LOST = 0x78,
  103. /** Data byte received after slave address received, ACK transmitted */
  104. TWSI_STAT_SLAVE_RXDATA_ACK = 0x80,
  105. /** Data byte received after slave address received, /ACK transmitted */
  106. TWSI_STAT_SLAVE_RXDATA_NAK = 0x88,
  107. /**
  108. * Data byte received after general call address received, ACK
  109. * transmitted
  110. */
  111. TWSI_STAT_GEN_RXADDR_ACK = 0x90,
  112. /**
  113. * Data byte received after general call address received, /ACK
  114. * transmitted
  115. */
  116. TWSI_STAT_GEN_RXADDR_NAK = 0x98,
  117. /** STOP or repeated START condition received in slave mode */
  118. TWSI_STAT_STOP_MULTI_START = 0xa0,
  119. /** Slave address + read bit received, ACK transmitted */
  120. TWSI_STAT_SLAVE_RXADDR2_ACK = 0xa8,
  121. /**
  122. * Arbitration lost in address as master, slave address + read bit
  123. * received, ACK transmitted
  124. */
  125. TWSI_STAT_RXDATA_ACK_ARB_LOST = 0xb0,
  126. /** Data byte transmitted in slave mode, ACK received */
  127. TWSI_STAT_SLAVE_TXDATA_ACK = 0xb8,
  128. /** Data byte transmitted in slave mode, /ACK received */
  129. TWSI_STAT_SLAVE_TXDATA_NAK = 0xc0,
  130. /** Last byte transmitted in slave mode, ACK received */
  131. TWSI_STAT_SLAVE_TXDATA_END_ACK = 0xc8,
  132. /** Second address byte + write bit transmitted, ACK received */
  133. TWSI_STAT_TXADDR2DATA_ACK = 0xd0,
  134. /** Second address byte + write bit transmitted, /ACK received */
  135. TWSI_STAT_TXADDR2DATA_NAK = 0xd8,
  136. /** No relevant status information */
  137. TWSI_STAT_IDLE = 0xf8
  138. };
  139. #define CONFIG_SYS_I2C_OCTEON_SLAVE_ADDR 0x77
  140. enum {
  141. PROBE_PCI = 0, /* PCI based probing */
  142. PROBE_DT, /* DT based probing */
  143. };
  144. enum {
  145. CLK_METHOD_OCTEON = 0,
  146. CLK_METHOD_OCTEONTX2,
  147. };
  148. /**
  149. * struct octeon_i2c_data - SoC specific data of this driver
  150. *
  151. * @probe: Probing of this SoC (DT vs PCI)
  152. * @reg_offs: Register offset
  153. * @thp: THP define for divider calculation
  154. * @clk_method: Clock calculation method
  155. */
  156. struct octeon_i2c_data {
  157. int probe;
  158. u32 reg_offs;
  159. int thp;
  160. int clk_method;
  161. };
  162. /**
  163. * struct octeon_twsi - Private data of this driver
  164. *
  165. * @base: Base address of i2c registers
  166. * @data: Pointer to SoC specific data struct
  167. */
  168. struct octeon_twsi {
  169. void __iomem *base;
  170. const struct octeon_i2c_data *data;
  171. struct clk clk;
  172. };
  173. static void twsi_unblock(void *base);
  174. static int twsi_stop(void *base);
  175. /**
  176. * Returns true if we lost arbitration
  177. *
  178. * @code status code
  179. * @final_read true if this is the final read operation
  180. * @return true if arbitration has been lost, false if it hasn't been lost.
  181. */
  182. static int twsi_i2c_lost_arb(u8 code, int final_read)
  183. {
  184. switch (code) {
  185. case TWSI_STAT_TX_ARB_LOST:
  186. case TWSI_STAT_TX_ACK_ARB_LOST:
  187. case TWSI_STAT_RX_GEN_ADDR_ARB_LOST:
  188. case TWSI_STAT_RXDATA_ACK_ARB_LOST:
  189. /* Arbitration lost */
  190. return -EAGAIN;
  191. case TWSI_STAT_SLAVE_RXADDR_ACK:
  192. case TWSI_STAT_RX_GEN_ADDR_ACK:
  193. case TWSI_STAT_GEN_RXADDR_ACK:
  194. case TWSI_STAT_GEN_RXADDR_NAK:
  195. /* Being addressed as slave, should back off and listen */
  196. return -EIO;
  197. case TWSI_STAT_SLAVE_RXDATA_ACK:
  198. case TWSI_STAT_SLAVE_RXDATA_NAK:
  199. case TWSI_STAT_STOP_MULTI_START:
  200. case TWSI_STAT_SLAVE_RXADDR2_ACK:
  201. case TWSI_STAT_SLAVE_TXDATA_ACK:
  202. case TWSI_STAT_SLAVE_TXDATA_NAK:
  203. case TWSI_STAT_SLAVE_TXDATA_END_ACK:
  204. /* Core busy as slave */
  205. return -EIO;
  206. case TWSI_STAT_RXDATA_ACK_SENT:
  207. /* Ack allowed on pre-terminal bytes only */
  208. if (!final_read)
  209. return 0;
  210. return -EAGAIN;
  211. case TWSI_STAT_RXDATA_NAK_SENT:
  212. /* NAK allowed on terminal byte only */
  213. if (!final_read)
  214. return 0;
  215. return -EAGAIN;
  216. case TWSI_STAT_TXDATA_NAK:
  217. case TWSI_STAT_TXADDR_NAK:
  218. case TWSI_STAT_RXADDR_NAK:
  219. case TWSI_STAT_TXADDR2DATA_NAK:
  220. return -EAGAIN;
  221. }
  222. return 0;
  223. }
  224. /**
  225. * Writes to the MIO_TWS(0..5)_SW_TWSI register
  226. *
  227. * @base Base address of i2c registers
  228. * @val value to write
  229. * @return 0 for success, otherwise error
  230. */
  231. static u64 twsi_write_sw(void __iomem *base, u64 val)
  232. {
  233. unsigned long start = get_timer(0);
  234. val &= ~TWSI_SW_R;
  235. val |= TWSI_SW_V;
  236. debug("%s(%p, 0x%llx)\n", __func__, base, val);
  237. writeq(val, base + TWSI_SW_TWSI);
  238. do {
  239. val = readq(base + TWSI_SW_TWSI);
  240. } while ((val & TWSI_SW_V) && (get_timer(start) < 50));
  241. if (val & TWSI_SW_V)
  242. debug("%s: timed out\n", __func__);
  243. return val;
  244. }
  245. /**
  246. * Reads the MIO_TWS(0..5)_SW_TWSI register
  247. *
  248. * @base Base address of i2c registers
  249. * @val value for eia and op, etc. to read
  250. * @return value of the register
  251. */
  252. static u64 twsi_read_sw(void __iomem *base, u64 val)
  253. {
  254. unsigned long start = get_timer(0);
  255. val |= TWSI_SW_R | TWSI_SW_V;
  256. debug("%s(%p, 0x%llx)\n", __func__, base, val);
  257. writeq(val, base + TWSI_SW_TWSI);
  258. do {
  259. val = readq(base + TWSI_SW_TWSI);
  260. } while ((val & TWSI_SW_V) && (get_timer(start) < 50));
  261. if (val & TWSI_SW_V)
  262. debug("%s: Error writing 0x%llx\n", __func__, val);
  263. debug("%s: Returning 0x%llx\n", __func__, val);
  264. return val;
  265. }
  266. /**
  267. * Write control register
  268. *
  269. * @base Base address for i2c registers
  270. * @data data to write
  271. */
  272. static void twsi_write_ctl(void __iomem *base, u8 data)
  273. {
  274. u64 val;
  275. debug("%s(%p, 0x%x)\n", __func__, base, data);
  276. val = data | FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_CTL) |
  277. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  278. twsi_write_sw(base, val);
  279. }
  280. /**
  281. * Reads the TWSI Control Register
  282. *
  283. * @base Base address for i2c
  284. * @return 8-bit TWSI control register
  285. */
  286. static u8 twsi_read_ctl(void __iomem *base)
  287. {
  288. u64 val;
  289. val = FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_CTL) |
  290. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  291. val = twsi_read_sw(base, val);
  292. debug("%s(%p): 0x%x\n", __func__, base, (u8)val);
  293. return (u8)val;
  294. }
  295. /**
  296. * Read i2c status register
  297. *
  298. * @base Base address of i2c registers
  299. * @return value of status register
  300. */
  301. static u8 twsi_read_status(void __iomem *base)
  302. {
  303. u64 val;
  304. val = FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_STAT) |
  305. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  306. return twsi_read_sw(base, val);
  307. }
  308. /**
  309. * Waits for an i2c operation to complete
  310. *
  311. * @param base Base address of registers
  312. * @return 0 for success, 1 if timeout
  313. */
  314. static int twsi_wait(void __iomem *base)
  315. {
  316. unsigned long start = get_timer(0);
  317. u8 twsi_ctl;
  318. debug("%s(%p)\n", __func__, base);
  319. do {
  320. twsi_ctl = twsi_read_ctl(base);
  321. twsi_ctl &= TWSI_CTL_IFLG;
  322. } while (!twsi_ctl && get_timer(start) < 50);
  323. debug(" return: %u\n", !twsi_ctl);
  324. return !twsi_ctl;
  325. }
  326. /**
  327. * Unsticks the i2c bus
  328. *
  329. * @base base address of registers
  330. */
  331. static int twsi_start_unstick(void __iomem *base)
  332. {
  333. twsi_stop(base);
  334. twsi_unblock(base);
  335. return 0;
  336. }
  337. /**
  338. * Sends an i2c start condition
  339. *
  340. * @base base address of registers
  341. * @return 0 for success, otherwise error
  342. */
  343. static int twsi_start(void __iomem *base)
  344. {
  345. int ret;
  346. u8 stat;
  347. debug("%s(%p)\n", __func__, base);
  348. twsi_write_ctl(base, TWSI_CTL_STA | TWSI_CTL_ENAB);
  349. ret = twsi_wait(base);
  350. if (ret) {
  351. stat = twsi_read_status(base);
  352. debug("%s: ret: 0x%x, status: 0x%x\n", __func__, ret, stat);
  353. switch (stat) {
  354. case TWSI_STAT_START:
  355. case TWSI_STAT_RSTART:
  356. return 0;
  357. case TWSI_STAT_RXADDR_ACK:
  358. default:
  359. return twsi_start_unstick(base);
  360. }
  361. }
  362. debug("%s: success\n", __func__);
  363. return 0;
  364. }
  365. /**
  366. * Sends an i2c stop condition
  367. *
  368. * @base register base address
  369. * @return 0 for success, -1 if error
  370. */
  371. static int twsi_stop(void __iomem *base)
  372. {
  373. u8 stat;
  374. twsi_write_ctl(base, TWSI_CTL_STP | TWSI_CTL_ENAB);
  375. stat = twsi_read_status(base);
  376. if (stat != TWSI_STAT_IDLE) {
  377. debug("%s: Bad status on bus@%p\n", __func__, base);
  378. return -1;
  379. }
  380. return 0;
  381. }
  382. /**
  383. * Writes data to the i2c bus
  384. *
  385. * @base register base address
  386. * @slave_addr address of slave to write to
  387. * @buffer Pointer to buffer to write
  388. * @length Number of bytes in buffer to write
  389. * @return 0 for success, otherwise error
  390. */
  391. static int twsi_write_data(void __iomem *base, u8 slave_addr,
  392. u8 *buffer, unsigned int length)
  393. {
  394. unsigned int curr = 0;
  395. u64 val;
  396. int ret;
  397. debug("%s(%p, 0x%x, %p, 0x%x)\n", __func__, base, slave_addr,
  398. buffer, length);
  399. ret = twsi_start(base);
  400. if (ret) {
  401. debug("%s: Could not start BUS transaction\n", __func__);
  402. return -1;
  403. }
  404. ret = twsi_wait(base);
  405. if (ret) {
  406. debug("%s: wait failed\n", __func__);
  407. return ret;
  408. }
  409. val = (u32)(slave_addr << 1) | TWSI_OP_WRITE |
  410. FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) |
  411. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  412. twsi_write_sw(base, val);
  413. twsi_write_ctl(base, TWSI_CTL_ENAB);
  414. debug("%s: Waiting\n", __func__);
  415. ret = twsi_wait(base);
  416. if (ret) {
  417. debug("%s: Timed out writing slave address 0x%x to target\n",
  418. __func__, slave_addr);
  419. return ret;
  420. }
  421. ret = twsi_read_status(base);
  422. debug("%s: status: 0x%x\n", __func__, ret);
  423. if (ret != TWSI_STAT_TXADDR_ACK) {
  424. debug("%s: status: 0x%x\n", __func__, ret);
  425. twsi_stop(base);
  426. return twsi_i2c_lost_arb(ret, 0);
  427. }
  428. while (curr < length) {
  429. val = buffer[curr++] |
  430. FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) |
  431. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  432. twsi_write_sw(base, val);
  433. twsi_write_ctl(base, TWSI_CTL_ENAB);
  434. debug("%s: Writing 0x%llx\n", __func__, val);
  435. ret = twsi_wait(base);
  436. if (ret) {
  437. debug("%s: Timed out writing data to 0x%x\n",
  438. __func__, slave_addr);
  439. return ret;
  440. }
  441. ret = twsi_read_status(base);
  442. debug("%s: status: 0x%x\n", __func__, ret);
  443. }
  444. debug("%s: Stopping\n", __func__);
  445. return twsi_stop(base);
  446. }
  447. /**
  448. * Manually clear the I2C bus and send a stop
  449. *
  450. * @base register base address
  451. */
  452. static void twsi_unblock(void __iomem *base)
  453. {
  454. int i;
  455. for (i = 0; i < 9; i++) {
  456. writeq(0, base + TWSI_INT);
  457. udelay(5);
  458. writeq(TWSI_INT_SCL_OVR, base + TWSI_INT);
  459. udelay(5);
  460. }
  461. writeq(TWSI_INT_SCL_OVR | TWSI_INT_SDA_OVR, base + TWSI_INT);
  462. udelay(5);
  463. writeq(TWSI_INT_SDA_OVR, base + TWSI_INT);
  464. udelay(5);
  465. writeq(0, base + TWSI_INT);
  466. udelay(5);
  467. }
  468. /**
  469. * Performs a read transaction on the i2c bus
  470. *
  471. * @base Base address of twsi registers
  472. * @slave_addr i2c bus address to read from
  473. * @buffer buffer to read into
  474. * @length number of bytes to read
  475. * @return 0 for success, otherwise error
  476. */
  477. static int twsi_read_data(void __iomem *base, u8 slave_addr,
  478. u8 *buffer, unsigned int length)
  479. {
  480. unsigned int curr = 0;
  481. u64 val;
  482. int ret;
  483. debug("%s(%p, 0x%x, %p, %u)\n", __func__, base, slave_addr,
  484. buffer, length);
  485. ret = twsi_start(base);
  486. if (ret) {
  487. debug("%s: start failed\n", __func__);
  488. return ret;
  489. }
  490. ret = twsi_wait(base);
  491. if (ret) {
  492. debug("%s: wait failed\n", __func__);
  493. return ret;
  494. }
  495. val = (u32)(slave_addr << 1) | TWSI_OP_READ |
  496. FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) |
  497. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA);
  498. twsi_write_sw(base, val);
  499. twsi_write_ctl(base, TWSI_CTL_ENAB);
  500. ret = twsi_wait(base);
  501. if (ret) {
  502. debug("%s: waiting for sending addr failed\n", __func__);
  503. return ret;
  504. }
  505. ret = twsi_read_status(base);
  506. debug("%s: status: 0x%x\n", __func__, ret);
  507. if (ret != TWSI_STAT_RXADDR_ACK) {
  508. debug("%s: status: 0x%x\n", __func__, ret);
  509. twsi_stop(base);
  510. return twsi_i2c_lost_arb(ret, 0);
  511. }
  512. while (curr < length) {
  513. twsi_write_ctl(base, TWSI_CTL_ENAB |
  514. ((curr < length - 1) ? TWSI_CTL_AAK : 0));
  515. ret = twsi_wait(base);
  516. if (ret) {
  517. debug("%s: waiting for data failed\n", __func__);
  518. return ret;
  519. }
  520. val = twsi_read_sw(base, val);
  521. buffer[curr++] = (u8)val;
  522. }
  523. twsi_stop(base);
  524. return 0;
  525. }
  526. /**
  527. * Calculate the divisor values
  528. *
  529. * @speed Speed to set
  530. * @m_div Pointer to M divisor
  531. * @n_div Pointer to N divisor
  532. * @return 0 for success, otherwise error
  533. */
  534. static void twsi_calc_div(struct udevice *bus, ulong sclk, unsigned int speed,
  535. int *m_div, int *n_div)
  536. {
  537. struct octeon_twsi *twsi = dev_get_priv(bus);
  538. int thp = twsi->data->thp;
  539. int tclk, fsamp;
  540. int ndiv, mdiv;
  541. if (twsi->data->clk_method == CLK_METHOD_OCTEON) {
  542. tclk = sclk / (2 * (thp + 1));
  543. } else {
  544. /* Refclk src in mode register defaults to 100MHz clock */
  545. sclk = 100000000; /* 100 Mhz */
  546. tclk = sclk / (thp + 2);
  547. }
  548. debug("%s( io_clock %lu tclk %u)\n", __func__, sclk, tclk);
  549. /*
  550. * Compute the clocks M divider:
  551. *
  552. * TWSI freq = (core freq) / (10 x (M+1) x 2 * (thp+1) x 2^N)
  553. * M = ((core freq) / (10 x (TWSI freq) x 2 * (thp+1) x 2^N)) - 1
  554. *
  555. * For OcteonTX2 -
  556. * TWSI freq = (core freq) / (10 x (M+1) x (thp+2) x 2^N)
  557. * M = ((core freq) / (10 x (TWSI freq) x (thp+2) x 2^N)) - 1
  558. */
  559. for (ndiv = 0; ndiv < 8; ndiv++) {
  560. fsamp = tclk / (1 << ndiv);
  561. mdiv = fsamp / speed / 10;
  562. mdiv -= 1;
  563. if (mdiv < 16)
  564. break;
  565. }
  566. *m_div = mdiv;
  567. *n_div = ndiv;
  568. }
  569. /**
  570. * Init I2C controller
  571. *
  572. * @base Base address of twsi registers
  573. * @slave_addr I2C slave address to configure this controller to
  574. * @return 0 for success, otherwise error
  575. */
  576. static int twsi_init(void __iomem *base, int slaveaddr)
  577. {
  578. u64 val;
  579. debug("%s (%p, 0x%x)\n", __func__, base, slaveaddr);
  580. val = slaveaddr << 1 |
  581. FIELD_PREP(TWSI_SW_EOP_IA_MASK, 0) |
  582. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA) |
  583. TWSI_SW_V;
  584. twsi_write_sw(base, val);
  585. /* Set slave address */
  586. val = slaveaddr |
  587. FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_EOP_SLAVE_ADDR) |
  588. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA) |
  589. TWSI_SW_V;
  590. twsi_write_sw(base, val);
  591. return 0;
  592. }
  593. /**
  594. * Transfers data over the i2c bus
  595. *
  596. * @bus i2c bus to transfer data over
  597. * @msg Array of i2c messages
  598. * @nmsgs Number of messages to send/receive
  599. * @return 0 for success, otherwise error
  600. */
  601. static int octeon_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  602. int nmsgs)
  603. {
  604. struct octeon_twsi *twsi = dev_get_priv(bus);
  605. int ret;
  606. int i;
  607. debug("%s: %d messages\n", __func__, nmsgs);
  608. for (i = 0; i < nmsgs; i++, msg++) {
  609. debug("%s: chip=0x%x, len=0x%x\n", __func__, msg->addr,
  610. msg->len);
  611. if (msg->flags & I2C_M_RD) {
  612. debug("%s: Reading data\n", __func__);
  613. ret = twsi_read_data(twsi->base, msg->addr,
  614. msg->buf, msg->len);
  615. } else {
  616. debug("%s: Writing data\n", __func__);
  617. ret = twsi_write_data(twsi->base, msg->addr,
  618. msg->buf, msg->len);
  619. }
  620. if (ret) {
  621. debug("%s: error sending\n", __func__);
  622. return -EREMOTEIO;
  623. }
  624. }
  625. return 0;
  626. }
  627. /**
  628. * Set I2C bus speed
  629. *
  630. * @bus i2c bus to transfer data over
  631. * @speed Speed in Hz to set
  632. * @return 0 for success, otherwise error
  633. */
  634. static int octeon_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  635. {
  636. struct octeon_twsi *twsi = dev_get_priv(bus);
  637. int m_div, n_div;
  638. ulong clk_rate;
  639. u64 val;
  640. debug("%s(%p, %u)\n", __func__, bus, speed);
  641. clk_rate = clk_get_rate(&twsi->clk);
  642. if (IS_ERR_VALUE(clk_rate))
  643. return -EINVAL;
  644. twsi_calc_div(bus, clk_rate, speed, &m_div, &n_div);
  645. if (m_div >= 16)
  646. return -1;
  647. val = (u32)(((m_div & 0xf) << 3) | ((n_div & 0x7) << 0)) |
  648. FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_CLKCTL) |
  649. FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA) |
  650. TWSI_SW_V;
  651. /* Only init non-slave ports */
  652. writeq(val, twsi->base + TWSI_SW_TWSI);
  653. debug("%s: Wrote 0x%llx to sw_twsi\n", __func__, val);
  654. return 0;
  655. }
  656. static const struct octeon_i2c_data i2c_octeon_data = {
  657. .probe = PROBE_DT,
  658. .reg_offs = 0x0000,
  659. .thp = 3,
  660. .clk_method = CLK_METHOD_OCTEON,
  661. };
  662. static const struct octeon_i2c_data i2c_octeontx_data = {
  663. .probe = PROBE_PCI,
  664. .reg_offs = 0x1000,
  665. .thp = 24,
  666. .clk_method = CLK_METHOD_OCTEON,
  667. };
  668. static const struct octeon_i2c_data i2c_octeontx2_data = {
  669. .probe = PROBE_PCI,
  670. .reg_offs = 0x1000,
  671. .thp = 3,
  672. .clk_method = CLK_METHOD_OCTEONTX2,
  673. };
  674. /**
  675. * Driver probe function
  676. *
  677. * @dev I2C device to probe
  678. * @return 0 for success, otherwise error
  679. */
  680. static int octeon_i2c_probe(struct udevice *dev)
  681. {
  682. struct octeon_twsi *twsi = dev_get_priv(dev);
  683. u32 i2c_slave_addr;
  684. int ret;
  685. /* Octeon TX2 needs a different data struct */
  686. if (device_is_compatible(dev, "cavium,thunderx-i2c"))
  687. dev->driver_data = (long)&i2c_octeontx2_data;
  688. twsi->data = (const struct octeon_i2c_data *)dev_get_driver_data(dev);
  689. if (twsi->data->probe == PROBE_PCI) {
  690. pci_dev_t bdf = dm_pci_get_bdf(dev);
  691. debug("TWSI PCI device: %x\n", bdf);
  692. dev->req_seq = PCI_FUNC(bdf);
  693. twsi->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
  694. PCI_REGION_MEM);
  695. } else {
  696. twsi->base = dev_remap_addr(dev);
  697. }
  698. twsi->base += twsi->data->reg_offs;
  699. i2c_slave_addr = dev_read_u32_default(dev, "i2c-sda-hold-time-ns",
  700. CONFIG_SYS_I2C_OCTEON_SLAVE_ADDR);
  701. ret = clk_get_by_index(dev, 0, &twsi->clk);
  702. if (ret < 0)
  703. return ret;
  704. ret = clk_enable(&twsi->clk);
  705. if (ret)
  706. return ret;
  707. debug("TWSI bus %d at %p\n", dev_seq(dev), twsi->base);
  708. /* Start with standard speed, real speed set via DT or cmd */
  709. return twsi_init(twsi->base, i2c_slave_addr);
  710. }
  711. static const struct dm_i2c_ops octeon_i2c_ops = {
  712. .xfer = octeon_i2c_xfer,
  713. .set_bus_speed = octeon_i2c_set_bus_speed,
  714. };
  715. static const struct udevice_id octeon_i2c_ids[] = {
  716. { .compatible = "cavium,octeon-7890-twsi",
  717. .data = (ulong)&i2c_octeon_data },
  718. { .compatible = "cavium,thunder-8890-twsi",
  719. .data = (ulong)&i2c_octeontx_data },
  720. { }
  721. };
  722. U_BOOT_DRIVER(octeon_pci_twsi) = {
  723. .name = "i2c_octeon",
  724. .id = UCLASS_I2C,
  725. .of_match = octeon_i2c_ids,
  726. .probe = octeon_i2c_probe,
  727. .priv_auto = sizeof(struct octeon_twsi),
  728. .ops = &octeon_i2c_ops,
  729. };