nx_i2c.c 14 KB

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  1. #include <common.h>
  2. #include <errno.h>
  3. #include <dm.h>
  4. #include <i2c.h>
  5. #include <log.h>
  6. #include <asm/arch/nexell.h>
  7. #include <asm/arch/reset.h>
  8. #include <asm/arch/clk.h>
  9. #include <asm/arch/nx_gpio.h>
  10. #include <linux/delay.h>
  11. #define I2C_WRITE 0
  12. #define I2C_READ 1
  13. #define I2CSTAT_MTM 0xC0 /* Master Transmit Mode */
  14. #define I2CSTAT_MRM 0x80 /* Master Receive Mode */
  15. #define I2CSTAT_BSY 0x20 /* Read: Bus Busy */
  16. #define I2CSTAT_SS 0x20 /* Write: START (1) / STOP (0) */
  17. #define I2CSTAT_RXTXEN 0x10 /* Rx/Tx enable */
  18. #define I2CSTAT_ABT 0x08 /* Arbitration bit */
  19. #define I2CSTAT_NACK 0x01 /* Nack bit */
  20. #define I2CCON_IRCLR 0x100 /* Interrupt Clear bit */
  21. #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
  22. #define I2CCON_TCP256 0x40 /* Tx-clock prescaler: 16 (0) / 256 (1) */
  23. #define I2CCON_IRENB 0x20 /* Interrupt Enable bit */
  24. #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
  25. #define I2CCON_TCDMSK 0x0F /* I2C-bus transmit clock divider bit mask */
  26. #ifdef CONFIG_ARCH_S5P6818
  27. #define SDADLY_CLKSTEP 5 /* SDA delay: Reg. val. is multiple of 5 clks */
  28. #define SDADLY_MAX 3 /* SDA delay: Max. reg. value is 3 */
  29. #define I2CLC_FILTER 0x04 /* SDA filter on */
  30. #else
  31. #define STOPCON_CLR 0x01 /* Clock Line Release */
  32. #define STOPCON_DLR 0x02 /* Data Line Release */
  33. #define STOPCON_NAG 0x04 /* not-ackn. generation and data shift cont. */
  34. #endif
  35. #define I2C_TIMEOUT_MS 10 /* 10 ms */
  36. #define I2C_M_NOSTOP 0x100
  37. #define MAX_I2C_NUM 3
  38. #define DEFAULT_SPEED 100000 /* default I2C speed [Hz] */
  39. DECLARE_GLOBAL_DATA_PTR;
  40. struct nx_i2c_regs {
  41. uint iiccon;
  42. uint iicstat;
  43. uint iicadd;
  44. uint iicds;
  45. #ifdef CONFIG_ARCH_S5P6818
  46. /* S5P6818: Offset 0x10 is Line Control Register (SDA-delay, Filter) */
  47. uint iiclc;
  48. #else
  49. /* S5P4418: Offset 0x10 is Stop Control Register */
  50. uint iicstopcon;
  51. #endif
  52. };
  53. struct nx_i2c_bus {
  54. uint bus_num;
  55. struct nx_i2c_regs *regs;
  56. uint speed;
  57. uint target_speed;
  58. #ifdef CONFIG_ARCH_S5P6818
  59. uint sda_delay;
  60. #else
  61. /* setup time for Stop condition [us] */
  62. uint tsu_stop;
  63. #endif
  64. };
  65. /* s5pxx18 i2c must be reset before enabled */
  66. static void i2c_reset(int ch)
  67. {
  68. int rst_id = RESET_ID_I2C0 + ch;
  69. nx_rstcon_setrst(rst_id, 0);
  70. nx_rstcon_setrst(rst_id, 1);
  71. }
  72. static uint i2c_get_clkrate(struct nx_i2c_bus *bus)
  73. {
  74. struct clk *clk;
  75. int index = bus->bus_num;
  76. char name[50] = {0, };
  77. sprintf(name, "%s.%d", DEV_NAME_I2C, index);
  78. clk = clk_get((const char *)name);
  79. if (!clk)
  80. return -1;
  81. return clk_get_rate(clk);
  82. }
  83. static uint i2c_set_clk(struct nx_i2c_bus *bus, uint enb)
  84. {
  85. struct clk *clk;
  86. char name[50];
  87. sprintf(name, "%s.%d", DEV_NAME_I2C, bus->bus_num);
  88. clk = clk_get((const char *)name);
  89. if (!clk) {
  90. debug("%s(): clk_get(%s) error!\n",
  91. __func__, (const char *)name);
  92. return -EINVAL;
  93. }
  94. clk_disable(clk);
  95. if (enb)
  96. clk_enable(clk);
  97. return 0;
  98. }
  99. #ifdef CONFIG_ARCH_S5P6818
  100. /* Set SDA line delay, not available at S5P4418 */
  101. static int nx_i2c_set_sda_delay(struct nx_i2c_bus *bus)
  102. {
  103. struct nx_i2c_regs *i2c = bus->regs;
  104. uint pclk = 0;
  105. uint t_pclk = 0;
  106. uint delay = 0;
  107. /* get input clock of the I2C-controller */
  108. pclk = i2c_get_clkrate(bus);
  109. if (bus->sda_delay) {
  110. /* t_pclk = period time of one pclk [ns] */
  111. t_pclk = DIV_ROUND_UP(1000, pclk / 1000000);
  112. /* delay = number of pclks required for sda_delay [ns] */
  113. delay = DIV_ROUND_UP(bus->sda_delay, t_pclk);
  114. /* delay = register value (step of 5 clocks) */
  115. delay = DIV_ROUND_UP(delay, SDADLY_CLKSTEP);
  116. /* max. possible register value = 3 */
  117. if (delay > SDADLY_MAX) {
  118. delay = SDADLY_MAX;
  119. debug("%s(): sda-delay des.: %dns, sat. to max.: %dns (granularity: %dns)\n",
  120. __func__, bus->sda_delay, t_pclk * delay * SDADLY_CLKSTEP,
  121. t_pclk * SDADLY_CLKSTEP);
  122. } else {
  123. debug("%s(): sda-delay des.: %dns, act.: %dns (granularity: %dns)\n",
  124. __func__, bus->sda_delay, t_pclk * delay * SDADLY_CLKSTEP,
  125. t_pclk * SDADLY_CLKSTEP);
  126. }
  127. delay |= I2CLC_FILTER;
  128. } else {
  129. delay = 0;
  130. debug("%s(): sda-delay = 0\n", __func__);
  131. }
  132. delay &= 0x7;
  133. writel(delay, &i2c->iiclc);
  134. return 0;
  135. }
  136. #endif
  137. static int nx_i2c_set_bus_speed(struct udevice *dev, uint speed)
  138. {
  139. struct nx_i2c_bus *bus = dev_get_priv(dev);
  140. struct nx_i2c_regs *i2c = bus->regs;
  141. unsigned long pclk, pres = 16, div;
  142. if (i2c_set_clk(bus, 1))
  143. return -EINVAL;
  144. /* get input clock of the I2C-controller */
  145. pclk = i2c_get_clkrate(bus);
  146. /* calculate prescaler and divisor values */
  147. if ((pclk / pres / (16 + 1)) > speed)
  148. /* prescaler value 16 is too less --> set to 256 */
  149. pres = 256;
  150. div = 0;
  151. /* actual divider = div + 1 */
  152. while ((pclk / pres / (div + 1)) > speed)
  153. div++;
  154. if (div > 0xF) {
  155. debug("%s(): pres==%ld, div==0x%lx is saturated to 0xF !)\n",
  156. __func__, pres, div);
  157. div = 0xF;
  158. } else {
  159. debug("%s(): pres==%ld, div==0x%lx)\n", __func__, pres, div);
  160. }
  161. /* set Tx-clock divisor and prescaler values */
  162. writel((div & I2CCON_TCDMSK) | ((pres == 256) ? I2CCON_TCP256 : 0),
  163. &i2c->iiccon);
  164. /* init to SLAVE REVEIVE and set slaveaddr */
  165. writel(0, &i2c->iicstat);
  166. writel(0x00, &i2c->iicadd);
  167. /* program Master Transmit (and implicit STOP) */
  168. writel(I2CSTAT_MTM | I2CSTAT_RXTXEN, &i2c->iicstat);
  169. /* calculate actual I2C speed [Hz] */
  170. bus->speed = pclk / ((div + 1) * pres);
  171. debug("%s(): speed des.: %dHz, act.: %dHz\n",
  172. __func__, speed, bus->speed);
  173. #ifdef CONFIG_ARCH_S5P6818
  174. nx_i2c_set_sda_delay(bus);
  175. #else
  176. /* setup time for Stop condition [us], min. 4us @ 100kHz I2C-clock */
  177. bus->tsu_stop = DIV_ROUND_UP(400, bus->speed / 1000);
  178. #endif
  179. if (i2c_set_clk(bus, 0))
  180. return -EINVAL;
  181. return 0;
  182. }
  183. static void i2c_process_node(struct udevice *dev)
  184. {
  185. struct nx_i2c_bus *bus = dev_get_priv(dev);
  186. bus->target_speed = dev_read_s32_default(dev, "clock-frequency",
  187. DEFAULT_SPEED);
  188. #ifdef CONFIG_ARCH_S5P6818
  189. bus->sda_delay = dev_read_s32_default(dev, "i2c-sda-delay-ns", 0);
  190. #endif
  191. }
  192. static int nx_i2c_probe(struct udevice *dev)
  193. {
  194. struct nx_i2c_bus *bus = dev_get_priv(dev);
  195. fdt_addr_t addr;
  196. /* get regs = i2c base address */
  197. addr = devfdt_get_addr(dev);
  198. if (addr == FDT_ADDR_T_NONE)
  199. return -EINVAL;
  200. bus->regs = (struct nx_i2c_regs *)addr;
  201. bus->bus_num = dev_seq(dev);
  202. /* i2c node parsing */
  203. i2c_process_node(dev);
  204. if (!bus->target_speed)
  205. return -ENODEV;
  206. /* reset */
  207. i2c_reset(bus->bus_num);
  208. return 0;
  209. }
  210. /* i2c bus busy check */
  211. static int i2c_is_busy(struct nx_i2c_regs *i2c)
  212. {
  213. ulong start_time;
  214. start_time = get_timer(0);
  215. while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
  216. if (get_timer(start_time) > I2C_TIMEOUT_MS) {
  217. debug("Timeout\n");
  218. return -EBUSY;
  219. }
  220. }
  221. return 0;
  222. }
  223. /* irq enable/disable functions */
  224. static void i2c_enable_irq(struct nx_i2c_regs *i2c)
  225. {
  226. unsigned int reg;
  227. reg = readl(&i2c->iiccon);
  228. reg |= I2CCON_IRENB;
  229. writel(reg, &i2c->iiccon);
  230. }
  231. /* irq clear function */
  232. static void i2c_clear_irq(struct nx_i2c_regs *i2c)
  233. {
  234. unsigned int reg;
  235. reg = readl(&i2c->iiccon);
  236. /* reset interrupt pending flag */
  237. reg &= ~(I2CCON_IRPND);
  238. /*
  239. * Interrupt must also be cleared!
  240. * Otherwise linux boot may hang after:
  241. * [ 0.436000] NetLabel: unlabeled traffic allowed by default
  242. * Next would be:
  243. * [ 0.442000] clocksource: Switched to clocksource source timer
  244. */
  245. reg |= I2CCON_IRCLR;
  246. writel(reg, &i2c->iiccon);
  247. }
  248. /* ack enable functions */
  249. static void i2c_enable_ack(struct nx_i2c_regs *i2c)
  250. {
  251. unsigned int reg;
  252. reg = readl(&i2c->iiccon);
  253. reg |= I2CCON_ACKGEN;
  254. writel(reg, &i2c->iiccon);
  255. }
  256. static void i2c_send_stop(struct nx_i2c_bus *bus)
  257. {
  258. struct nx_i2c_regs *i2c = bus->regs;
  259. if (IS_ENABLED(CONFIG_ARCH_S5P6818)) {
  260. unsigned int reg;
  261. reg = readl(&i2c->iicstat);
  262. reg |= I2CSTAT_MRM | I2CSTAT_RXTXEN;
  263. reg &= (~I2CSTAT_SS);
  264. writel(reg, &i2c->iicstat);
  265. i2c_clear_irq(i2c);
  266. } else { /* S5P4418 */
  267. writel(STOPCON_NAG, &i2c->iicstopcon);
  268. i2c_clear_irq(i2c);
  269. /*
  270. * Clock Line Release --> SDC changes from Low to High and
  271. * SDA from High to Low
  272. */
  273. writel(STOPCON_CLR, &i2c->iicstopcon);
  274. /* Hold SDA Low (Setup Time for Stop condition) */
  275. udelay(bus->tsu_stop);
  276. i2c_clear_irq(i2c);
  277. /* Master Receive Mode Stop --> SDA becomes High */
  278. writel(I2CSTAT_MRM, &i2c->iicstat);
  279. }
  280. }
  281. static int wait_for_xfer(struct nx_i2c_regs *i2c)
  282. {
  283. unsigned long start_time = get_timer(0);
  284. do {
  285. if (readl(&i2c->iiccon) & I2CCON_IRPND)
  286. /* return -EREMOTEIO if not Acknowledged, otherwise 0 */
  287. return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
  288. -EREMOTEIO : 0;
  289. } while (get_timer(start_time) < I2C_TIMEOUT_MS);
  290. return -ETIMEDOUT;
  291. }
  292. static int i2c_transfer(struct nx_i2c_regs *i2c,
  293. uchar cmd_type,
  294. uchar chip_addr,
  295. uchar addr[],
  296. uchar addr_len,
  297. uchar data[],
  298. unsigned short data_len,
  299. uint seq)
  300. {
  301. uint status;
  302. int i = 0, result;
  303. /* Note: data_len = 0 is supported for "probe_chip" */
  304. i2c_enable_irq(i2c);
  305. i2c_enable_ack(i2c);
  306. /* Get the slave chip address going */
  307. /* Enable Rx/Tx */
  308. writel(I2CSTAT_RXTXEN, &i2c->iicstat);
  309. writel(chip_addr, &i2c->iicds);
  310. status = I2CSTAT_RXTXEN | I2CSTAT_SS;
  311. if (cmd_type == I2C_WRITE || (addr && addr_len))
  312. status |= I2CSTAT_MTM;
  313. else
  314. status |= I2CSTAT_MRM;
  315. writel(status, &i2c->iicstat);
  316. if (seq)
  317. i2c_clear_irq(i2c);
  318. /* Wait for chip address to transmit. */
  319. result = wait_for_xfer(i2c);
  320. if (result) {
  321. debug("%s: transmitting chip address failed\n", __func__);
  322. goto bailout;
  323. }
  324. /* If register address needs to be transmitted - do it now. */
  325. if (addr && addr_len) { /* register addr */
  326. while ((i < addr_len) && !result) {
  327. writel(addr[i++], &i2c->iicds);
  328. i2c_clear_irq(i2c);
  329. result = wait_for_xfer(i2c);
  330. }
  331. i = 0;
  332. if (result) {
  333. debug("%s: transmitting register address failed\n",
  334. __func__);
  335. goto bailout;
  336. }
  337. }
  338. switch (cmd_type) {
  339. case I2C_WRITE:
  340. while ((i < data_len) && !result) {
  341. writel(data[i++], &i2c->iicds);
  342. i2c_clear_irq(i2c);
  343. result = wait_for_xfer(i2c);
  344. }
  345. break;
  346. case I2C_READ:
  347. if (addr && addr_len) {
  348. /*
  349. * Register address has been sent, now send slave chip
  350. * address again to start the actual read transaction.
  351. */
  352. writel(chip_addr, &i2c->iicds);
  353. /* Generate a re-START. */
  354. writel(I2CSTAT_MRM | I2CSTAT_RXTXEN |
  355. I2CSTAT_SS, &i2c->iicstat);
  356. i2c_clear_irq(i2c);
  357. result = wait_for_xfer(i2c);
  358. if (result) {
  359. debug("%s: I2C_READ: sending chip addr. failed\n",
  360. __func__);
  361. goto bailout;
  362. }
  363. }
  364. while ((i < data_len) && !result) {
  365. /* disable ACK for final READ */
  366. if (i == data_len - 1)
  367. clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
  368. i2c_clear_irq(i2c);
  369. result = wait_for_xfer(i2c);
  370. data[i++] = readb(&i2c->iicds);
  371. }
  372. if (result == -EREMOTEIO)
  373. /* Not Acknowledged --> normal terminated read. */
  374. result = 0;
  375. else if (result == -ETIMEDOUT)
  376. debug("%s: I2C_READ: time out\n", __func__);
  377. else
  378. debug("%s: I2C_READ: read not terminated with NACK\n",
  379. __func__);
  380. break;
  381. default:
  382. debug("%s: bad call\n", __func__);
  383. result = -EINVAL;
  384. break;
  385. }
  386. bailout:
  387. return result;
  388. }
  389. static int nx_i2c_read(struct udevice *dev, uchar chip_addr, uint addr,
  390. uint alen, uchar *buffer, uint len, uint seq)
  391. {
  392. struct nx_i2c_bus *i2c;
  393. uchar xaddr[4];
  394. int ret;
  395. i2c = dev_get_priv(dev);
  396. if (!i2c)
  397. return -EFAULT;
  398. if (alen > 4) {
  399. debug("I2C read: addr len %d not supported\n", alen);
  400. return -EADDRNOTAVAIL;
  401. }
  402. if (alen > 0)
  403. xaddr[0] = (addr >> 24) & 0xFF;
  404. if (alen > 0) {
  405. xaddr[0] = (addr >> 24) & 0xFF;
  406. xaddr[1] = (addr >> 16) & 0xFF;
  407. xaddr[2] = (addr >> 8) & 0xFF;
  408. xaddr[3] = addr & 0xFF;
  409. }
  410. ret = i2c_transfer(i2c->regs, I2C_READ, chip_addr << 1,
  411. &xaddr[4 - alen], alen, buffer, len, seq);
  412. if (ret) {
  413. debug("I2C read failed %d\n", ret);
  414. return -EIO;
  415. }
  416. return 0;
  417. }
  418. static int nx_i2c_write(struct udevice *dev, uchar chip_addr, uint addr,
  419. uint alen, uchar *buffer, uint len, uint seq)
  420. {
  421. struct nx_i2c_bus *i2c;
  422. uchar xaddr[4];
  423. int ret;
  424. i2c = dev_get_priv(dev);
  425. if (!i2c)
  426. return -EFAULT;
  427. if (alen > 4) {
  428. debug("I2C write: addr len %d not supported\n", alen);
  429. return -EINVAL;
  430. }
  431. if (alen > 0) {
  432. xaddr[0] = (addr >> 24) & 0xFF;
  433. xaddr[1] = (addr >> 16) & 0xFF;
  434. xaddr[2] = (addr >> 8) & 0xFF;
  435. xaddr[3] = addr & 0xFF;
  436. }
  437. ret = i2c_transfer(i2c->regs, I2C_WRITE, chip_addr << 1,
  438. &xaddr[4 - alen], alen, buffer, len, seq);
  439. if (ret) {
  440. debug("I2C write failed %d\n", ret);
  441. return -EIO;
  442. }
  443. return 0;
  444. }
  445. static int nx_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
  446. {
  447. struct nx_i2c_bus *bus = dev_get_priv(dev);
  448. struct nx_i2c_regs *i2c = bus->regs;
  449. int ret;
  450. int i;
  451. /* The power loss by the clock, only during on/off. */
  452. ret = i2c_set_clk(bus, 1);
  453. if (!ret)
  454. /* Bus State(Busy) check */
  455. ret = i2c_is_busy(i2c);
  456. if (!ret) {
  457. for (i = 0; i < nmsgs; msg++, i++) {
  458. if (msg->flags & I2C_M_RD) {
  459. ret = nx_i2c_read(dev, msg->addr, 0, 0,
  460. msg->buf, msg->len, i);
  461. } else {
  462. ret = nx_i2c_write(dev, msg->addr, 0, 0,
  463. msg->buf, msg->len, i);
  464. }
  465. if (ret) {
  466. debug("i2c_xfer: error sending\n");
  467. ret = -EREMOTEIO;
  468. }
  469. }
  470. i2c_send_stop(bus);
  471. if (i2c_set_clk(bus, 0))
  472. ret = -EINVAL;
  473. }
  474. return ret;
  475. };
  476. static int nx_i2c_probe_chip(struct udevice *dev, u32 chip_addr,
  477. u32 chip_flags)
  478. {
  479. int ret;
  480. struct nx_i2c_bus *bus = dev_get_priv(dev);
  481. ret = i2c_set_clk(bus, 1);
  482. if (!ret) {
  483. /*
  484. * Send Chip Address only
  485. * --> I2C transfer with data length and address length = 0.
  486. * If there is a Slave, i2c_transfer() returns 0 (acknowledge
  487. * transfer).
  488. * I2C_WRITE must be used in order Master Transmit Mode is
  489. * selected. Otherwise (in Master Receive Mode, I2C_READ)
  490. * sending the stop condition below is not working (SDA does
  491. * not transit to High).
  492. */
  493. ret = i2c_transfer(bus->regs, I2C_WRITE, (uchar)chip_addr << 1,
  494. NULL, 0, NULL, 0, 0);
  495. i2c_send_stop(bus);
  496. if (i2c_set_clk(bus, 0))
  497. ret = -EINVAL;
  498. }
  499. return ret;
  500. }
  501. static const struct dm_i2c_ops nx_i2c_ops = {
  502. .xfer = nx_i2c_xfer,
  503. .probe_chip = nx_i2c_probe_chip,
  504. .set_bus_speed = nx_i2c_set_bus_speed,
  505. };
  506. static const struct udevice_id nx_i2c_ids[] = {
  507. { .compatible = "nexell,s5pxx18-i2c" },
  508. { }
  509. };
  510. U_BOOT_DRIVER(i2c_nexell) = {
  511. .name = "i2c_nexell",
  512. .id = UCLASS_I2C,
  513. .of_match = nx_i2c_ids,
  514. .probe = nx_i2c_probe,
  515. .priv_auto = sizeof(struct nx_i2c_bus),
  516. .ops = &nx_i2c_ops,
  517. };