mxc_i2c.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * i2c driver for Freescale i.MX series
  4. *
  5. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  6. * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
  7. * Copyright 2020 NXP
  8. *
  9. * Based on i2c-imx.c from linux kernel:
  10. * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
  11. * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  12. * Copyright (C) 2007 RightHand Technologies, Inc.
  13. * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  14. *
  15. */
  16. #include <common.h>
  17. #include <log.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/imx-regs.h>
  20. #include <dm/device_compat.h>
  21. #include <linux/delay.h>
  22. #include <linux/errno.h>
  23. #include <asm/mach-imx/mxc_i2c.h>
  24. #include <asm/mach-imx/sys_proto.h>
  25. #include <asm/io.h>
  26. #include <i2c.h>
  27. #include <watchdog.h>
  28. #include <dm.h>
  29. #include <dm/pinctrl.h>
  30. #include <fdtdec.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #define I2C_QUIRK_FLAG (1 << 0)
  33. #define IMX_I2C_REGSHIFT 2
  34. #define VF610_I2C_REGSHIFT 0
  35. #define I2C_EARLY_INIT_INDEX 0
  36. #ifdef CONFIG_SYS_I2C_IFDR_DIV
  37. #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
  38. #else
  39. #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
  40. #endif
  41. /* Register index */
  42. #define IADR 0
  43. #define IFDR 1
  44. #define I2CR 2
  45. #define I2SR 3
  46. #define I2DR 4
  47. #define I2CR_IIEN (1 << 6)
  48. #define I2CR_MSTA (1 << 5)
  49. #define I2CR_MTX (1 << 4)
  50. #define I2CR_TX_NO_AK (1 << 3)
  51. #define I2CR_RSTA (1 << 2)
  52. #define I2SR_ICF (1 << 7)
  53. #define I2SR_IBB (1 << 5)
  54. #define I2SR_IAL (1 << 4)
  55. #define I2SR_IIF (1 << 1)
  56. #define I2SR_RX_NO_AK (1 << 0)
  57. #ifdef I2C_QUIRK_REG
  58. #define I2CR_IEN (0 << 7)
  59. #define I2CR_IDIS (1 << 7)
  60. #define I2SR_IIF_CLEAR (1 << 1)
  61. #else
  62. #define I2CR_IEN (1 << 7)
  63. #define I2CR_IDIS (0 << 7)
  64. #define I2SR_IIF_CLEAR (0 << 1)
  65. #endif
  66. #ifdef I2C_QUIRK_REG
  67. static u16 i2c_clk_div[60][2] = {
  68. { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
  69. { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
  70. { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
  71. { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
  72. { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
  73. { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
  74. { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
  75. { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
  76. { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
  77. { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
  78. { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
  79. { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
  80. { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
  81. { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
  82. { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
  83. };
  84. #else
  85. static u16 i2c_clk_div[50][2] = {
  86. { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
  87. { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
  88. { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
  89. { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
  90. { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
  91. { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
  92. { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
  93. { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
  94. { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
  95. { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
  96. { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
  97. { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
  98. { 3072, 0x1E }, { 3840, 0x1F }
  99. };
  100. #endif
  101. #ifndef CONFIG_SYS_MXC_I2C1_SPEED
  102. #define CONFIG_SYS_MXC_I2C1_SPEED 100000
  103. #endif
  104. #ifndef CONFIG_SYS_MXC_I2C2_SPEED
  105. #define CONFIG_SYS_MXC_I2C2_SPEED 100000
  106. #endif
  107. #ifndef CONFIG_SYS_MXC_I2C3_SPEED
  108. #define CONFIG_SYS_MXC_I2C3_SPEED 100000
  109. #endif
  110. #ifndef CONFIG_SYS_MXC_I2C4_SPEED
  111. #define CONFIG_SYS_MXC_I2C4_SPEED 100000
  112. #endif
  113. #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
  114. #define CONFIG_SYS_MXC_I2C1_SLAVE 0
  115. #endif
  116. #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
  117. #define CONFIG_SYS_MXC_I2C2_SLAVE 0
  118. #endif
  119. #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
  120. #define CONFIG_SYS_MXC_I2C3_SLAVE 0
  121. #endif
  122. #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
  123. #define CONFIG_SYS_MXC_I2C4_SLAVE 0
  124. #endif
  125. /*
  126. * Calculate and set proper clock divider
  127. */
  128. static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
  129. {
  130. unsigned int i2c_clk_rate;
  131. unsigned int div;
  132. u8 clk_div;
  133. #if defined(CONFIG_MX31)
  134. struct clock_control_regs *sc_regs =
  135. (struct clock_control_regs *)CCM_BASE;
  136. /* start the required I2C clock */
  137. writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
  138. &sc_regs->cgr0);
  139. #endif
  140. /* Divider value calculation */
  141. #if CONFIG_IS_ENABLED(CLK)
  142. i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
  143. #else
  144. i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
  145. #endif
  146. div = (i2c_clk_rate + rate - 1) / rate;
  147. if (div < i2c_clk_div[0][0])
  148. clk_div = 0;
  149. else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
  150. clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
  151. else
  152. for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
  153. ;
  154. /* Store divider value */
  155. return clk_div;
  156. }
  157. /*
  158. * Set I2C Bus speed
  159. */
  160. static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
  161. {
  162. ulong base = i2c_bus->base;
  163. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  164. u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
  165. u8 idx = i2c_clk_div[clk_idx][1];
  166. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  167. if (!base)
  168. return -EINVAL;
  169. /* Store divider value */
  170. writeb(idx, base + (IFDR << reg_shift));
  171. /* Reset module */
  172. writeb(I2CR_IDIS, base + (I2CR << reg_shift));
  173. writeb(0, base + (I2SR << reg_shift));
  174. return 0;
  175. }
  176. #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
  177. #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
  178. #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
  179. static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
  180. {
  181. unsigned sr;
  182. ulong elapsed;
  183. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  184. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  185. ulong base = i2c_bus->base;
  186. ulong start_time = get_timer(0);
  187. for (;;) {
  188. sr = readb(base + (I2SR << reg_shift));
  189. if (sr & I2SR_IAL) {
  190. if (quirk)
  191. writeb(sr | I2SR_IAL, base +
  192. (I2SR << reg_shift));
  193. else
  194. writeb(sr & ~I2SR_IAL, base +
  195. (I2SR << reg_shift));
  196. printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
  197. __func__, sr, readb(base + (I2CR << reg_shift)),
  198. state);
  199. return -ERESTART;
  200. }
  201. if ((sr & (state >> 8)) == (unsigned char)state)
  202. return sr;
  203. WATCHDOG_RESET();
  204. elapsed = get_timer(start_time);
  205. if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
  206. break;
  207. }
  208. printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
  209. sr, readb(base + (I2CR << reg_shift)), state);
  210. return -ETIMEDOUT;
  211. }
  212. static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
  213. {
  214. int ret;
  215. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  216. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  217. ulong base = i2c_bus->base;
  218. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  219. writeb(byte, base + (I2DR << reg_shift));
  220. ret = wait_for_sr_state(i2c_bus, ST_IIF);
  221. if (ret < 0)
  222. return ret;
  223. if (ret & I2SR_RX_NO_AK)
  224. return -EREMOTEIO;
  225. return 0;
  226. }
  227. /*
  228. * Stub implementations for outer i2c slave operations.
  229. */
  230. void __i2c_force_reset_slave(void)
  231. {
  232. }
  233. void i2c_force_reset_slave(void)
  234. __attribute__((weak, alias("__i2c_force_reset_slave")));
  235. /*
  236. * Stop I2C transaction
  237. */
  238. static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
  239. {
  240. int ret;
  241. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  242. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  243. ulong base = i2c_bus->base;
  244. unsigned int temp = readb(base + (I2CR << reg_shift));
  245. temp &= ~(I2CR_MSTA | I2CR_MTX);
  246. writeb(temp, base + (I2CR << reg_shift));
  247. ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
  248. if (ret < 0)
  249. printf("%s:trigger stop failed\n", __func__);
  250. }
  251. /*
  252. * Send start signal, chip address and
  253. * write register address
  254. */
  255. static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
  256. u32 addr, int alen)
  257. {
  258. unsigned int temp;
  259. int ret;
  260. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  261. ulong base = i2c_bus->base;
  262. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  263. /* Reset i2c slave */
  264. i2c_force_reset_slave();
  265. /* Enable I2C controller */
  266. if (quirk)
  267. ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
  268. else
  269. ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
  270. if (ret) {
  271. writeb(I2CR_IEN, base + (I2CR << reg_shift));
  272. /* Wait for controller to be stable */
  273. udelay(50);
  274. }
  275. if (readb(base + (IADR << reg_shift)) == (chip << 1))
  276. writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
  277. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  278. ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
  279. if (ret < 0)
  280. return ret;
  281. /* Start I2C transaction */
  282. temp = readb(base + (I2CR << reg_shift));
  283. temp |= I2CR_MSTA;
  284. writeb(temp, base + (I2CR << reg_shift));
  285. ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
  286. if (ret < 0)
  287. return ret;
  288. temp |= I2CR_MTX | I2CR_TX_NO_AK;
  289. writeb(temp, base + (I2CR << reg_shift));
  290. if (alen >= 0) {
  291. /* write slave address */
  292. ret = tx_byte(i2c_bus, chip << 1);
  293. if (ret < 0)
  294. return ret;
  295. while (alen--) {
  296. ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
  297. if (ret < 0)
  298. return ret;
  299. }
  300. }
  301. return 0;
  302. }
  303. #if !defined(I2C2_BASE_ADDR)
  304. #define I2C2_BASE_ADDR 0
  305. #endif
  306. #if !defined(I2C3_BASE_ADDR)
  307. #define I2C3_BASE_ADDR 0
  308. #endif
  309. #if !defined(I2C4_BASE_ADDR)
  310. #define I2C4_BASE_ADDR 0
  311. #endif
  312. #if !defined(I2C5_BASE_ADDR)
  313. #define I2C5_BASE_ADDR 0
  314. #endif
  315. #if !defined(I2C6_BASE_ADDR)
  316. #define I2C6_BASE_ADDR 0
  317. #endif
  318. #if !defined(I2C7_BASE_ADDR)
  319. #define I2C7_BASE_ADDR 0
  320. #endif
  321. #if !defined(I2C8_BASE_ADDR)
  322. #define I2C8_BASE_ADDR 0
  323. #endif
  324. static struct mxc_i2c_bus mxc_i2c_buses[] = {
  325. #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
  326. defined(CONFIG_FSL_LAYERSCAPE)
  327. { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
  328. { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
  329. { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
  330. { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
  331. { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
  332. { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
  333. { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
  334. { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
  335. #else
  336. { 0, I2C1_BASE_ADDR, 0 },
  337. { 1, I2C2_BASE_ADDR, 0 },
  338. { 2, I2C3_BASE_ADDR, 0 },
  339. { 3, I2C4_BASE_ADDR, 0 },
  340. { 4, I2C5_BASE_ADDR, 0 },
  341. { 5, I2C6_BASE_ADDR, 0 },
  342. { 6, I2C7_BASE_ADDR, 0 },
  343. { 7, I2C8_BASE_ADDR, 0 },
  344. #endif
  345. };
  346. #ifndef CONFIG_DM_I2C
  347. int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
  348. {
  349. if (i2c_bus && i2c_bus->idle_bus_fn)
  350. return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
  351. return 0;
  352. }
  353. #else
  354. /*
  355. * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
  356. * "
  357. * scl-gpios: specify the gpio related to SCL pin
  358. * sda-gpios: specify the gpio related to SDA pin
  359. * add pinctrl to configure i2c pins to gpio function for i2c
  360. * bus recovery, call it "gpio" state
  361. * "
  362. *
  363. * The i2c_idle_bus is an implementation following Linux Kernel.
  364. */
  365. int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
  366. {
  367. struct udevice *bus = i2c_bus->bus;
  368. struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
  369. struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
  370. struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
  371. int sda, scl, idle_sclks;
  372. int i, ret = 0;
  373. ulong elapsed, start_time;
  374. if (pinctrl_select_state(bus, "gpio")) {
  375. dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
  376. /*
  377. * GPIO pinctrl for i2c force idle is not a must,
  378. * but it is strongly recommended to be used.
  379. * Because it can help you to recover from bad
  380. * i2c bus state. Do not return failure, because
  381. * it is not a must.
  382. */
  383. return 0;
  384. }
  385. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  386. dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
  387. scl = dm_gpio_get_value(scl_gpio);
  388. sda = dm_gpio_get_value(sda_gpio);
  389. if ((sda & scl) == 1)
  390. goto exit; /* Bus is idle already */
  391. /*
  392. * In most cases it is just enough to generate 8 + 1 SCLK
  393. * clocks to recover I2C slave device from 'stuck' state
  394. * (when for example SW reset was performed, in the middle of
  395. * I2C transmission).
  396. *
  397. * However, there are devices which send data in packets of
  398. * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
  399. * clocks.
  400. */
  401. idle_sclks = 8 + 1;
  402. if (i2c->max_transaction_bytes > 0)
  403. idle_sclks = i2c->max_transaction_bytes * 8 + 1;
  404. /* Send high and low on the SCL line */
  405. for (i = 0; i < idle_sclks; i++) {
  406. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
  407. dm_gpio_set_value(scl_gpio, 0);
  408. udelay(50);
  409. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  410. udelay(50);
  411. }
  412. start_time = get_timer(0);
  413. for (;;) {
  414. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  415. dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
  416. scl = dm_gpio_get_value(scl_gpio);
  417. sda = dm_gpio_get_value(sda_gpio);
  418. if ((sda & scl) == 1)
  419. break;
  420. WATCHDOG_RESET();
  421. elapsed = get_timer(start_time);
  422. if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
  423. ret = -EBUSY;
  424. printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
  425. break;
  426. }
  427. }
  428. exit:
  429. pinctrl_select_state(bus, "default");
  430. return ret;
  431. }
  432. #endif
  433. /*
  434. * Early init I2C for prepare read the clk through I2C.
  435. */
  436. void i2c_early_init_f(void)
  437. {
  438. ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
  439. bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
  440. & I2C_QUIRK_FLAG ? true : false;
  441. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  442. /* Set I2C divider value */
  443. writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
  444. /* Reset module */
  445. writeb(I2CR_IDIS, base + (I2CR << reg_shift));
  446. writeb(0, base + (I2SR << reg_shift));
  447. /* Enable I2C */
  448. writeb(I2CR_IEN, base + (I2CR << reg_shift));
  449. }
  450. static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
  451. u32 addr, int alen)
  452. {
  453. int retry;
  454. int ret;
  455. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  456. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  457. if (!i2c_bus->base)
  458. return -EINVAL;
  459. for (retry = 0; retry < 3; retry++) {
  460. ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
  461. if (ret >= 0)
  462. return 0;
  463. i2c_imx_stop(i2c_bus);
  464. if (ret == -EREMOTEIO)
  465. return ret;
  466. printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
  467. retry);
  468. if (ret != -ERESTART)
  469. /* Disable controller */
  470. writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
  471. udelay(100);
  472. if (i2c_idle_bus(i2c_bus) < 0)
  473. break;
  474. }
  475. printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
  476. return ret;
  477. }
  478. static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
  479. int len)
  480. {
  481. int i, ret = 0;
  482. debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
  483. debug("write_data: ");
  484. /* use rc for counter */
  485. for (i = 0; i < len; ++i)
  486. debug(" 0x%02x", buf[i]);
  487. debug("\n");
  488. for (i = 0; i < len; i++) {
  489. ret = tx_byte(i2c_bus, buf[i]);
  490. if (ret < 0) {
  491. debug("i2c_write_data(): rc=%d\n", ret);
  492. break;
  493. }
  494. }
  495. return ret;
  496. }
  497. /* Will generate a STOP after the last byte if "last" is true, i.e. this is the
  498. * final message of a transaction. If not, it switches the bus back to TX mode
  499. * and does not send a STOP, leaving the bus in a state where a repeated start
  500. * and address can be sent for another message.
  501. */
  502. static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
  503. int len, bool last)
  504. {
  505. int ret;
  506. unsigned int temp;
  507. int i;
  508. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  509. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  510. ulong base = i2c_bus->base;
  511. debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
  512. /* setup bus to read data */
  513. temp = readb(base + (I2CR << reg_shift));
  514. temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
  515. if (len == 1)
  516. temp |= I2CR_TX_NO_AK;
  517. writeb(temp, base + (I2CR << reg_shift));
  518. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  519. /* dummy read to clear ICF */
  520. readb(base + (I2DR << reg_shift));
  521. /* read data */
  522. for (i = 0; i < len; i++) {
  523. ret = wait_for_sr_state(i2c_bus, ST_IIF);
  524. if (ret < 0) {
  525. debug("i2c_read_data(): ret=%d\n", ret);
  526. i2c_imx_stop(i2c_bus);
  527. return ret;
  528. }
  529. if (i == (len - 1)) {
  530. /* Final byte has already been received by master! When
  531. * we read it from I2DR, the master will start another
  532. * cycle. We must program it first to send a STOP or
  533. * switch to TX to avoid this.
  534. */
  535. if (last) {
  536. i2c_imx_stop(i2c_bus);
  537. } else {
  538. /* Final read, no stop, switch back to tx */
  539. temp = readb(base + (I2CR << reg_shift));
  540. temp |= I2CR_MTX | I2CR_TX_NO_AK;
  541. writeb(temp, base + (I2CR << reg_shift));
  542. }
  543. } else if (i == (len - 2)) {
  544. /* Master has already recevied penultimate byte. When
  545. * we read it from I2DR, master will start RX of final
  546. * byte. We must set TX_NO_AK now so it does not ACK
  547. * that final byte.
  548. */
  549. temp = readb(base + (I2CR << reg_shift));
  550. temp |= I2CR_TX_NO_AK;
  551. writeb(temp, base + (I2CR << reg_shift));
  552. }
  553. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  554. buf[i] = readb(base + (I2DR << reg_shift));
  555. }
  556. /* reuse ret for counter*/
  557. for (ret = 0; ret < len; ++ret)
  558. debug(" 0x%02x", buf[ret]);
  559. debug("\n");
  560. /* It is not clear to me that this is necessary */
  561. if (last)
  562. i2c_imx_stop(i2c_bus);
  563. return 0;
  564. }
  565. int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  566. {
  567. return 1;
  568. }
  569. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  570. __attribute__((weak, alias("__enable_i2c_clk")));
  571. #ifndef CONFIG_DM_I2C
  572. /*
  573. * Read data from I2C device
  574. *
  575. * The transactions use the syntax defined in the Linux kernel I2C docs.
  576. *
  577. * If alen is > 0, then this function will send a transaction of the form:
  578. * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
  579. * This is a normal I2C register read: writing the register address, then doing
  580. * a repeated start and reading the data.
  581. *
  582. * If alen == 0, then we get this transaction:
  583. * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
  584. * This is somewhat unusual, though valid, transaction. It addresses the chip
  585. * in write mode, but doesn't actually write any register address or data, then
  586. * does a repeated start and reads data.
  587. *
  588. * If alen < 0, then we get this transaction:
  589. * S Chip Rd [A] [data] A ... NA P
  590. * The chip is addressed in read mode and then data is read. No register
  591. * address is written first. This is perfectly valid on most devices and
  592. * required on some (usually those that don't act like an array of registers).
  593. */
  594. static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
  595. int alen, u8 *buf, int len)
  596. {
  597. int ret = 0;
  598. u32 temp;
  599. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  600. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  601. ulong base = i2c_bus->base;
  602. ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
  603. if (ret < 0)
  604. return ret;
  605. if (alen >= 0) {
  606. temp = readb(base + (I2CR << reg_shift));
  607. temp |= I2CR_RSTA;
  608. writeb(temp, base + (I2CR << reg_shift));
  609. }
  610. ret = tx_byte(i2c_bus, (chip << 1) | 1);
  611. if (ret < 0) {
  612. i2c_imx_stop(i2c_bus);
  613. return ret;
  614. }
  615. ret = i2c_read_data(i2c_bus, chip, buf, len, true);
  616. i2c_imx_stop(i2c_bus);
  617. return ret;
  618. }
  619. /*
  620. * Write data to I2C device
  621. *
  622. * If alen > 0, we get this transaction:
  623. * S Chip Wr [A] addr [A] data [A] ... [A] P
  624. * An ordinary write register command.
  625. *
  626. * If alen == 0, then we get this:
  627. * S Chip Wr [A] data [A] ... [A] P
  628. * This is a simple I2C write.
  629. *
  630. * If alen < 0, then we get this:
  631. * S data [A] ... [A] P
  632. * This is most likely NOT something that should be used. It doesn't send the
  633. * chip address first, so in effect, the first byte of data will be used as the
  634. * address.
  635. */
  636. static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
  637. int alen, const u8 *buf, int len)
  638. {
  639. int ret = 0;
  640. ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
  641. if (ret < 0)
  642. return ret;
  643. ret = i2c_write_data(i2c_bus, chip, buf, len);
  644. i2c_imx_stop(i2c_bus);
  645. return ret;
  646. }
  647. struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
  648. {
  649. return &mxc_i2c_buses[adap->hwadapnr];
  650. }
  651. static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  652. uint addr, int alen, uint8_t *buffer,
  653. int len)
  654. {
  655. return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
  656. }
  657. static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
  658. uint addr, int alen, uint8_t *buffer,
  659. int len)
  660. {
  661. return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
  662. }
  663. /*
  664. * Test if a chip at a given address responds (probe the chip)
  665. */
  666. static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
  667. {
  668. return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
  669. }
  670. void bus_i2c_init(int index, int speed, int unused,
  671. int (*idle_bus_fn)(void *p), void *idle_bus_data)
  672. {
  673. int ret;
  674. if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
  675. debug("Error i2c index\n");
  676. return;
  677. }
  678. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  679. if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
  680. printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
  681. (ulong)mxc_i2c_buses[index].base);
  682. return;
  683. }
  684. }
  685. /*
  686. * Warning: Be careful to allow the assignment to a static
  687. * variable here. This function could be called while U-Boot is
  688. * still running in flash memory. So such assignment is equal
  689. * to write data to flash without erasing.
  690. */
  691. if (idle_bus_fn)
  692. mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
  693. if (idle_bus_data)
  694. mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
  695. ret = enable_i2c_clk(1, index);
  696. if (ret < 0) {
  697. debug("I2C-%d clk fail to enable.\n", index);
  698. return;
  699. }
  700. bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
  701. }
  702. /*
  703. * Init I2C Bus
  704. */
  705. static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  706. {
  707. bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
  708. }
  709. /*
  710. * Set I2C Speed
  711. */
  712. static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  713. {
  714. return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
  715. }
  716. /*
  717. * Register mxc i2c adapters
  718. */
  719. #ifdef CONFIG_SYS_I2C_MXC_I2C1
  720. U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
  721. mxc_i2c_read, mxc_i2c_write,
  722. mxc_i2c_set_bus_speed,
  723. CONFIG_SYS_MXC_I2C1_SPEED,
  724. CONFIG_SYS_MXC_I2C1_SLAVE, 0)
  725. #endif
  726. #ifdef CONFIG_SYS_I2C_MXC_I2C2
  727. U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
  728. mxc_i2c_read, mxc_i2c_write,
  729. mxc_i2c_set_bus_speed,
  730. CONFIG_SYS_MXC_I2C2_SPEED,
  731. CONFIG_SYS_MXC_I2C2_SLAVE, 1)
  732. #endif
  733. #ifdef CONFIG_SYS_I2C_MXC_I2C3
  734. U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
  735. mxc_i2c_read, mxc_i2c_write,
  736. mxc_i2c_set_bus_speed,
  737. CONFIG_SYS_MXC_I2C3_SPEED,
  738. CONFIG_SYS_MXC_I2C3_SLAVE, 2)
  739. #endif
  740. #ifdef CONFIG_SYS_I2C_MXC_I2C4
  741. U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
  742. mxc_i2c_read, mxc_i2c_write,
  743. mxc_i2c_set_bus_speed,
  744. CONFIG_SYS_MXC_I2C4_SPEED,
  745. CONFIG_SYS_MXC_I2C4_SLAVE, 3)
  746. #endif
  747. #ifdef CONFIG_SYS_I2C_MXC_I2C5
  748. U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
  749. mxc_i2c_read, mxc_i2c_write,
  750. mxc_i2c_set_bus_speed,
  751. CONFIG_SYS_MXC_I2C5_SPEED,
  752. CONFIG_SYS_MXC_I2C5_SLAVE, 4)
  753. #endif
  754. #ifdef CONFIG_SYS_I2C_MXC_I2C6
  755. U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
  756. mxc_i2c_read, mxc_i2c_write,
  757. mxc_i2c_set_bus_speed,
  758. CONFIG_SYS_MXC_I2C6_SPEED,
  759. CONFIG_SYS_MXC_I2C6_SLAVE, 5)
  760. #endif
  761. #ifdef CONFIG_SYS_I2C_MXC_I2C7
  762. U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
  763. mxc_i2c_read, mxc_i2c_write,
  764. mxc_i2c_set_bus_speed,
  765. CONFIG_SYS_MXC_I2C7_SPEED,
  766. CONFIG_SYS_MXC_I2C7_SLAVE, 6)
  767. #endif
  768. #ifdef CONFIG_SYS_I2C_MXC_I2C8
  769. U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
  770. mxc_i2c_read, mxc_i2c_write,
  771. mxc_i2c_set_bus_speed,
  772. CONFIG_SYS_MXC_I2C8_SPEED,
  773. CONFIG_SYS_MXC_I2C8_SLAVE, 7)
  774. #endif
  775. #else
  776. static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  777. {
  778. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  779. return bus_i2c_set_bus_speed(i2c_bus, speed);
  780. }
  781. static int mxc_i2c_probe(struct udevice *bus)
  782. {
  783. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  784. const void *fdt = gd->fdt_blob;
  785. int node = dev_of_offset(bus);
  786. fdt_addr_t addr;
  787. int ret, ret2;
  788. i2c_bus->driver_data = dev_get_driver_data(bus);
  789. addr = dev_read_addr(bus);
  790. if (addr == FDT_ADDR_T_NONE)
  791. return -EINVAL;
  792. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  793. if (i2c_fused((ulong)addr)) {
  794. printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
  795. (ulong)addr);
  796. return -ENODEV;
  797. }
  798. }
  799. i2c_bus->base = addr;
  800. i2c_bus->index = dev_seq(bus);
  801. i2c_bus->bus = bus;
  802. /* Enable clk */
  803. #if CONFIG_IS_ENABLED(CLK)
  804. ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
  805. if (ret) {
  806. printf("Failed to get i2c clk\n");
  807. return ret;
  808. }
  809. ret = clk_enable(&i2c_bus->per_clk);
  810. if (ret) {
  811. printf("Failed to enable i2c clk\n");
  812. return ret;
  813. }
  814. #else
  815. ret = enable_i2c_clk(1, dev_seq(bus));
  816. if (ret < 0)
  817. return ret;
  818. #endif
  819. /*
  820. * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
  821. * Use gpio to force bus idle when necessary.
  822. */
  823. ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
  824. if (ret < 0) {
  825. debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
  826. dev_seq(bus), i2c_bus->base);
  827. } else {
  828. ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
  829. "scl-gpios", 0, &i2c_bus->scl_gpio,
  830. GPIOD_IS_OUT);
  831. ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
  832. "sda-gpios", 0, &i2c_bus->sda_gpio,
  833. GPIOD_IS_OUT);
  834. if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
  835. !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
  836. ret || ret2) {
  837. dev_err(bus,
  838. "i2c bus %d at %lu, fail to request scl/sda gpio\n",
  839. dev_seq(bus), i2c_bus->base);
  840. return -EINVAL;
  841. }
  842. }
  843. /*
  844. * Pinmux settings are in board file now, until pinmux is supported,
  845. * we can set pinmux here in probe function.
  846. */
  847. debug("i2c : controller bus %d at %lu , speed %d: ",
  848. dev_seq(bus), i2c_bus->base,
  849. i2c_bus->speed);
  850. return 0;
  851. }
  852. /* Sends: S Addr Wr [A|NA] P */
  853. static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  854. u32 chip_flags)
  855. {
  856. int ret;
  857. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  858. ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
  859. if (ret < 0) {
  860. debug("%s failed, ret = %d\n", __func__, ret);
  861. return ret;
  862. }
  863. i2c_imx_stop(i2c_bus);
  864. return 0;
  865. }
  866. static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  867. {
  868. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  869. int ret = 0;
  870. ulong base = i2c_bus->base;
  871. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  872. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  873. int read_mode;
  874. /* Here address len is set to -1 to not send any address at first.
  875. * Otherwise i2c_init_transfer will send the chip address with write
  876. * mode set. This is wrong if the 1st message is read.
  877. */
  878. ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
  879. if (ret < 0) {
  880. debug("i2c_init_transfer error: %d\n", ret);
  881. return ret;
  882. }
  883. read_mode = -1; /* So it's always different on the first message */
  884. for (; nmsgs > 0; nmsgs--, msg++) {
  885. const int msg_is_read = !!(msg->flags & I2C_M_RD);
  886. debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
  887. msg->len, msg_is_read ? 'R' : 'W');
  888. if (msg_is_read != read_mode) {
  889. /* Send repeated start if not 1st message */
  890. if (read_mode != -1) {
  891. debug("i2c_xfer: [RSTART]\n");
  892. ret = readb(base + (I2CR << reg_shift));
  893. ret |= I2CR_RSTA;
  894. writeb(ret, base + (I2CR << reg_shift));
  895. }
  896. debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
  897. msg_is_read ? 'R' : 'W');
  898. ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
  899. if (ret < 0) {
  900. debug("i2c_xfer: [STOP]\n");
  901. i2c_imx_stop(i2c_bus);
  902. break;
  903. }
  904. read_mode = msg_is_read;
  905. }
  906. if (msg->flags & I2C_M_RD)
  907. ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
  908. msg->len, nmsgs == 1 ||
  909. (msg->flags & I2C_M_STOP));
  910. else
  911. ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
  912. msg->len);
  913. if (ret < 0)
  914. break;
  915. }
  916. if (ret)
  917. debug("i2c_write: error sending\n");
  918. i2c_imx_stop(i2c_bus);
  919. return ret;
  920. }
  921. static const struct dm_i2c_ops mxc_i2c_ops = {
  922. .xfer = mxc_i2c_xfer,
  923. .probe_chip = mxc_i2c_probe_chip,
  924. .set_bus_speed = mxc_i2c_set_bus_speed,
  925. };
  926. static const struct udevice_id mxc_i2c_ids[] = {
  927. { .compatible = "fsl,imx21-i2c", },
  928. { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
  929. {}
  930. };
  931. U_BOOT_DRIVER(i2c_mxc) = {
  932. .name = "i2c_mxc",
  933. .id = UCLASS_I2C,
  934. .of_match = mxc_i2c_ids,
  935. .probe = mxc_i2c_probe,
  936. .priv_auto = sizeof(struct mxc_i2c_bus),
  937. .ops = &mxc_i2c_ops,
  938. .flags = DM_FLAG_PRE_RELOC,
  939. };
  940. #endif