lpc32xx_i2c.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * LPC32xx I2C interface driver
  4. *
  5. * (C) Copyright 2014-2015 DENX Software Engineering GmbH
  6. * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <asm/io.h>
  11. #include <i2c.h>
  12. #include <linux/errno.h>
  13. #include <asm/arch/clk.h>
  14. #include <asm/arch/i2c.h>
  15. #include <dm.h>
  16. #include <mapmem.h>
  17. /*
  18. * Provide default speed and slave if target did not
  19. */
  20. #if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
  21. #define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
  22. #endif
  23. #if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
  24. #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
  25. #endif
  26. /* TX register fields */
  27. #define LPC32XX_I2C_TX_START 0x00000100
  28. #define LPC32XX_I2C_TX_STOP 0x00000200
  29. /* Control register values */
  30. #define LPC32XX_I2C_SOFT_RESET 0x00000100
  31. /* Status register values */
  32. #define LPC32XX_I2C_STAT_TFF 0x00000400
  33. #define LPC32XX_I2C_STAT_RFE 0x00000200
  34. #define LPC32XX_I2C_STAT_DRMI 0x00000008
  35. #define LPC32XX_I2C_STAT_NAI 0x00000004
  36. #define LPC32XX_I2C_STAT_TDI 0x00000001
  37. #ifndef CONFIG_DM_I2C
  38. static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
  39. (struct lpc32xx_i2c_base *)I2C1_BASE,
  40. (struct lpc32xx_i2c_base *)I2C2_BASE,
  41. (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
  42. };
  43. #endif
  44. /* Set I2C bus speed */
  45. static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
  46. unsigned int speed, unsigned int chip)
  47. {
  48. int half_period;
  49. if (speed == 0)
  50. return -EINVAL;
  51. /* OTG I2C clock source and CLK registers are different */
  52. if (chip == 2) {
  53. half_period = (get_periph_clk_rate() / speed) / 2;
  54. if (half_period > 0xFF)
  55. return -EINVAL;
  56. } else {
  57. half_period = (get_hclk_clk_rate() / speed) / 2;
  58. if (half_period > 0x3FF)
  59. return -EINVAL;
  60. }
  61. writel(half_period, &base->clk_hi);
  62. writel(half_period, &base->clk_lo);
  63. return 0;
  64. }
  65. /* I2C init called by cmd_i2c when doing 'i2c reset'. */
  66. static void __i2c_init(struct lpc32xx_i2c_base *base,
  67. int requested_speed, int slaveadd, unsigned int chip)
  68. {
  69. /* soft reset (auto-clears) */
  70. writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
  71. /* set HI and LO periods for half of the default speed */
  72. __i2c_set_bus_speed(base, requested_speed, chip);
  73. }
  74. /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
  75. static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
  76. {
  77. int stat;
  78. /* Soft-reset the controller */
  79. writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
  80. while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
  81. ;
  82. /* Addre slave for write with start before and stop after */
  83. writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
  84. &base->tx);
  85. /* wait for end of transation */
  86. while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
  87. ;
  88. /* was there no acknowledge? */
  89. return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
  90. }
  91. /*
  92. * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
  93. * Begin write, send address byte(s), begin read, receive data bytes, end.
  94. */
  95. static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
  96. int alen, u8 *data, int length)
  97. {
  98. int stat, wlen;
  99. /* Soft-reset the controller */
  100. writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
  101. while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
  102. ;
  103. /* do we need to write an address at all? */
  104. if (alen) {
  105. /* Address slave in write mode */
  106. writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
  107. /* write address bytes */
  108. while (alen--) {
  109. /* compute address byte + stop for the last one */
  110. int a = (addr >> (8 * alen)) & 0xff;
  111. if (!alen)
  112. a |= LPC32XX_I2C_TX_STOP;
  113. /* Send address byte */
  114. writel(a, &base->tx);
  115. }
  116. /* wait for end of transation */
  117. while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
  118. ;
  119. /* clear end-of-transaction flag */
  120. writel(1, &base->stat);
  121. }
  122. /* do we have to read data at all? */
  123. if (length) {
  124. /* Address slave in read mode */
  125. writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
  126. wlen = length;
  127. /* get data */
  128. while (length | wlen) {
  129. /* read status for TFF and RFE */
  130. stat = readl(&base->stat);
  131. /* must we, can we write a trigger byte? */
  132. if ((wlen > 0)
  133. & (!(stat & LPC32XX_I2C_STAT_TFF))) {
  134. wlen--;
  135. /* write trigger byte + stop if last */
  136. writel(wlen ? 0 :
  137. LPC32XX_I2C_TX_STOP, &base->tx);
  138. }
  139. /* must we, can we read a data byte? */
  140. if ((length > 0)
  141. & (!(stat & LPC32XX_I2C_STAT_RFE))) {
  142. length--;
  143. /* read byte */
  144. *(data++) = readl(&base->rx);
  145. }
  146. }
  147. /* wait for end of transation */
  148. while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
  149. ;
  150. /* clear end-of-transaction flag */
  151. writel(1, &base->stat);
  152. }
  153. /* success */
  154. return 0;
  155. }
  156. /*
  157. * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
  158. * Begin write, send address byte(s), send data bytes, end.
  159. */
  160. static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
  161. int alen, u8 *data, int length)
  162. {
  163. int stat;
  164. /* Soft-reset the controller */
  165. writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
  166. while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
  167. ;
  168. /* do we need to write anything at all? */
  169. if (alen | length)
  170. /* Address slave in write mode */
  171. writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
  172. else
  173. return 0;
  174. /* write address bytes */
  175. while (alen) {
  176. /* wait for transmit fifo not full */
  177. stat = readl(&base->stat);
  178. if (!(stat & LPC32XX_I2C_STAT_TFF)) {
  179. alen--;
  180. int a = (addr >> (8 * alen)) & 0xff;
  181. if (!(alen | length))
  182. a |= LPC32XX_I2C_TX_STOP;
  183. /* Send address byte */
  184. writel(a, &base->tx);
  185. }
  186. }
  187. while (length) {
  188. /* wait for transmit fifo not full */
  189. stat = readl(&base->stat);
  190. if (!(stat & LPC32XX_I2C_STAT_TFF)) {
  191. /* compute data byte, add stop if length==0 */
  192. length--;
  193. int d = *(data++);
  194. if (!length)
  195. d |= LPC32XX_I2C_TX_STOP;
  196. /* Send data byte */
  197. writel(d, &base->tx);
  198. }
  199. }
  200. /* wait for end of transation */
  201. while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
  202. ;
  203. /* clear end-of-transaction flag */
  204. writel(1, &base->stat);
  205. return 0;
  206. }
  207. #ifndef CONFIG_DM_I2C
  208. static void lpc32xx_i2c_init(struct i2c_adapter *adap,
  209. int requested_speed, int slaveadd)
  210. {
  211. __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
  212. adap->hwadapnr);
  213. }
  214. static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
  215. {
  216. return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
  217. }
  218. static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
  219. int alen, u8 *data, int length)
  220. {
  221. return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
  222. alen, data, length);
  223. }
  224. static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
  225. int alen, u8 *data, int length)
  226. {
  227. return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
  228. alen, data, length);
  229. }
  230. static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
  231. unsigned int speed)
  232. {
  233. return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
  234. adap->hwadapnr);
  235. }
  236. U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
  237. lpc32xx_i2c_read, lpc32xx_i2c_write,
  238. lpc32xx_i2c_set_bus_speed,
  239. CONFIG_SYS_I2C_LPC32XX_SPEED,
  240. CONFIG_SYS_I2C_LPC32XX_SLAVE,
  241. 0)
  242. U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
  243. lpc32xx_i2c_read, lpc32xx_i2c_write,
  244. lpc32xx_i2c_set_bus_speed,
  245. CONFIG_SYS_I2C_LPC32XX_SPEED,
  246. CONFIG_SYS_I2C_LPC32XX_SLAVE,
  247. 1)
  248. U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
  249. lpc32xx_i2c_read, lpc32xx_i2c_write,
  250. lpc32xx_i2c_set_bus_speed,
  251. 100000,
  252. 0,
  253. 2)
  254. #else /* CONFIG_DM_I2C */
  255. static int lpc32xx_i2c_probe(struct udevice *bus)
  256. {
  257. struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
  258. /*
  259. * FIXME: This is not permitted
  260. * dev_seq(bus) = dev->index;
  261. */
  262. __i2c_init(dev->base, dev->speed, 0, dev->index);
  263. return 0;
  264. }
  265. static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  266. u32 chip_flags)
  267. {
  268. struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
  269. return __i2c_probe_chip(dev->base, chip_addr);
  270. }
  271. static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  272. int nmsgs)
  273. {
  274. struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
  275. struct i2c_msg *dmsg, *omsg, dummy;
  276. uint i = 0, address = 0;
  277. memset(&dummy, 0, sizeof(struct i2c_msg));
  278. /* We expect either two messages (one with an offset and one with the
  279. * actual data) or one message (just data)
  280. */
  281. if (nmsgs > 2 || nmsgs == 0) {
  282. debug("%s: Only one or two messages are supported.", __func__);
  283. return -1;
  284. }
  285. omsg = nmsgs == 1 ? &dummy : msg;
  286. dmsg = nmsgs == 1 ? msg : msg + 1;
  287. /* the address is expected to be a uint, not a array. */
  288. address = omsg->buf[0];
  289. for (i = 1; i < omsg->len; i++)
  290. address = (address << 8) + omsg->buf[i];
  291. if (dmsg->flags & I2C_M_RD)
  292. return __i2c_read(dev->base, dmsg->addr, address,
  293. omsg->len, dmsg->buf, dmsg->len);
  294. else
  295. return __i2c_write(dev->base, dmsg->addr, address,
  296. omsg->len, dmsg->buf, dmsg->len);
  297. }
  298. static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  299. {
  300. struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
  301. return __i2c_set_bus_speed(dev->base, speed, dev->index);
  302. }
  303. static int lpc32xx_i2c_reset(struct udevice *bus)
  304. {
  305. struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
  306. __i2c_init(dev->base, dev->speed, 0, dev->index);
  307. return 0;
  308. }
  309. static const struct dm_i2c_ops lpc32xx_i2c_ops = {
  310. .xfer = lpc32xx_i2c_xfer,
  311. .probe_chip = lpc32xx_i2c_probe_chip,
  312. .deblock = lpc32xx_i2c_reset,
  313. .set_bus_speed = lpc32xx_i2c_set_bus_speed,
  314. };
  315. U_BOOT_DRIVER(i2c_lpc32xx) = {
  316. .id = UCLASS_I2C,
  317. .name = "i2c_lpc32xx",
  318. .probe = lpc32xx_i2c_probe,
  319. .ops = &lpc32xx_i2c_ops,
  320. };
  321. #endif /* CONFIG_DM_I2C */