exynos_hs_i2c.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016, Google Inc
  4. *
  5. * (C) Copyright 2002
  6. * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <i2c.h>
  11. #include <log.h>
  12. #include <asm/arch/clk.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/pinmux.h>
  15. #include <linux/delay.h>
  16. #include "s3c24x0_i2c.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /* HSI2C-specific register description */
  19. /* I2C_CTL Register bits */
  20. #define HSI2C_FUNC_MODE_I2C (1u << 0)
  21. #define HSI2C_MASTER (1u << 3)
  22. #define HSI2C_RXCHON (1u << 6) /* Write/Send */
  23. #define HSI2C_TXCHON (1u << 7) /* Read/Receive */
  24. #define HSI2C_SW_RST (1u << 31)
  25. /* I2C_FIFO_CTL Register bits */
  26. #define HSI2C_RXFIFO_EN (1u << 0)
  27. #define HSI2C_TXFIFO_EN (1u << 1)
  28. #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
  29. #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
  30. /* I2C_TRAILING_CTL Register bits */
  31. #define HSI2C_TRAILING_COUNT (0xff)
  32. /* I2C_INT_EN Register bits */
  33. #define HSI2C_TX_UNDERRUN_EN (1u << 2)
  34. #define HSI2C_TX_OVERRUN_EN (1u << 3)
  35. #define HSI2C_RX_UNDERRUN_EN (1u << 4)
  36. #define HSI2C_RX_OVERRUN_EN (1u << 5)
  37. #define HSI2C_INT_TRAILING_EN (1u << 6)
  38. #define HSI2C_INT_I2C_EN (1u << 9)
  39. #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\
  40. HSI2C_TX_OVERRUN_EN |\
  41. HSI2C_RX_UNDERRUN_EN |\
  42. HSI2C_RX_OVERRUN_EN |\
  43. HSI2C_INT_TRAILING_EN)
  44. /* I2C_CONF Register bits */
  45. #define HSI2C_AUTO_MODE (1u << 31)
  46. #define HSI2C_10BIT_ADDR_MODE (1u << 30)
  47. #define HSI2C_HS_MODE (1u << 29)
  48. /* I2C_AUTO_CONF Register bits */
  49. #define HSI2C_READ_WRITE (1u << 16)
  50. #define HSI2C_STOP_AFTER_TRANS (1u << 17)
  51. #define HSI2C_MASTER_RUN (1u << 31)
  52. /* I2C_TIMEOUT Register bits */
  53. #define HSI2C_TIMEOUT_EN (1u << 31)
  54. /* I2C_TRANS_STATUS register bits */
  55. #define HSI2C_MASTER_BUSY (1u << 17)
  56. #define HSI2C_SLAVE_BUSY (1u << 16)
  57. #define HSI2C_TIMEOUT_AUTO (1u << 4)
  58. #define HSI2C_NO_DEV (1u << 3)
  59. #define HSI2C_NO_DEV_ACK (1u << 2)
  60. #define HSI2C_TRANS_ABORT (1u << 1)
  61. #define HSI2C_TRANS_SUCCESS (1u << 0)
  62. #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\
  63. HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
  64. HSI2C_TRANS_ABORT)
  65. #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
  66. /* I2C_FIFO_STAT Register bits */
  67. #define HSI2C_RX_FIFO_EMPTY (1u << 24)
  68. #define HSI2C_RX_FIFO_FULL (1u << 23)
  69. #define HSI2C_TX_FIFO_EMPTY (1u << 8)
  70. #define HSI2C_TX_FIFO_FULL (1u << 7)
  71. #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f)
  72. #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f)
  73. #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
  74. #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
  75. /*
  76. * Wait for transfer completion.
  77. *
  78. * This function reads the interrupt status register waiting for the INT_I2C
  79. * bit to be set, which indicates copletion of a transaction.
  80. *
  81. * @param i2c: pointer to the appropriate register bank
  82. *
  83. * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
  84. * the status bits do not get set in time, or an approrpiate error
  85. * value in case of transfer errors.
  86. */
  87. static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
  88. {
  89. int i = HSI2C_TIMEOUT_US;
  90. while (i-- > 0) {
  91. u32 int_status = readl(&i2c->usi_int_stat);
  92. if (int_status & HSI2C_INT_I2C_EN) {
  93. u32 trans_status = readl(&i2c->usi_trans_status);
  94. /* Deassert pending interrupt. */
  95. writel(int_status, &i2c->usi_int_stat);
  96. if (trans_status & HSI2C_NO_DEV_ACK) {
  97. debug("%s: no ACK from device\n", __func__);
  98. return I2C_NACK;
  99. }
  100. if (trans_status & HSI2C_NO_DEV) {
  101. debug("%s: no device\n", __func__);
  102. return I2C_NOK;
  103. }
  104. if (trans_status & HSI2C_TRANS_ABORT) {
  105. debug("%s: arbitration lost\n", __func__);
  106. return I2C_NOK_LA;
  107. }
  108. if (trans_status & HSI2C_TIMEOUT_AUTO) {
  109. debug("%s: device timed out\n", __func__);
  110. return I2C_NOK_TOUT;
  111. }
  112. return I2C_OK;
  113. }
  114. udelay(1);
  115. }
  116. debug("%s: transaction timeout!\n", __func__);
  117. return I2C_NOK_TOUT;
  118. }
  119. static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
  120. {
  121. struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
  122. ulong clkin;
  123. unsigned int op_clk = i2c_bus->clock_frequency;
  124. unsigned int i = 0, utemp0 = 0, utemp1 = 0;
  125. unsigned int t_ftl_cycle;
  126. #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  127. clkin = get_i2c_clk();
  128. #else
  129. clkin = get_PCLK();
  130. #endif
  131. /* FPCLK / FI2C =
  132. * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
  133. * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
  134. * uTemp1 = (TSCLK_L + TSCLK_H + 2)
  135. * uTemp2 = TSCLK_L + TSCLK_H
  136. */
  137. t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
  138. utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
  139. /* CLK_DIV max is 256 */
  140. for (i = 0; i < 256; i++) {
  141. utemp1 = utemp0 / (i + 1);
  142. if ((utemp1 < 512) && (utemp1 > 4)) {
  143. i2c_bus->clk_cycle = utemp1 - 2;
  144. i2c_bus->clk_div = i;
  145. return 0;
  146. }
  147. }
  148. return -EINVAL;
  149. }
  150. static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
  151. {
  152. struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
  153. unsigned int t_sr_release;
  154. unsigned int n_clkdiv;
  155. unsigned int t_start_su, t_start_hd;
  156. unsigned int t_stop_su;
  157. unsigned int t_data_su, t_data_hd;
  158. unsigned int t_scl_l, t_scl_h;
  159. u32 i2c_timing_s1;
  160. u32 i2c_timing_s2;
  161. u32 i2c_timing_s3;
  162. u32 i2c_timing_sla;
  163. n_clkdiv = i2c_bus->clk_div;
  164. t_scl_l = i2c_bus->clk_cycle / 2;
  165. t_scl_h = i2c_bus->clk_cycle / 2;
  166. t_start_su = t_scl_l;
  167. t_start_hd = t_scl_l;
  168. t_stop_su = t_scl_l;
  169. t_data_su = t_scl_l / 2;
  170. t_data_hd = t_scl_l / 2;
  171. t_sr_release = i2c_bus->clk_cycle;
  172. i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
  173. i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
  174. i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
  175. i2c_timing_sla = t_data_hd << 0;
  176. writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
  177. /* Clear to enable Timeout */
  178. clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
  179. /* set AUTO mode */
  180. writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
  181. /* Enable completion conditions' reporting. */
  182. writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
  183. /* Enable FIFOs */
  184. writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
  185. /* Currently operating in Fast speed mode. */
  186. writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
  187. writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
  188. writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
  189. writel(i2c_timing_sla, &hsregs->usi_timing_sla);
  190. }
  191. /* SW reset for the high speed bus */
  192. static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
  193. {
  194. struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
  195. u32 i2c_ctl;
  196. /* Set and clear the bit for reset */
  197. i2c_ctl = readl(&i2c->usi_ctl);
  198. i2c_ctl |= HSI2C_SW_RST;
  199. writel(i2c_ctl, &i2c->usi_ctl);
  200. i2c_ctl = readl(&i2c->usi_ctl);
  201. i2c_ctl &= ~HSI2C_SW_RST;
  202. writel(i2c_ctl, &i2c->usi_ctl);
  203. /* Initialize the configure registers */
  204. hsi2c_ch_init(i2c_bus);
  205. }
  206. /*
  207. * Poll the appropriate bit of the fifo status register until the interface is
  208. * ready to process the next byte or timeout expires.
  209. *
  210. * In addition to the FIFO status register this function also polls the
  211. * interrupt status register to be able to detect unexpected transaction
  212. * completion.
  213. *
  214. * When FIFO is ready to process the next byte, this function returns I2C_OK.
  215. * If in course of polling the INT_I2C assertion is detected, the function
  216. * returns I2C_NOK. If timeout happens before any of the above conditions is
  217. * met - the function returns I2C_NOK_TOUT;
  218. * @param i2c: pointer to the appropriate i2c register bank.
  219. * @param rx_transfer: set to True if the receive transaction is in progress.
  220. * @return: as described above.
  221. */
  222. static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
  223. {
  224. u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
  225. int i = HSI2C_TIMEOUT_US;
  226. while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
  227. if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
  228. /*
  229. * There is a chance that assertion of
  230. * HSI2C_INT_I2C_EN and deassertion of
  231. * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
  232. * give FIFO status priority and check it one more
  233. * time before reporting interrupt. The interrupt will
  234. * be reported next time this function is called.
  235. */
  236. if (rx_transfer &&
  237. !(readl(&i2c->usi_fifo_stat) & fifo_bit))
  238. break;
  239. return I2C_NOK;
  240. }
  241. if (!i--) {
  242. debug("%s: FIFO polling timeout!\n", __func__);
  243. return I2C_NOK_TOUT;
  244. }
  245. udelay(1);
  246. }
  247. return I2C_OK;
  248. }
  249. /*
  250. * Preapre hsi2c transaction, either read or write.
  251. *
  252. * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
  253. * the 5420 UM.
  254. *
  255. * @param i2c: pointer to the appropriate i2c register bank.
  256. * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
  257. * @param len: number of bytes expected to be sent or received
  258. * @param rx_transfer: set to true for receive transactions
  259. * @param: issue_stop: set to true if i2c stop condition should be generated
  260. * after this transaction.
  261. * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
  262. * I2C_OK otherwise.
  263. */
  264. static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
  265. u8 chip,
  266. u16 len,
  267. bool rx_transfer,
  268. bool issue_stop)
  269. {
  270. u32 conf;
  271. conf = len | HSI2C_MASTER_RUN;
  272. if (issue_stop)
  273. conf |= HSI2C_STOP_AFTER_TRANS;
  274. /* Clear to enable Timeout */
  275. writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
  276. /* Set slave address */
  277. writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
  278. if (rx_transfer) {
  279. /* i2c master, read transaction */
  280. writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
  281. &i2c->usi_ctl);
  282. /* read up to len bytes, stop after transaction is finished */
  283. writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
  284. } else {
  285. /* i2c master, write transaction */
  286. writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
  287. &i2c->usi_ctl);
  288. /* write up to len bytes, stop after transaction is finished */
  289. writel(conf, &i2c->usi_auto_conf);
  290. }
  291. /* Reset all pending interrupt status bits we care about, if any */
  292. writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
  293. return I2C_OK;
  294. }
  295. /*
  296. * Wait while i2c bus is settling down (mostly stop gets completed).
  297. */
  298. static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
  299. {
  300. int i = HSI2C_TIMEOUT_US;
  301. while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
  302. if (!i--) {
  303. debug("%s: bus busy\n", __func__);
  304. return I2C_NOK_TOUT;
  305. }
  306. udelay(1);
  307. }
  308. return I2C_OK;
  309. }
  310. static int hsi2c_write(struct exynos5_hsi2c *i2c,
  311. unsigned char chip,
  312. unsigned char addr[],
  313. unsigned char alen,
  314. unsigned char data[],
  315. unsigned short len,
  316. bool issue_stop)
  317. {
  318. int i, rv = 0;
  319. if (!(len + alen)) {
  320. /* Writes of zero length not supported in auto mode. */
  321. debug("%s: zero length writes not supported\n", __func__);
  322. return I2C_NOK;
  323. }
  324. rv = hsi2c_prepare_transaction
  325. (i2c, chip, len + alen, false, issue_stop);
  326. if (rv != I2C_OK)
  327. return rv;
  328. /* Move address, if any, and the data, if any, into the FIFO. */
  329. for (i = 0; i < alen; i++) {
  330. rv = hsi2c_poll_fifo(i2c, false);
  331. if (rv != I2C_OK) {
  332. debug("%s: address write failed\n", __func__);
  333. goto write_error;
  334. }
  335. writel(addr[i], &i2c->usi_txdata);
  336. }
  337. for (i = 0; i < len; i++) {
  338. rv = hsi2c_poll_fifo(i2c, false);
  339. if (rv != I2C_OK) {
  340. debug("%s: data write failed\n", __func__);
  341. goto write_error;
  342. }
  343. writel(data[i], &i2c->usi_txdata);
  344. }
  345. rv = hsi2c_wait_for_trx(i2c);
  346. write_error:
  347. if (issue_stop) {
  348. int tmp_ret = hsi2c_wait_while_busy(i2c);
  349. if (rv == I2C_OK)
  350. rv = tmp_ret;
  351. }
  352. writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
  353. return rv;
  354. }
  355. static int hsi2c_read(struct exynos5_hsi2c *i2c,
  356. unsigned char chip,
  357. unsigned char addr[],
  358. unsigned char alen,
  359. unsigned char data[],
  360. unsigned short len)
  361. {
  362. int i, rv, tmp_ret;
  363. bool drop_data = false;
  364. if (!len) {
  365. /* Reads of zero length not supported in auto mode. */
  366. debug("%s: zero length read adjusted\n", __func__);
  367. drop_data = true;
  368. len = 1;
  369. }
  370. if (alen) {
  371. /* Internal register adress needs to be written first. */
  372. rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
  373. if (rv != I2C_OK)
  374. return rv;
  375. }
  376. rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
  377. if (rv != I2C_OK)
  378. return rv;
  379. for (i = 0; i < len; i++) {
  380. rv = hsi2c_poll_fifo(i2c, true);
  381. if (rv != I2C_OK)
  382. goto read_err;
  383. if (drop_data)
  384. continue;
  385. data[i] = readl(&i2c->usi_rxdata);
  386. }
  387. rv = hsi2c_wait_for_trx(i2c);
  388. read_err:
  389. tmp_ret = hsi2c_wait_while_busy(i2c);
  390. if (rv == I2C_OK)
  391. rv = tmp_ret;
  392. writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
  393. return rv;
  394. }
  395. static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
  396. int nmsgs)
  397. {
  398. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  399. struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
  400. int ret;
  401. for (; nmsgs > 0; nmsgs--, msg++) {
  402. if (msg->flags & I2C_M_RD) {
  403. ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
  404. msg->len);
  405. } else {
  406. ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
  407. msg->len, true);
  408. }
  409. if (ret) {
  410. exynos5_i2c_reset(i2c_bus);
  411. return -EREMOTEIO;
  412. }
  413. }
  414. return 0;
  415. }
  416. static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  417. {
  418. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  419. i2c_bus->clock_frequency = speed;
  420. if (hsi2c_get_clk_details(i2c_bus))
  421. return -EFAULT;
  422. hsi2c_ch_init(i2c_bus);
  423. return 0;
  424. }
  425. static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
  426. {
  427. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  428. uchar buf[1];
  429. int ret;
  430. buf[0] = 0;
  431. /*
  432. * What is needed is to send the chip address and verify that the
  433. * address was <ACK>ed (i.e. there was a chip at that address which
  434. * drove the data line low).
  435. */
  436. ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1);
  437. return ret != I2C_OK;
  438. }
  439. static int s3c_i2c_of_to_plat(struct udevice *dev)
  440. {
  441. const void *blob = gd->fdt_blob;
  442. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  443. int node;
  444. node = dev_of_offset(dev);
  445. i2c_bus->hsregs = dev_read_addr_ptr(dev);
  446. i2c_bus->id = pinmux_decode_periph_id(blob, node);
  447. i2c_bus->clock_frequency =
  448. dev_read_u32_default(dev, "clock-frequency",
  449. I2C_SPEED_STANDARD_RATE);
  450. i2c_bus->node = node;
  451. i2c_bus->bus_num = dev_seq(dev);
  452. exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE);
  453. i2c_bus->active = true;
  454. return 0;
  455. }
  456. static const struct dm_i2c_ops exynos_hs_i2c_ops = {
  457. .xfer = exynos_hs_i2c_xfer,
  458. .probe_chip = s3c24x0_i2c_probe,
  459. .set_bus_speed = s3c24x0_i2c_set_bus_speed,
  460. };
  461. static const struct udevice_id exynos_hs_i2c_ids[] = {
  462. { .compatible = "samsung,exynos5-hsi2c" },
  463. { }
  464. };
  465. U_BOOT_DRIVER(hs_i2c) = {
  466. .name = "i2c_s3c_hs",
  467. .id = UCLASS_I2C,
  468. .of_match = exynos_hs_i2c_ids,
  469. .of_to_plat = s3c_i2c_of_to_plat,
  470. .priv_auto = sizeof(struct s3c24x0_i2c_bus),
  471. .ops = &exynos_hs_i2c_ops,
  472. };