davinci_i2c.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI DaVinci (TMS320DM644x) I2C driver.
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
  8. * --------------------------------------------------------
  9. *
  10. * NOTE: This driver should be converted to driver model before June 2017.
  11. * Please see doc/driver-model/i2c-howto.rst for instructions.
  12. */
  13. #include <common.h>
  14. #include <i2c.h>
  15. #include <dm.h>
  16. #include <log.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/i2c_defs.h>
  19. #include <asm/io.h>
  20. #include <linux/delay.h>
  21. #include "davinci_i2c.h"
  22. #ifdef CONFIG_DM_I2C
  23. /* Information about i2c controller */
  24. struct i2c_bus {
  25. int id;
  26. uint speed;
  27. struct i2c_regs *regs;
  28. };
  29. #endif
  30. #define CHECK_NACK() \
  31. do {\
  32. if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
  33. REG(&(i2c_base->i2c_con)) = 0;\
  34. return 1;\
  35. } \
  36. } while (0)
  37. static int _wait_for_bus(struct i2c_regs *i2c_base)
  38. {
  39. int stat, timeout;
  40. REG(&(i2c_base->i2c_stat)) = 0xffff;
  41. for (timeout = 0; timeout < 10; timeout++) {
  42. stat = REG(&(i2c_base->i2c_stat));
  43. if (!((stat) & I2C_STAT_BB)) {
  44. REG(&(i2c_base->i2c_stat)) = 0xffff;
  45. return 0;
  46. }
  47. REG(&(i2c_base->i2c_stat)) = stat;
  48. udelay(50000);
  49. }
  50. REG(&(i2c_base->i2c_stat)) = 0xffff;
  51. return 1;
  52. }
  53. static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask)
  54. {
  55. int stat, timeout;
  56. for (timeout = 0; timeout < 10; timeout++) {
  57. udelay(1000);
  58. stat = REG(&(i2c_base->i2c_stat));
  59. if (stat & mask)
  60. return stat;
  61. }
  62. REG(&(i2c_base->i2c_stat)) = 0xffff;
  63. return stat | I2C_TIMEOUT;
  64. }
  65. static void _flush_rx(struct i2c_regs *i2c_base)
  66. {
  67. while (1) {
  68. if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
  69. break;
  70. REG(&(i2c_base->i2c_drr));
  71. REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
  72. udelay(1000);
  73. }
  74. }
  75. static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base,
  76. uint speed)
  77. {
  78. uint32_t div, psc;
  79. psc = 2;
  80. /* SCLL + SCLH */
  81. div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
  82. REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
  83. REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
  84. REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
  85. return 0;
  86. }
  87. static void _davinci_i2c_init(struct i2c_regs *i2c_base,
  88. uint speed, int slaveadd)
  89. {
  90. if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
  91. REG(&(i2c_base->i2c_con)) = 0;
  92. udelay(50000);
  93. }
  94. _davinci_i2c_setspeed(i2c_base, speed);
  95. REG(&(i2c_base->i2c_oa)) = slaveadd;
  96. REG(&(i2c_base->i2c_cnt)) = 0;
  97. /* Interrupts must be enabled or I2C module won't work */
  98. REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
  99. I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
  100. /* Now enable I2C controller (get it out of reset) */
  101. REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
  102. udelay(1000);
  103. }
  104. static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip,
  105. uint32_t addr, int alen, uint8_t *buf, int len)
  106. {
  107. uint32_t tmp;
  108. int i;
  109. if ((alen < 0) || (alen > 2)) {
  110. printf("%s(): bogus address length %x\n", __func__, alen);
  111. return 1;
  112. }
  113. if (_wait_for_bus(i2c_base))
  114. return 1;
  115. if (alen != 0) {
  116. /* Start address phase */
  117. tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
  118. REG(&(i2c_base->i2c_cnt)) = alen;
  119. REG(&(i2c_base->i2c_sa)) = chip;
  120. REG(&(i2c_base->i2c_con)) = tmp;
  121. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
  122. CHECK_NACK();
  123. switch (alen) {
  124. case 2:
  125. /* Send address MSByte */
  126. if (tmp & I2C_STAT_XRDY) {
  127. REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
  128. } else {
  129. REG(&(i2c_base->i2c_con)) = 0;
  130. return 1;
  131. }
  132. tmp = _poll_i2c_irq(i2c_base,
  133. I2C_STAT_XRDY | I2C_STAT_NACK);
  134. CHECK_NACK();
  135. /* No break, fall through */
  136. case 1:
  137. /* Send address LSByte */
  138. if (tmp & I2C_STAT_XRDY) {
  139. REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
  140. } else {
  141. REG(&(i2c_base->i2c_con)) = 0;
  142. return 1;
  143. }
  144. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY |
  145. I2C_STAT_NACK | I2C_STAT_ARDY);
  146. CHECK_NACK();
  147. if (!(tmp & I2C_STAT_ARDY)) {
  148. REG(&(i2c_base->i2c_con)) = 0;
  149. return 1;
  150. }
  151. }
  152. }
  153. /* Address phase is over, now read 'len' bytes and stop */
  154. tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
  155. REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
  156. REG(&(i2c_base->i2c_sa)) = chip;
  157. REG(&(i2c_base->i2c_con)) = tmp;
  158. for (i = 0; i < len; i++) {
  159. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_RRDY | I2C_STAT_NACK |
  160. I2C_STAT_ROVR);
  161. CHECK_NACK();
  162. if (tmp & I2C_STAT_RRDY) {
  163. buf[i] = REG(&(i2c_base->i2c_drr));
  164. } else {
  165. REG(&(i2c_base->i2c_con)) = 0;
  166. return 1;
  167. }
  168. }
  169. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
  170. CHECK_NACK();
  171. if (!(tmp & I2C_STAT_SCD)) {
  172. REG(&(i2c_base->i2c_con)) = 0;
  173. return 1;
  174. }
  175. _flush_rx(i2c_base);
  176. REG(&(i2c_base->i2c_stat)) = 0xffff;
  177. REG(&(i2c_base->i2c_cnt)) = 0;
  178. REG(&(i2c_base->i2c_con)) = 0;
  179. return 0;
  180. }
  181. static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip,
  182. uint32_t addr, int alen, uint8_t *buf, int len)
  183. {
  184. uint32_t tmp;
  185. int i;
  186. if ((alen < 0) || (alen > 2)) {
  187. printf("%s(): bogus address length %x\n", __func__, alen);
  188. return 1;
  189. }
  190. if (len < 0) {
  191. printf("%s(): bogus length %x\n", __func__, len);
  192. return 1;
  193. }
  194. if (_wait_for_bus(i2c_base))
  195. return 1;
  196. /* Start address phase */
  197. tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
  198. I2C_CON_TRX | I2C_CON_STP;
  199. REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
  200. len & 0xffff : (len & 0xffff) + alen;
  201. REG(&(i2c_base->i2c_sa)) = chip;
  202. REG(&(i2c_base->i2c_con)) = tmp;
  203. switch (alen) {
  204. case 2:
  205. /* Send address MSByte */
  206. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
  207. CHECK_NACK();
  208. if (tmp & I2C_STAT_XRDY) {
  209. REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
  210. } else {
  211. REG(&(i2c_base->i2c_con)) = 0;
  212. return 1;
  213. }
  214. /* No break, fall through */
  215. case 1:
  216. /* Send address LSByte */
  217. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
  218. CHECK_NACK();
  219. if (tmp & I2C_STAT_XRDY) {
  220. REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
  221. } else {
  222. REG(&(i2c_base->i2c_con)) = 0;
  223. return 1;
  224. }
  225. }
  226. for (i = 0; i < len; i++) {
  227. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
  228. CHECK_NACK();
  229. if (tmp & I2C_STAT_XRDY)
  230. REG(&(i2c_base->i2c_dxr)) = buf[i];
  231. else
  232. return 1;
  233. }
  234. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
  235. CHECK_NACK();
  236. if (!(tmp & I2C_STAT_SCD)) {
  237. REG(&(i2c_base->i2c_con)) = 0;
  238. return 1;
  239. }
  240. _flush_rx(i2c_base);
  241. REG(&(i2c_base->i2c_stat)) = 0xffff;
  242. REG(&(i2c_base->i2c_cnt)) = 0;
  243. REG(&(i2c_base->i2c_con)) = 0;
  244. return 0;
  245. }
  246. static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
  247. {
  248. int rc = 1;
  249. if (chip == REG(&(i2c_base->i2c_oa)))
  250. return rc;
  251. REG(&(i2c_base->i2c_con)) = 0;
  252. if (_wait_for_bus(i2c_base))
  253. return 1;
  254. /* try to read one byte from current (or only) address */
  255. REG(&(i2c_base->i2c_cnt)) = 1;
  256. REG(&(i2c_base->i2c_sa)) = chip;
  257. REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
  258. I2C_CON_STP);
  259. udelay(50000);
  260. if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
  261. rc = 0;
  262. _flush_rx(i2c_base);
  263. REG(&(i2c_base->i2c_stat)) = 0xffff;
  264. } else {
  265. REG(&(i2c_base->i2c_stat)) = 0xffff;
  266. REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
  267. udelay(20000);
  268. if (_wait_for_bus(i2c_base))
  269. return 1;
  270. }
  271. _flush_rx(i2c_base);
  272. REG(&(i2c_base->i2c_stat)) = 0xffff;
  273. REG(&(i2c_base->i2c_cnt)) = 0;
  274. return rc;
  275. }
  276. #ifndef CONFIG_DM_I2C
  277. static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
  278. {
  279. switch (adap->hwadapnr) {
  280. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  281. case 2:
  282. return (struct i2c_regs *)I2C2_BASE;
  283. #endif
  284. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  285. case 1:
  286. return (struct i2c_regs *)I2C1_BASE;
  287. #endif
  288. case 0:
  289. return (struct i2c_regs *)I2C_BASE;
  290. default:
  291. printf("wrong hwadapnr: %d\n", adap->hwadapnr);
  292. }
  293. return NULL;
  294. }
  295. static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
  296. {
  297. struct i2c_regs *i2c_base = davinci_get_base(adap);
  298. uint ret;
  299. adap->speed = speed;
  300. ret = _davinci_i2c_setspeed(i2c_base, speed);
  301. return ret;
  302. }
  303. static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
  304. int slaveadd)
  305. {
  306. struct i2c_regs *i2c_base = davinci_get_base(adap);
  307. adap->speed = speed;
  308. _davinci_i2c_init(i2c_base, speed, slaveadd);
  309. return;
  310. }
  311. static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  312. uint32_t addr, int alen, uint8_t *buf, int len)
  313. {
  314. struct i2c_regs *i2c_base = davinci_get_base(adap);
  315. return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
  316. }
  317. static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
  318. uint32_t addr, int alen, uint8_t *buf, int len)
  319. {
  320. struct i2c_regs *i2c_base = davinci_get_base(adap);
  321. return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
  322. }
  323. static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
  324. {
  325. struct i2c_regs *i2c_base = davinci_get_base(adap);
  326. return _davinci_i2c_probe_chip(i2c_base, chip);
  327. }
  328. U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
  329. davinci_i2c_read, davinci_i2c_write,
  330. davinci_i2c_setspeed,
  331. CONFIG_SYS_DAVINCI_I2C_SPEED,
  332. CONFIG_SYS_DAVINCI_I2C_SLAVE,
  333. 0)
  334. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  335. U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
  336. davinci_i2c_read, davinci_i2c_write,
  337. davinci_i2c_setspeed,
  338. CONFIG_SYS_DAVINCI_I2C_SPEED1,
  339. CONFIG_SYS_DAVINCI_I2C_SLAVE1,
  340. 1)
  341. #endif
  342. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  343. U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
  344. davinci_i2c_read, davinci_i2c_write,
  345. davinci_i2c_setspeed,
  346. CONFIG_SYS_DAVINCI_I2C_SPEED2,
  347. CONFIG_SYS_DAVINCI_I2C_SLAVE2,
  348. 2)
  349. #endif
  350. #else /* CONFIG_DM_I2C */
  351. static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  352. int nmsgs)
  353. {
  354. struct i2c_bus *i2c_bus = dev_get_priv(bus);
  355. int ret;
  356. debug("i2c_xfer: %d messages\n", nmsgs);
  357. for (; nmsgs > 0; nmsgs--, msg++) {
  358. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  359. if (msg->flags & I2C_M_RD) {
  360. ret = _davinci_i2c_read(i2c_bus->regs, msg->addr,
  361. 0, 0, msg->buf, msg->len);
  362. } else {
  363. ret = _davinci_i2c_write(i2c_bus->regs, msg->addr,
  364. 0, 0, msg->buf, msg->len);
  365. }
  366. if (ret) {
  367. debug("i2c_write: error sending\n");
  368. return -EREMOTEIO;
  369. }
  370. }
  371. return ret;
  372. }
  373. static int davinci_i2c_set_speed(struct udevice *dev, uint speed)
  374. {
  375. struct i2c_bus *i2c_bus = dev_get_priv(dev);
  376. i2c_bus->speed = speed;
  377. return _davinci_i2c_setspeed(i2c_bus->regs, speed);
  378. }
  379. static int davinci_i2c_probe(struct udevice *dev)
  380. {
  381. struct i2c_bus *i2c_bus = dev_get_priv(dev);
  382. i2c_bus->id = dev_seq(dev);
  383. i2c_bus->regs = dev_read_addr_ptr(dev);
  384. i2c_bus->speed = 100000;
  385. _davinci_i2c_init(i2c_bus->regs, i2c_bus->speed, 0);
  386. return 0;
  387. }
  388. static int davinci_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  389. uint chip_flags)
  390. {
  391. struct i2c_bus *i2c_bus = dev_get_priv(bus);
  392. return _davinci_i2c_probe_chip(i2c_bus->regs, chip_addr);
  393. }
  394. static const struct dm_i2c_ops davinci_i2c_ops = {
  395. .xfer = davinci_i2c_xfer,
  396. .probe_chip = davinci_i2c_probe_chip,
  397. .set_bus_speed = davinci_i2c_set_speed,
  398. };
  399. static const struct udevice_id davinci_i2c_ids[] = {
  400. { .compatible = "ti,davinci-i2c"},
  401. { .compatible = "ti,keystone-i2c"},
  402. { }
  403. };
  404. U_BOOT_DRIVER(i2c_davinci) = {
  405. .name = "i2c_davinci",
  406. .id = UCLASS_I2C,
  407. .of_match = davinci_i2c_ids,
  408. .probe = davinci_i2c_probe,
  409. .priv_auto = sizeof(struct i2c_bus),
  410. .ops = &davinci_i2c_ops,
  411. };
  412. #endif /* CONFIG_DM_I2C */