board.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2018 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <env.h>
  9. #include <fdtdec.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <time.h>
  14. #include <asm/cache.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <dm/device.h>
  19. #include <dm/uclass.h>
  20. #include <versalpl.h>
  21. #include "../common/board.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #if defined(CONFIG_FPGA_VERSALPL)
  24. static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  25. #endif
  26. int board_init(void)
  27. {
  28. printf("EL Level:\tEL%d\n", current_el());
  29. #if defined(CONFIG_FPGA_VERSALPL)
  30. fpga_init();
  31. fpga_add(fpga_xilinx, &versalpl);
  32. #endif
  33. if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
  34. xilinx_read_eeprom();
  35. return 0;
  36. }
  37. int board_early_init_r(void)
  38. {
  39. u32 val;
  40. if (current_el() != 3)
  41. return 0;
  42. debug("iou_switch ctrl div0 %x\n",
  43. readl(&crlapb_base->iou_switch_ctrl));
  44. writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  45. (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  46. &crlapb_base->iou_switch_ctrl);
  47. /* Global timer init - Program time stamp reference clk */
  48. val = readl(&crlapb_base->timestamp_ref_ctrl);
  49. val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  50. writel(val, &crlapb_base->timestamp_ref_ctrl);
  51. debug("ref ctrl 0x%x\n",
  52. readl(&crlapb_base->timestamp_ref_ctrl));
  53. /* Clear reset of timestamp reg */
  54. writel(0, &crlapb_base->rst_timestamp);
  55. /*
  56. * Program freq register in System counter and
  57. * enable system counter.
  58. */
  59. writel(COUNTER_FREQUENCY,
  60. &iou_scntr_secure->base_frequency_id_register);
  61. debug("counter val 0x%x\n",
  62. readl(&iou_scntr_secure->base_frequency_id_register));
  63. writel(IOU_SCNTRS_CONTROL_EN,
  64. &iou_scntr_secure->counter_control_register);
  65. debug("scntrs control 0x%x\n",
  66. readl(&iou_scntr_secure->counter_control_register));
  67. debug("timer 0x%llx\n", get_ticks());
  68. debug("timer 0x%llx\n", get_ticks());
  69. return 0;
  70. }
  71. static u8 versal_get_bootmode(void)
  72. {
  73. u8 bootmode;
  74. u32 reg = 0;
  75. reg = readl(&crp_base->boot_mode_usr);
  76. if (reg >> BOOT_MODE_ALT_SHIFT)
  77. reg >>= BOOT_MODE_ALT_SHIFT;
  78. bootmode = reg & BOOT_MODES_MASK;
  79. return bootmode;
  80. }
  81. int board_late_init(void)
  82. {
  83. u8 bootmode;
  84. struct udevice *dev;
  85. int bootseq = -1;
  86. int bootseq_len = 0;
  87. int env_targets_len = 0;
  88. const char *mode;
  89. char *new_targets;
  90. char *env_targets;
  91. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  92. debug("Saved variables - Skipping\n");
  93. return 0;
  94. }
  95. if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
  96. return 0;
  97. bootmode = versal_get_bootmode();
  98. puts("Bootmode: ");
  99. switch (bootmode) {
  100. case USB_MODE:
  101. puts("USB_MODE\n");
  102. mode = "dfu_usb";
  103. break;
  104. case JTAG_MODE:
  105. puts("JTAG_MODE\n");
  106. mode = "jtag pxe dhcp";
  107. break;
  108. case QSPI_MODE_24BIT:
  109. puts("QSPI_MODE_24\n");
  110. mode = "xspi0";
  111. break;
  112. case QSPI_MODE_32BIT:
  113. puts("QSPI_MODE_32\n");
  114. mode = "xspi0";
  115. break;
  116. case OSPI_MODE:
  117. puts("OSPI_MODE\n");
  118. mode = "xspi0";
  119. break;
  120. case EMMC_MODE:
  121. puts("EMMC_MODE\n");
  122. if (uclass_get_device_by_name(UCLASS_MMC,
  123. "sdhci@f1050000", &dev)) {
  124. puts("Boot from EMMC but without SD1 enabled!\n");
  125. return -1;
  126. }
  127. debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
  128. mode = "mmc";
  129. bootseq = dev_seq(dev);
  130. break;
  131. case SD_MODE:
  132. puts("SD_MODE\n");
  133. if (uclass_get_device_by_name(UCLASS_MMC,
  134. "sdhci@f1040000", &dev)) {
  135. puts("Boot from SD0 but without SD0 enabled!\n");
  136. return -1;
  137. }
  138. debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
  139. mode = "mmc";
  140. bootseq = dev_seq(dev);
  141. break;
  142. case SD1_LSHFT_MODE:
  143. puts("LVL_SHFT_");
  144. /* fall through */
  145. case SD_MODE1:
  146. puts("SD_MODE1\n");
  147. if (uclass_get_device_by_name(UCLASS_MMC,
  148. "sdhci@f1050000", &dev)) {
  149. puts("Boot from SD1 but without SD1 enabled!\n");
  150. return -1;
  151. }
  152. debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
  153. mode = "mmc";
  154. bootseq = dev_seq(dev);
  155. break;
  156. default:
  157. mode = "";
  158. printf("Invalid Boot Mode:0x%x\n", bootmode);
  159. break;
  160. }
  161. if (bootseq >= 0) {
  162. bootseq_len = snprintf(NULL, 0, "%i", bootseq);
  163. debug("Bootseq len: %x\n", bootseq_len);
  164. }
  165. /*
  166. * One terminating char + one byte for space between mode
  167. * and default boot_targets
  168. */
  169. env_targets = env_get("boot_targets");
  170. if (env_targets)
  171. env_targets_len = strlen(env_targets);
  172. new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
  173. bootseq_len);
  174. if (!new_targets)
  175. return -ENOMEM;
  176. if (bootseq >= 0)
  177. sprintf(new_targets, "%s%x %s", mode, bootseq,
  178. env_targets ? env_targets : "");
  179. else
  180. sprintf(new_targets, "%s %s", mode,
  181. env_targets ? env_targets : "");
  182. env_set("boot_targets", new_targets);
  183. return board_late_init_xilinx();
  184. }
  185. int dram_init_banksize(void)
  186. {
  187. int ret;
  188. ret = fdtdec_setup_memory_banksize();
  189. if (ret)
  190. return ret;
  191. mem_map_fill();
  192. return 0;
  193. }
  194. int dram_init(void)
  195. {
  196. if (fdtdec_setup_mem_size_base_lowest() != 0)
  197. return -EINVAL;
  198. return 0;
  199. }
  200. void reset_cpu(ulong addr)
  201. {
  202. }