model_206ax.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * From Coreboot file of same name
  4. *
  5. * Copyright (C) 2007-2009 coresystems GmbH
  6. * Copyright (C) 2011 The Chromium Authors
  7. */
  8. #include <common.h>
  9. #include <cpu.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <asm/cpu.h>
  15. #include <asm/cpu_common.h>
  16. #include <asm/cpu_x86.h>
  17. #include <asm/msr.h>
  18. #include <asm/msr-index.h>
  19. #include <asm/mtrr.h>
  20. #include <asm/processor.h>
  21. #include <asm/speedstep.h>
  22. #include <asm/turbo.h>
  23. #include <asm/arch/model_206ax.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. static void enable_vmx(void)
  26. {
  27. struct cpuid_result regs;
  28. #ifdef CONFIG_ENABLE_VMX
  29. int enable = true;
  30. #else
  31. int enable = false;
  32. #endif
  33. msr_t msr;
  34. regs = cpuid(1);
  35. /* Check that the VMX is supported before reading or writing the MSR. */
  36. if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
  37. return;
  38. msr = msr_read(MSR_IA32_FEATURE_CONTROL);
  39. if (msr.lo & (1 << 0)) {
  40. debug("VMX is locked, so %s will do nothing\n", __func__);
  41. /* VMX locked. If we set it again we get an illegal
  42. * instruction
  43. */
  44. return;
  45. }
  46. /* The IA32_FEATURE_CONTROL MSR may initialize with random values.
  47. * It must be cleared regardless of VMX config setting.
  48. */
  49. msr.hi = 0;
  50. msr.lo = 0;
  51. debug("%s VMX\n", enable ? "Enabling" : "Disabling");
  52. /*
  53. * Even though the Intel manual says you must set the lock bit in
  54. * addition to the VMX bit in order for VMX to work, it is incorrect.
  55. * Thus we leave it unlocked for the OS to manage things itself.
  56. * This is good for a few reasons:
  57. * - No need to reflash the bios just to toggle the lock bit.
  58. * - The VMX bits really really should match each other across cores,
  59. * so hard locking it on one while another has the opposite setting
  60. * can easily lead to crashes as code using VMX migrates between
  61. * them.
  62. * - Vendors that want to "upsell" from a bios that disables+locks to
  63. * one that doesn't is sleazy.
  64. * By leaving this to the OS (e.g. Linux), people can do exactly what
  65. * they want on the fly, and do it correctly (e.g. across multiple
  66. * cores).
  67. */
  68. if (enable) {
  69. msr.lo |= (1 << 2);
  70. if (regs.ecx & CPUID_SMX)
  71. msr.lo |= (1 << 1);
  72. }
  73. msr_write(MSR_IA32_FEATURE_CONTROL, msr);
  74. }
  75. /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
  76. static const u8 power_limit_time_sec_to_msr[] = {
  77. [0] = 0x00,
  78. [1] = 0x0a,
  79. [2] = 0x0b,
  80. [3] = 0x4b,
  81. [4] = 0x0c,
  82. [5] = 0x2c,
  83. [6] = 0x4c,
  84. [7] = 0x6c,
  85. [8] = 0x0d,
  86. [10] = 0x2d,
  87. [12] = 0x4d,
  88. [14] = 0x6d,
  89. [16] = 0x0e,
  90. [20] = 0x2e,
  91. [24] = 0x4e,
  92. [28] = 0x6e,
  93. [32] = 0x0f,
  94. [40] = 0x2f,
  95. [48] = 0x4f,
  96. [56] = 0x6f,
  97. [64] = 0x10,
  98. [80] = 0x30,
  99. [96] = 0x50,
  100. [112] = 0x70,
  101. [128] = 0x11,
  102. };
  103. /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
  104. static const u8 power_limit_time_msr_to_sec[] = {
  105. [0x00] = 0,
  106. [0x0a] = 1,
  107. [0x0b] = 2,
  108. [0x4b] = 3,
  109. [0x0c] = 4,
  110. [0x2c] = 5,
  111. [0x4c] = 6,
  112. [0x6c] = 7,
  113. [0x0d] = 8,
  114. [0x2d] = 10,
  115. [0x4d] = 12,
  116. [0x6d] = 14,
  117. [0x0e] = 16,
  118. [0x2e] = 20,
  119. [0x4e] = 24,
  120. [0x6e] = 28,
  121. [0x0f] = 32,
  122. [0x2f] = 40,
  123. [0x4f] = 48,
  124. [0x6f] = 56,
  125. [0x10] = 64,
  126. [0x30] = 80,
  127. [0x50] = 96,
  128. [0x70] = 112,
  129. [0x11] = 128,
  130. };
  131. bool cpu_ivybridge_config_tdp_levels(void)
  132. {
  133. struct cpuid_result result;
  134. /* Minimum CPU revision */
  135. result = cpuid(1);
  136. if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
  137. return false;
  138. return cpu_config_tdp_levels();
  139. }
  140. /*
  141. * Configure processor power limits if possible
  142. * This must be done AFTER set of BIOS_RESET_CPL
  143. */
  144. void set_power_limits(u8 power_limit_1_time)
  145. {
  146. msr_t msr = msr_read(MSR_PLATFORM_INFO);
  147. msr_t limit;
  148. unsigned power_unit;
  149. unsigned tdp, min_power, max_power, max_time;
  150. u8 power_limit_1_val;
  151. if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
  152. return;
  153. if (!(msr.lo & PLATFORM_INFO_SET_TDP))
  154. return;
  155. /* Get units */
  156. msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
  157. power_unit = 2 << ((msr.lo & 0xf) - 1);
  158. /* Get power defaults for this SKU */
  159. msr = msr_read(MSR_PKG_POWER_SKU);
  160. tdp = msr.lo & 0x7fff;
  161. min_power = (msr.lo >> 16) & 0x7fff;
  162. max_power = msr.hi & 0x7fff;
  163. max_time = (msr.hi >> 16) & 0x7f;
  164. debug("CPU TDP: %u Watts\n", tdp / power_unit);
  165. if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
  166. power_limit_1_time = power_limit_time_msr_to_sec[max_time];
  167. if (min_power > 0 && tdp < min_power)
  168. tdp = min_power;
  169. if (max_power > 0 && tdp > max_power)
  170. tdp = max_power;
  171. power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
  172. /* Set long term power limit to TDP */
  173. limit.lo = 0;
  174. limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
  175. limit.lo |= PKG_POWER_LIMIT_EN;
  176. limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
  177. PKG_POWER_LIMIT_TIME_SHIFT;
  178. /* Set short term power limit to 1.25 * TDP */
  179. limit.hi = 0;
  180. limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
  181. limit.hi |= PKG_POWER_LIMIT_EN;
  182. /* Power limit 2 time is only programmable on SNB EP/EX */
  183. msr_write(MSR_PKG_POWER_LIMIT, limit);
  184. /* Use nominal TDP values for CPUs with configurable TDP */
  185. if (cpu_ivybridge_config_tdp_levels()) {
  186. msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
  187. limit.hi = 0;
  188. limit.lo = msr.lo & 0xff;
  189. msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
  190. }
  191. }
  192. static void configure_c_states(void)
  193. {
  194. struct cpuid_result result;
  195. msr_t msr;
  196. msr = msr_read(MSR_PMG_CST_CONFIG_CTL);
  197. msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
  198. msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
  199. msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
  200. msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
  201. msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
  202. msr.lo |= 7; /* No package C-state limit */
  203. msr_write(MSR_PMG_CST_CONFIG_CTL, msr);
  204. msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);
  205. msr.lo &= ~0x7ffff;
  206. msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */
  207. msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */
  208. msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);
  209. msr = msr_read(MSR_MISC_PWR_MGMT);
  210. msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
  211. msr_write(MSR_MISC_PWR_MGMT, msr);
  212. msr = msr_read(MSR_POWER_CTL);
  213. msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
  214. msr.lo |= (1 << 1); /* C1E Enable */
  215. msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
  216. msr_write(MSR_POWER_CTL, msr);
  217. /* C3 Interrupt Response Time Limit */
  218. msr.hi = 0;
  219. msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
  220. msr_write(MSR_PKGC3_IRTL, msr);
  221. /* C6 Interrupt Response Time Limit */
  222. msr.hi = 0;
  223. msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
  224. msr_write(MSR_PKGC6_IRTL, msr);
  225. /* C7 Interrupt Response Time Limit */
  226. msr.hi = 0;
  227. msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
  228. msr_write(MSR_PKGC7_IRTL, msr);
  229. /* Primary Plane Current Limit */
  230. msr = msr_read(MSR_PP0_CURRENT_CONFIG);
  231. msr.lo &= ~0x1fff;
  232. msr.lo |= PP0_CURRENT_LIMIT;
  233. msr_write(MSR_PP0_CURRENT_CONFIG, msr);
  234. /* Secondary Plane Current Limit */
  235. msr = msr_read(MSR_PP1_CURRENT_CONFIG);
  236. msr.lo &= ~0x1fff;
  237. result = cpuid(1);
  238. if (result.eax >= 0x30600)
  239. msr.lo |= PP1_CURRENT_LIMIT_IVB;
  240. else
  241. msr.lo |= PP1_CURRENT_LIMIT_SNB;
  242. msr_write(MSR_PP1_CURRENT_CONFIG, msr);
  243. }
  244. static void configure_misc(void)
  245. {
  246. msr_t msr;
  247. msr = msr_read(IA32_MISC_ENABLE);
  248. msr.lo |= (1 << 0); /* Fast String enable */
  249. msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
  250. msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
  251. msr_write(IA32_MISC_ENABLE, msr);
  252. /* Disable Thermal interrupts */
  253. msr.lo = 0;
  254. msr.hi = 0;
  255. msr_write(IA32_THERM_INTERRUPT, msr);
  256. /* Enable package critical interrupt only */
  257. msr.lo = 1 << 4;
  258. msr.hi = 0;
  259. msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);
  260. }
  261. static void enable_lapic_tpr(void)
  262. {
  263. msr_t msr;
  264. msr = msr_read(MSR_PIC_MSG_CONTROL);
  265. msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
  266. msr_write(MSR_PIC_MSG_CONTROL, msr);
  267. }
  268. static void configure_dca_cap(void)
  269. {
  270. struct cpuid_result cpuid_regs;
  271. msr_t msr;
  272. /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
  273. cpuid_regs = cpuid(1);
  274. if (cpuid_regs.ecx & (1 << 18)) {
  275. msr = msr_read(IA32_PLATFORM_DCA_CAP);
  276. msr.lo |= 1;
  277. msr_write(IA32_PLATFORM_DCA_CAP, msr);
  278. }
  279. }
  280. static void set_max_ratio(void)
  281. {
  282. msr_t msr;
  283. uint ratio;
  284. /* Check for configurable TDP option */
  285. if (cpu_ivybridge_config_tdp_levels()) {
  286. /* Set to nominal TDP ratio */
  287. msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
  288. ratio = msr.lo & 0xff;
  289. } else {
  290. /* Platform Info bits 15:8 give max ratio */
  291. msr = msr_read(MSR_PLATFORM_INFO);
  292. ratio = (msr.lo & 0xff00) >> 8;
  293. }
  294. cpu_set_perf_control(ratio);
  295. }
  296. static void set_energy_perf_bias(u8 policy)
  297. {
  298. msr_t msr;
  299. /* Energy Policy is bits 3:0 */
  300. msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);
  301. msr.lo &= ~0xf;
  302. msr.lo |= policy & 0xf;
  303. msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);
  304. debug("model_x06ax: energy policy set to %u\n", policy);
  305. }
  306. static void configure_mca(void)
  307. {
  308. msr_t msr;
  309. int i;
  310. msr.lo = 0;
  311. msr.hi = 0;
  312. /* This should only be done on a cold boot */
  313. for (i = 0; i < 7; i++)
  314. msr_write(IA32_MC0_STATUS + (i * 4), msr);
  315. }
  316. static int model_206ax_init(struct udevice *dev)
  317. {
  318. int ret;
  319. /* Clear out pending MCEs */
  320. configure_mca();
  321. /* Enable the local cpu apics */
  322. enable_lapic_tpr();
  323. /* Enable virtualization if enabled in CMOS */
  324. enable_vmx();
  325. /* Configure C States */
  326. configure_c_states();
  327. /* Configure Enhanced SpeedStep and Thermal Sensors */
  328. configure_misc();
  329. /* Thermal throttle activation offset */
  330. ret = cpu_configure_thermal_target(dev);
  331. if (ret) {
  332. debug("Cannot set thermal target\n");
  333. if (ret != -ENOENT)
  334. return ret;
  335. }
  336. /* Enable Direct Cache Access */
  337. configure_dca_cap();
  338. /* Set energy policy */
  339. set_energy_perf_bias(ENERGY_POLICY_NORMAL);
  340. /* Set Max Ratio */
  341. set_max_ratio();
  342. /* Enable Turbo */
  343. turbo_enable();
  344. return 0;
  345. }
  346. static int model_206ax_get_info(const struct udevice *dev,
  347. struct cpu_info *info)
  348. {
  349. return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
  350. return 0;
  351. }
  352. static int model_206ax_get_count(const struct udevice *dev)
  353. {
  354. return 4;
  355. }
  356. static int cpu_x86_model_206ax_probe(struct udevice *dev)
  357. {
  358. if (dev_seq(dev) == 0)
  359. model_206ax_init(dev);
  360. return 0;
  361. }
  362. static const struct cpu_ops cpu_x86_model_206ax_ops = {
  363. .get_desc = cpu_x86_get_desc,
  364. .get_info = model_206ax_get_info,
  365. .get_count = model_206ax_get_count,
  366. .get_vendor = cpu_x86_get_vendor,
  367. };
  368. static const struct udevice_id cpu_x86_model_206ax_ids[] = {
  369. { .compatible = "intel,core-gen3" },
  370. { }
  371. };
  372. U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = {
  373. .name = "cpu_x86_model_206ax",
  374. .id = UCLASS_CPU,
  375. .of_match = cpu_x86_model_206ax_ids,
  376. .bind = cpu_x86_bind,
  377. .probe = cpu_x86_model_206ax_probe,
  378. .ops = &cpu_x86_model_206ax_ops,
  379. .flags = DM_FLAG_PRE_RELOC,
  380. };