atmel_pio4.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atmel PIO4 device driver
  4. *
  5. * Copyright (C) 2015 Atmel Corporation
  6. * Wenyou.Yang <wenyou.yang@atmel.com>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <malloc.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/gpio.h>
  15. #include <linux/bitops.h>
  16. #include <mach/gpio.h>
  17. #include <mach/atmel_pio4.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
  20. {
  21. struct atmel_pio4_port *base = NULL;
  22. switch (port) {
  23. case AT91_PIO_PORTA:
  24. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
  25. break;
  26. case AT91_PIO_PORTB:
  27. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
  28. break;
  29. case AT91_PIO_PORTC:
  30. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
  31. break;
  32. case AT91_PIO_PORTD:
  33. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
  34. break;
  35. default:
  36. printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
  37. port);
  38. break;
  39. }
  40. return base;
  41. }
  42. static int atmel_pio4_config_io_func(u32 port, u32 pin,
  43. u32 func, u32 config)
  44. {
  45. struct atmel_pio4_port *port_base;
  46. u32 reg, mask;
  47. if (pin >= ATMEL_PIO_NPINS_PER_BANK)
  48. return -EINVAL;
  49. port_base = atmel_pio4_port_base(port);
  50. if (!port_base)
  51. return -EINVAL;
  52. mask = 1 << pin;
  53. reg = func;
  54. reg |= config;
  55. writel(mask, &port_base->mskr);
  56. writel(reg, &port_base->cfgr);
  57. return 0;
  58. }
  59. int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config)
  60. {
  61. return atmel_pio4_config_io_func(port, pin,
  62. ATMEL_PIO_CFGR_FUNC_GPIO,
  63. config);
  64. }
  65. int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config)
  66. {
  67. return atmel_pio4_config_io_func(port, pin,
  68. ATMEL_PIO_CFGR_FUNC_PERIPH_A,
  69. config);
  70. }
  71. int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config)
  72. {
  73. return atmel_pio4_config_io_func(port, pin,
  74. ATMEL_PIO_CFGR_FUNC_PERIPH_B,
  75. config);
  76. }
  77. int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config)
  78. {
  79. return atmel_pio4_config_io_func(port, pin,
  80. ATMEL_PIO_CFGR_FUNC_PERIPH_C,
  81. config);
  82. }
  83. int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config)
  84. {
  85. return atmel_pio4_config_io_func(port, pin,
  86. ATMEL_PIO_CFGR_FUNC_PERIPH_D,
  87. config);
  88. }
  89. int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config)
  90. {
  91. return atmel_pio4_config_io_func(port, pin,
  92. ATMEL_PIO_CFGR_FUNC_PERIPH_E,
  93. config);
  94. }
  95. int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config)
  96. {
  97. return atmel_pio4_config_io_func(port, pin,
  98. ATMEL_PIO_CFGR_FUNC_PERIPH_F,
  99. config);
  100. }
  101. int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config)
  102. {
  103. return atmel_pio4_config_io_func(port, pin,
  104. ATMEL_PIO_CFGR_FUNC_PERIPH_G,
  105. config);
  106. }
  107. int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
  108. {
  109. struct atmel_pio4_port *port_base;
  110. u32 reg, mask;
  111. if (pin >= ATMEL_PIO_NPINS_PER_BANK)
  112. return -EINVAL;
  113. port_base = atmel_pio4_port_base(port);
  114. if (!port_base)
  115. return -EINVAL;
  116. mask = 0x01 << pin;
  117. reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
  118. writel(mask, &port_base->mskr);
  119. writel(reg, &port_base->cfgr);
  120. if (value)
  121. writel(mask, &port_base->sodr);
  122. else
  123. writel(mask, &port_base->codr);
  124. return 0;
  125. }
  126. int atmel_pio4_get_pio_input(u32 port, u32 pin)
  127. {
  128. struct atmel_pio4_port *port_base;
  129. u32 reg, mask;
  130. if (pin >= ATMEL_PIO_NPINS_PER_BANK)
  131. return -EINVAL;
  132. port_base = atmel_pio4_port_base(port);
  133. if (!port_base)
  134. return -EINVAL;
  135. mask = 0x01 << pin;
  136. reg = ATMEL_PIO_CFGR_FUNC_GPIO;
  137. writel(mask, &port_base->mskr);
  138. writel(reg, &port_base->cfgr);
  139. return (readl(&port_base->pdsr) & mask) ? 1 : 0;
  140. }
  141. #if CONFIG_IS_ENABLED(DM_GPIO)
  142. struct atmel_pioctrl_data {
  143. u32 nbanks;
  144. };
  145. struct atmel_pio4_plat {
  146. struct atmel_pio4_port *reg_base;
  147. };
  148. static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
  149. u32 bank)
  150. {
  151. struct atmel_pio4_plat *plat = dev_get_plat(dev);
  152. struct atmel_pio4_port *port_base =
  153. (struct atmel_pio4_port *)((u32)plat->reg_base +
  154. ATMEL_PIO_BANK_OFFSET * bank);
  155. return port_base;
  156. }
  157. static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
  158. {
  159. u32 bank = ATMEL_PIO_BANK(offset);
  160. u32 line = ATMEL_PIO_LINE(offset);
  161. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  162. u32 mask = BIT(line);
  163. writel(mask, &port_base->mskr);
  164. clrbits_le32(&port_base->cfgr,
  165. ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
  166. return 0;
  167. }
  168. static int atmel_pio4_direction_output(struct udevice *dev,
  169. unsigned offset, int value)
  170. {
  171. u32 bank = ATMEL_PIO_BANK(offset);
  172. u32 line = ATMEL_PIO_LINE(offset);
  173. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  174. u32 mask = BIT(line);
  175. writel(mask, &port_base->mskr);
  176. clrsetbits_le32(&port_base->cfgr,
  177. ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
  178. if (value)
  179. writel(mask, &port_base->sodr);
  180. else
  181. writel(mask, &port_base->codr);
  182. return 0;
  183. }
  184. static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
  185. {
  186. u32 bank = ATMEL_PIO_BANK(offset);
  187. u32 line = ATMEL_PIO_LINE(offset);
  188. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  189. u32 mask = BIT(line);
  190. return (readl(&port_base->pdsr) & mask) ? 1 : 0;
  191. }
  192. static int atmel_pio4_set_value(struct udevice *dev,
  193. unsigned offset, int value)
  194. {
  195. u32 bank = ATMEL_PIO_BANK(offset);
  196. u32 line = ATMEL_PIO_LINE(offset);
  197. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  198. u32 mask = BIT(line);
  199. if (value)
  200. writel(mask, &port_base->sodr);
  201. else
  202. writel(mask, &port_base->codr);
  203. return 0;
  204. }
  205. static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
  206. {
  207. u32 bank = ATMEL_PIO_BANK(offset);
  208. u32 line = ATMEL_PIO_LINE(offset);
  209. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  210. u32 mask = BIT(line);
  211. writel(mask, &port_base->mskr);
  212. return (readl(&port_base->cfgr) &
  213. ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
  214. }
  215. static const struct dm_gpio_ops atmel_pio4_ops = {
  216. .direction_input = atmel_pio4_direction_input,
  217. .direction_output = atmel_pio4_direction_output,
  218. .get_value = atmel_pio4_get_value,
  219. .set_value = atmel_pio4_set_value,
  220. .get_function = atmel_pio4_get_function,
  221. };
  222. static int atmel_pio4_bind(struct udevice *dev)
  223. {
  224. return dm_scan_fdt_dev(dev);
  225. }
  226. static int atmel_pio4_probe(struct udevice *dev)
  227. {
  228. struct atmel_pio4_plat *plat = dev_get_plat(dev);
  229. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  230. struct atmel_pioctrl_data *pioctrl_data;
  231. struct clk clk;
  232. fdt_addr_t addr_base;
  233. u32 nbanks;
  234. int ret;
  235. ret = clk_get_by_index(dev, 0, &clk);
  236. if (ret)
  237. return ret;
  238. ret = clk_enable(&clk);
  239. if (ret)
  240. return ret;
  241. clk_free(&clk);
  242. addr_base = dev_read_addr(dev);
  243. if (addr_base == FDT_ADDR_T_NONE)
  244. return -EINVAL;
  245. plat->reg_base = (struct atmel_pio4_port *)addr_base;
  246. pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
  247. nbanks = pioctrl_data->nbanks;
  248. uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
  249. NULL);
  250. uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
  251. return 0;
  252. }
  253. /*
  254. * The number of banks can be different from a SoC to another one.
  255. * We can have up to 16 banks.
  256. */
  257. static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
  258. .nbanks = 4,
  259. };
  260. static const struct udevice_id atmel_pio4_ids[] = {
  261. {
  262. .compatible = "atmel,sama5d2-gpio",
  263. .data = (ulong)&atmel_sama5d2_pioctrl_data,
  264. },
  265. {}
  266. };
  267. U_BOOT_DRIVER(gpio_atmel_pio4) = {
  268. .name = "gpio_atmel_pio4",
  269. .id = UCLASS_GPIO,
  270. .ops = &atmel_pio4_ops,
  271. .probe = atmel_pio4_probe,
  272. .bind = atmel_pio4_bind,
  273. .of_match = atmel_pio4_ids,
  274. .plat_auto = sizeof(struct atmel_pio4_plat),
  275. };
  276. #endif