sdram_soc64.h 5.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  4. */
  5. #ifndef _SDRAM_SOC64_H_
  6. #define _SDRAM_SOC64_H_
  7. #include <common.h>
  8. #include <linux/sizes.h>
  9. struct altera_sdram_priv {
  10. struct ram_info info;
  11. struct reset_ctl_bulk resets;
  12. };
  13. struct altera_sdram_plat {
  14. void __iomem *hmc;
  15. void __iomem *ddr_sch;
  16. void __iomem *iomhc;
  17. };
  18. /* ECC HMC registers */
  19. #define DDRIOCTRL 0x8
  20. #define DDRCALSTAT 0xc
  21. #define DRAMADDRWIDTH 0xe0
  22. #define ECCCTRL1 0x100
  23. #define ECCCTRL2 0x104
  24. #define ERRINTEN 0x110
  25. #define ERRINTENS 0x114
  26. #define INTMODE 0x11c
  27. #define INTSTAT 0x120
  28. #define AUTOWB_CORRADDR 0x138
  29. #define ECC_REG2WRECCDATABUS 0x144
  30. #define ECC_DIAGON 0x150
  31. #define ECC_DECSTAT 0x154
  32. #define HPSINTFCSEL 0x210
  33. #define RSTHANDSHAKECTRL 0x214
  34. #define RSTHANDSHAKESTAT 0x218
  35. #define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003
  36. #define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0)
  37. #define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
  38. #define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8)
  39. #define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0)
  40. #define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8)
  41. #define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0)
  42. #define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16)
  43. #define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0)
  44. #define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0)
  45. #define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1)
  46. #define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0)
  47. #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1)
  48. #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16)
  49. #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
  50. #define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff
  51. #define DDR_HMC_CORE2SEQ_INT_REQ 0xF
  52. #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
  53. #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
  54. #define DDR_HMC_ERRINTEN_INTMASK \
  55. (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \
  56. DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
  57. /* HMC MMR IO48 registers */
  58. #define CTRLCFG0 0x28
  59. #define CTRLCFG1 0x2c
  60. #define CTRLCFG3 0x34
  61. #define DRAMTIMING0 0x50
  62. #define CALTIMING0 0x7c
  63. #define CALTIMING1 0x80
  64. #define CALTIMING2 0x84
  65. #define CALTIMING3 0x88
  66. #define CALTIMING4 0x8c
  67. #define CALTIMING9 0xa0
  68. #define DRAMADDRW 0xa8
  69. #define DRAMSTS 0xec
  70. #define NIOSRESERVED0 0x110
  71. #define NIOSRESERVED1 0x114
  72. #define NIOSRESERVED2 0x118
  73. #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \
  74. (((x) >> 0) & 0x1F)
  75. #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
  76. (((x) >> 5) & 0x1F)
  77. #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
  78. (((x) >> 10) & 0xF)
  79. #define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \
  80. (((x) >> 14) & 0x3)
  81. #define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \
  82. (((x) >> 16) & 0x7)
  83. #define CTRLCFG0_CFG_MEMTYPE(x) \
  84. (((x) >> 0) & 0xF)
  85. #define CTRLCFG0_CFG_DIMM_TYPE(x) \
  86. (((x) >> 4) & 0x7)
  87. #define CTRLCFG0_CFG_AC_POS(x) \
  88. (((x) >> 7) & 0x3)
  89. #define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \
  90. (((x) >> 9) & 0x1F)
  91. #define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
  92. (((x) >> 0) & 0x1F)
  93. #define CTRLCFG1_CFG_ADDR_ORDER(x) \
  94. (((x) >> 5) & 0x3)
  95. #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
  96. (((x) >> 7) & 0x1)
  97. #define DRAMTIMING0_CFG_TCL(x) \
  98. (((x) >> 0) & 0x7F)
  99. #define CALTIMING0_CFG_ACT_TO_RDWR(x) \
  100. (((x) >> 0) & 0x3F)
  101. #define CALTIMING0_CFG_ACT_TO_PCH(x) \
  102. (((x) >> 6) & 0x3F)
  103. #define CALTIMING0_CFG_ACT_TO_ACT(x) \
  104. (((x) >> 12) & 0x3F)
  105. #define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \
  106. (((x) >> 18) & 0x3F)
  107. #define CALTIMING1_CFG_RD_TO_RD(x) \
  108. (((x) >> 0) & 0x3F)
  109. #define CALTIMING1_CFG_RD_TO_RD_DC(x) \
  110. (((x) >> 6) & 0x3F)
  111. #define CALTIMING1_CFG_RD_TO_RD_DB(x) \
  112. (((x) >> 12) & 0x3F)
  113. #define CALTIMING1_CFG_RD_TO_WR(x) \
  114. (((x) >> 18) & 0x3F)
  115. #define CALTIMING1_CFG_RD_TO_WR_DC(x) \
  116. (((x) >> 24) & 0x3F)
  117. #define CALTIMING2_CFG_RD_TO_WR_DB(x) \
  118. (((x) >> 0) & 0x3F)
  119. #define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
  120. (((x) >> 6) & 0x3F)
  121. #define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
  122. (((x) >> 12) & 0x3F)
  123. #define CALTIMING2_CFG_WR_TO_WR(x) \
  124. (((x) >> 18) & 0x3F)
  125. #define CALTIMING2_CFG_WR_TO_WR_DC(x) \
  126. (((x) >> 24) & 0x3F)
  127. #define CALTIMING3_CFG_WR_TO_WR_DB(x) \
  128. (((x) >> 0) & 0x3F)
  129. #define CALTIMING3_CFG_WR_TO_RD(x) \
  130. (((x) >> 6) & 0x3F)
  131. #define CALTIMING3_CFG_WR_TO_RD_DC(x) \
  132. (((x) >> 12) & 0x3F)
  133. #define CALTIMING3_CFG_WR_TO_RD_DB(x) \
  134. (((x) >> 18) & 0x3F)
  135. #define CALTIMING3_CFG_WR_TO_PCH(x) \
  136. (((x) >> 24) & 0x3F)
  137. #define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
  138. (((x) >> 0) & 0x3F)
  139. #define CALTIMING4_CFG_PCH_TO_VALID(x) \
  140. (((x) >> 6) & 0x3F)
  141. #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
  142. (((x) >> 12) & 0x3F)
  143. #define CALTIMING4_CFG_ARF_TO_VALID(x) \
  144. (((x) >> 18) & 0xFF)
  145. #define CALTIMING4_CFG_PDN_TO_VALID(x) \
  146. (((x) >> 26) & 0x3F)
  147. #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
  148. (((x) >> 0) & 0xFF)
  149. /* Firewall DDR scheduler MPFE */
  150. #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
  151. #define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
  152. u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg);
  153. u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg);
  154. u32 hmc_ecc_writel(struct altera_sdram_plat *plat,
  155. u32 data, u32 reg);
  156. u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data,
  157. u32 reg);
  158. int emif_clear(struct altera_sdram_plat *plat);
  159. int emif_reset(struct altera_sdram_plat *plat);
  160. int poll_hmc_clock_status(void);
  161. void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
  162. void sdram_init_ecc_bits(struct bd_info *bd);
  163. void sdram_size_check(struct bd_info *bd);
  164. phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat);
  165. int sdram_mmr_init_full(struct udevice *dev);
  166. #endif /* _SDRAM_SOC64_H_ */