sdram_soc64.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <div64.h>
  11. #include <fdtdec.h>
  12. #include <hang.h>
  13. #include <init.h>
  14. #include <log.h>
  15. #include <ram.h>
  16. #include <reset.h>
  17. #include "sdram_soc64.h"
  18. #include <wait_bit.h>
  19. #include <asm/arch/firewall.h>
  20. #include <asm/arch/system_manager.h>
  21. #include <asm/arch/reset_manager.h>
  22. #include <asm/cache.h>
  23. #include <asm/io.h>
  24. #include <dm/device_compat.h>
  25. #include <linux/sizes.h>
  26. #define PGTABLE_OFF 0x4000
  27. u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
  28. {
  29. return readl(plat->iomhc + reg);
  30. }
  31. u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg)
  32. {
  33. return readl(plat->hmc + reg);
  34. }
  35. u32 hmc_ecc_writel(struct altera_sdram_plat *plat,
  36. u32 data, u32 reg)
  37. {
  38. return writel(data, plat->hmc + reg);
  39. }
  40. u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data,
  41. u32 reg)
  42. {
  43. return writel(data, plat->ddr_sch + reg);
  44. }
  45. int emif_clear(struct altera_sdram_plat *plat)
  46. {
  47. hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
  48. return wait_for_bit_le32((const void *)(plat->hmc +
  49. RSTHANDSHAKESTAT),
  50. DDR_HMC_RSTHANDSHAKE_MASK,
  51. false, 1000, false);
  52. }
  53. int emif_reset(struct altera_sdram_plat *plat)
  54. {
  55. u32 c2s, s2c, ret;
  56. c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
  57. s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
  58. debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
  59. c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
  60. hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
  61. hmc_readl(plat, DRAMSTS));
  62. if (s2c && emif_clear(plat)) {
  63. printf("DDR: emif_clear() failed\n");
  64. return -1;
  65. }
  66. debug("DDR: Triggerring emif reset\n");
  67. hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
  68. /* if seq2core[3] = 0, we are good */
  69. ret = wait_for_bit_le32((const void *)(plat->hmc +
  70. RSTHANDSHAKESTAT),
  71. DDR_HMC_SEQ2CORE_INT_RESP_MASK,
  72. false, 1000, false);
  73. if (ret) {
  74. printf("DDR: failed to get ack from EMIF\n");
  75. return ret;
  76. }
  77. ret = emif_clear(plat);
  78. if (ret) {
  79. printf("DDR: emif_clear() failed\n");
  80. return ret;
  81. }
  82. debug("DDR: %s triggered successly\n", __func__);
  83. return 0;
  84. }
  85. int poll_hmc_clock_status(void)
  86. {
  87. return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
  88. SYSMGR_SOC64_HMC_CLK),
  89. SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
  90. }
  91. void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
  92. {
  93. phys_size_t i;
  94. if (addr % CONFIG_SYS_CACHELINE_SIZE) {
  95. printf("DDR: address 0x%llx is not cacheline size aligned.\n",
  96. addr);
  97. hang();
  98. }
  99. if (size % CONFIG_SYS_CACHELINE_SIZE) {
  100. printf("DDR: size 0x%llx is not multiple of cacheline size\n",
  101. size);
  102. hang();
  103. }
  104. /* Use DC ZVA instruction to clear memory to zeros by a cache line */
  105. for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
  106. asm volatile("dc zva, %0"
  107. :
  108. : "r"(addr)
  109. : "memory");
  110. addr += CONFIG_SYS_CACHELINE_SIZE;
  111. }
  112. }
  113. void sdram_init_ecc_bits(struct bd_info *bd)
  114. {
  115. phys_size_t size, size_init;
  116. phys_addr_t start_addr;
  117. int bank = 0;
  118. unsigned int start = get_timer(0);
  119. icache_enable();
  120. start_addr = bd->bi_dram[0].start;
  121. size = bd->bi_dram[0].size;
  122. /* Initialize small block for page table */
  123. memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
  124. gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
  125. gd->arch.tlb_size = PGTABLE_SIZE;
  126. start_addr += PGTABLE_SIZE + PGTABLE_OFF;
  127. size -= (PGTABLE_OFF + PGTABLE_SIZE);
  128. dcache_enable();
  129. while (1) {
  130. while (size) {
  131. size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
  132. sdram_clear_mem(start_addr, size_init);
  133. size -= size_init;
  134. start_addr += size_init;
  135. WATCHDOG_RESET();
  136. }
  137. bank++;
  138. if (bank >= CONFIG_NR_DRAM_BANKS)
  139. break;
  140. start_addr = bd->bi_dram[bank].start;
  141. size = bd->bi_dram[bank].size;
  142. }
  143. dcache_disable();
  144. icache_disable();
  145. printf("SDRAM-ECC: Initialized success with %d ms\n",
  146. (unsigned int)get_timer(start));
  147. }
  148. void sdram_size_check(struct bd_info *bd)
  149. {
  150. phys_size_t total_ram_check = 0;
  151. phys_size_t ram_check = 0;
  152. phys_addr_t start = 0;
  153. int bank;
  154. /* Sanity check ensure correct SDRAM size specified */
  155. debug("DDR: Running SDRAM size sanity check\n");
  156. for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
  157. start = bd->bi_dram[bank].start;
  158. while (ram_check < bd->bi_dram[bank].size) {
  159. ram_check += get_ram_size((void *)(start + ram_check),
  160. (phys_size_t)SZ_1G);
  161. }
  162. total_ram_check += ram_check;
  163. ram_check = 0;
  164. }
  165. /* If the ram_size is 2GB smaller, we can assume the IO space is
  166. * not mapped in. gd->ram_size is the actual size of the dram
  167. * not the accessible size.
  168. */
  169. if (total_ram_check != gd->ram_size) {
  170. puts("DDR: SDRAM size check failed!\n");
  171. hang();
  172. }
  173. debug("DDR: SDRAM size check passed!\n");
  174. }
  175. /**
  176. * sdram_calculate_size() - Calculate SDRAM size
  177. *
  178. * Calculate SDRAM device size based on SDRAM controller parameters.
  179. * Size is specified in bytes.
  180. */
  181. phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
  182. {
  183. u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
  184. phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
  185. DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
  186. DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
  187. DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
  188. DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
  189. size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
  190. DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
  191. return size;
  192. }
  193. static int altera_sdram_of_to_plat(struct udevice *dev)
  194. {
  195. struct altera_sdram_plat *plat = dev->plat;
  196. fdt_addr_t addr;
  197. addr = dev_read_addr_index(dev, 0);
  198. if (addr == FDT_ADDR_T_NONE)
  199. return -EINVAL;
  200. plat->ddr_sch = (void __iomem *)addr;
  201. addr = dev_read_addr_index(dev, 1);
  202. if (addr == FDT_ADDR_T_NONE)
  203. return -EINVAL;
  204. plat->iomhc = (void __iomem *)addr;
  205. addr = dev_read_addr_index(dev, 2);
  206. if (addr == FDT_ADDR_T_NONE)
  207. return -EINVAL;
  208. plat->hmc = (void __iomem *)addr;
  209. return 0;
  210. }
  211. static int altera_sdram_probe(struct udevice *dev)
  212. {
  213. int ret;
  214. struct altera_sdram_priv *priv = dev_get_priv(dev);
  215. ret = reset_get_bulk(dev, &priv->resets);
  216. if (ret) {
  217. dev_err(dev, "Can't get reset: %d\n", ret);
  218. return -ENODEV;
  219. }
  220. reset_deassert_bulk(&priv->resets);
  221. if (sdram_mmr_init_full(dev) != 0) {
  222. puts("SDRAM init failed.\n");
  223. goto failed;
  224. }
  225. return 0;
  226. failed:
  227. reset_release_bulk(&priv->resets);
  228. return -ENODEV;
  229. }
  230. static int altera_sdram_get_info(struct udevice *dev,
  231. struct ram_info *info)
  232. {
  233. struct altera_sdram_priv *priv = dev_get_priv(dev);
  234. info->base = priv->info.base;
  235. info->size = priv->info.size;
  236. return 0;
  237. }
  238. static struct ram_ops altera_sdram_ops = {
  239. .get_info = altera_sdram_get_info,
  240. };
  241. static const struct udevice_id altera_sdram_ids[] = {
  242. { .compatible = "altr,sdr-ctl-s10" },
  243. { .compatible = "intel,sdr-ctl-agilex" },
  244. { /* sentinel */ }
  245. };
  246. U_BOOT_DRIVER(altera_sdram) = {
  247. .name = "altr_sdr_ctl",
  248. .id = UCLASS_RAM,
  249. .of_match = altera_sdram_ids,
  250. .ops = &altera_sdram_ops,
  251. .of_to_plat = altera_sdram_of_to_plat,
  252. .plat_auto = sizeof(struct altera_sdram_plat),
  253. .probe = altera_sdram_probe,
  254. .priv_auto = sizeof(struct altera_sdram_priv),
  255. };