sdram_agilex.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <div64.h>
  10. #include <fdtdec.h>
  11. #include <hang.h>
  12. #include <log.h>
  13. #include <ram.h>
  14. #include <reset.h>
  15. #include "sdram_soc64.h"
  16. #include <wait_bit.h>
  17. #include <asm/arch/firewall.h>
  18. #include <asm/arch/reset_manager.h>
  19. #include <asm/arch/system_manager.h>
  20. #include <asm/io.h>
  21. #include <linux/sizes.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. int sdram_mmr_init_full(struct udevice *dev)
  24. {
  25. struct altera_sdram_plat *plat = dev->plat;
  26. struct altera_sdram_priv *priv = dev_get_priv(dev);
  27. u32 i;
  28. int ret;
  29. phys_size_t hw_size;
  30. struct bd_info bd = {0};
  31. /* Ensure HMC clock is running */
  32. if (poll_hmc_clock_status()) {
  33. debug("DDR: Error as HMC clock was not running\n");
  34. return -EPERM;
  35. }
  36. /* Trying 3 times to do a calibration */
  37. for (i = 0; i < 3; i++) {
  38. ret = wait_for_bit_le32((const void *)(plat->hmc +
  39. DDRCALSTAT),
  40. DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
  41. false);
  42. if (!ret)
  43. break;
  44. emif_reset(plat);
  45. }
  46. if (ret) {
  47. puts("DDR: Error as SDRAM calibration failed\n");
  48. return -EPERM;
  49. }
  50. debug("DDR: Calibration success\n");
  51. /*
  52. * Configure the DDR IO size
  53. * niosreserve0: Used to indicate DDR width &
  54. * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
  55. * bit[8] = 1 if user-mode OCT is present
  56. * bit[9] = 1 if warm reset compiled into EMIF Cal Code
  57. * bit[10] = 1 if warm reset is on during generation in EMIF Cal
  58. * niosreserve1: IP ADCDS version encoded as 16 bit value
  59. * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
  60. * 3=EAP, 4-6 are reserved)
  61. * bit[5:3] = Service Pack # (e.g. 1)
  62. * bit[9:6] = Minor Release #
  63. * bit[14:10] = Major Release #
  64. */
  65. /* Configure DDR IO size x16, x32 and x64 mode */
  66. u32 update_value;
  67. update_value = hmc_readl(plat, NIOSRESERVED0);
  68. update_value = (update_value & 0xFF) >> 5;
  69. /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */
  70. update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4);
  71. hmc_ecc_writel(plat, update_value, DDRIOCTRL);
  72. /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */
  73. hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
  74. /* assigning the SDRAM size */
  75. phys_size_t size = sdram_calculate_size(plat);
  76. if (size <= 0)
  77. hw_size = PHYS_SDRAM_1_SIZE;
  78. else
  79. hw_size = size;
  80. /* Get bank configuration from devicetree */
  81. ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
  82. (phys_size_t *)&gd->ram_size, &bd);
  83. if (ret) {
  84. puts("DDR: Failed to decode memory node\n");
  85. return -ENXIO;
  86. }
  87. if (gd->ram_size != hw_size) {
  88. printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",
  89. gd->ram_size >> 20);
  90. printf(" mismatch with hardware (%lld MiB).\n",
  91. hw_size >> 20);
  92. }
  93. if (gd->ram_size > hw_size) {
  94. printf("DDR: Error: DRAM size from device tree is greater\n");
  95. printf(" than hardware size.\n");
  96. hang();
  97. }
  98. printf("DDR: %lld MiB\n", gd->ram_size >> 20);
  99. /* This enables nonsecure access to DDR */
  100. /* mpuregion0addr_limit */
  101. FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
  102. FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
  103. FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
  104. /* nonmpuregion0addr_limit */
  105. FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
  106. FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
  107. /* Enable mpuregion0enable and nonmpuregion0enable */
  108. FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
  109. FW_MPU_DDR_SCR_EN_SET);
  110. u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
  111. /* Enable or disable the DDR ECC */
  112. if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
  113. setbits_le32(plat->hmc + ECCCTRL1,
  114. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  115. DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
  116. DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
  117. clrbits_le32(plat->hmc + ECCCTRL1,
  118. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  119. DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
  120. setbits_le32(plat->hmc + ECCCTRL2,
  121. (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
  122. DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
  123. setbits_le32(plat->hmc + ERRINTEN,
  124. DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
  125. if (!cpu_has_been_warmreset())
  126. sdram_init_ecc_bits(&bd);
  127. } else {
  128. clrbits_le32(plat->hmc + ECCCTRL1,
  129. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  130. DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
  131. DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
  132. clrbits_le32(plat->hmc + ECCCTRL2,
  133. (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
  134. DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
  135. }
  136. /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
  137. writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
  138. sdram_size_check(&bd);
  139. priv->info.base = bd.bi_dram[0].start;
  140. priv->info.size = gd->ram_size;
  141. debug("DDR: HMC init success\n");
  142. return 0;
  143. }