imx8_cpu.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <cpu.h>
  7. #include <dm.h>
  8. #include <thermal.h>
  9. #include <asm/system.h>
  10. #include <asm/arch/sci/sci.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/arch-imx/cpu.h>
  13. #include <asm/armv8/cpu.h>
  14. #include <linux/bitops.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. struct cpu_imx_plat {
  17. const char *name;
  18. const char *rev;
  19. const char *type;
  20. u32 cpu_rsrc;
  21. u32 cpurev;
  22. u32 freq_mhz;
  23. u32 mpidr;
  24. };
  25. const char *get_imx8_type(u32 imxtype)
  26. {
  27. switch (imxtype) {
  28. case MXC_CPU_IMX8QXP:
  29. case MXC_CPU_IMX8QXP_A0:
  30. return "QXP";
  31. case MXC_CPU_IMX8QM:
  32. return "QM";
  33. default:
  34. return "??";
  35. }
  36. }
  37. const char *get_imx8_rev(u32 rev)
  38. {
  39. switch (rev) {
  40. case CHIP_REV_A:
  41. return "A";
  42. case CHIP_REV_B:
  43. return "B";
  44. case CHIP_REV_C:
  45. return "C";
  46. default:
  47. return "?";
  48. }
  49. }
  50. static void set_core_data(struct udevice *dev)
  51. {
  52. struct cpu_imx_plat *plat = dev_get_plat(dev);
  53. if (device_is_compatible(dev, "arm,cortex-a35")) {
  54. plat->cpu_rsrc = SC_R_A35;
  55. plat->name = "A35";
  56. } else if (device_is_compatible(dev, "arm,cortex-a53")) {
  57. plat->cpu_rsrc = SC_R_A53;
  58. plat->name = "A53";
  59. } else if (device_is_compatible(dev, "arm,cortex-a72")) {
  60. plat->cpu_rsrc = SC_R_A72;
  61. plat->name = "A72";
  62. } else {
  63. plat->cpu_rsrc = SC_R_A53;
  64. plat->name = "?";
  65. }
  66. }
  67. #if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
  68. static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
  69. {
  70. struct udevice *thermal_dev;
  71. int cpu_tmp, ret;
  72. int idx = 1; /* use "cpu-thermal0" device */
  73. if (plat->cpu_rsrc == SC_R_A72)
  74. idx = 2; /* use "cpu-thermal1" device */
  75. ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev);
  76. if (!ret) {
  77. ret = thermal_get_temp(thermal_dev, &cpu_tmp);
  78. if (ret)
  79. return 0xdeadbeef;
  80. } else {
  81. return 0xdeadbeef;
  82. }
  83. return cpu_tmp;
  84. }
  85. #else
  86. static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
  87. {
  88. return 0;
  89. }
  90. #endif
  91. int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
  92. {
  93. struct cpu_imx_plat *plat = dev_get_plat(dev);
  94. int ret, temp;
  95. if (size < 100)
  96. return -ENOSPC;
  97. ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
  98. plat->type, plat->rev, plat->name, plat->freq_mhz);
  99. if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
  100. temp = cpu_imx_get_temp(plat);
  101. buf = buf + ret;
  102. size = size - ret;
  103. if (temp != 0xdeadbeef)
  104. ret = snprintf(buf, size, " at %dC", temp);
  105. else
  106. ret = snprintf(buf, size, " - invalid sensor data");
  107. }
  108. snprintf(buf + ret, size - ret, "\n");
  109. return 0;
  110. }
  111. static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
  112. {
  113. struct cpu_imx_plat *plat = dev_get_plat(dev);
  114. info->cpu_freq = plat->freq_mhz * 1000;
  115. info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
  116. return 0;
  117. }
  118. static int cpu_imx_get_count(const struct udevice *dev)
  119. {
  120. ofnode node;
  121. int num = 0;
  122. ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
  123. const char *device_type;
  124. if (!ofnode_is_available(node))
  125. continue;
  126. device_type = ofnode_read_string(node, "device_type");
  127. if (!device_type)
  128. continue;
  129. if (!strcmp(device_type, "cpu"))
  130. num++;
  131. }
  132. return num;
  133. }
  134. static int cpu_imx_get_vendor(const struct udevice *dev, char *buf, int size)
  135. {
  136. snprintf(buf, size, "NXP");
  137. return 0;
  138. }
  139. static int cpu_imx_is_current(struct udevice *dev)
  140. {
  141. struct cpu_imx_plat *plat = dev_get_plat(dev);
  142. if (plat->mpidr == (read_mpidr() & 0xffff))
  143. return 1;
  144. return 0;
  145. }
  146. static const struct cpu_ops cpu_imx8_ops = {
  147. .get_desc = cpu_imx_get_desc,
  148. .get_info = cpu_imx_get_info,
  149. .get_count = cpu_imx_get_count,
  150. .get_vendor = cpu_imx_get_vendor,
  151. .is_current = cpu_imx_is_current,
  152. };
  153. static const struct udevice_id cpu_imx8_ids[] = {
  154. { .compatible = "arm,cortex-a35" },
  155. { .compatible = "arm,cortex-a53" },
  156. { .compatible = "arm,cortex-a72" },
  157. { }
  158. };
  159. static ulong imx8_get_cpu_rate(struct udevice *dev)
  160. {
  161. struct cpu_imx_plat *plat = dev_get_plat(dev);
  162. ulong rate;
  163. int ret;
  164. ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
  165. (sc_pm_clock_rate_t *)&rate);
  166. if (ret) {
  167. printf("Could not read CPU frequency: %d\n", ret);
  168. return 0;
  169. }
  170. return rate;
  171. }
  172. static int imx8_cpu_probe(struct udevice *dev)
  173. {
  174. struct cpu_imx_plat *plat = dev_get_plat(dev);
  175. u32 cpurev;
  176. set_core_data(dev);
  177. cpurev = get_cpu_rev();
  178. plat->cpurev = cpurev;
  179. plat->rev = get_imx8_rev(cpurev & 0xFFF);
  180. plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
  181. plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000;
  182. plat->mpidr = dev_read_addr(dev);
  183. if (plat->mpidr == FDT_ADDR_T_NONE) {
  184. printf("%s: Failed to get CPU reg property\n", __func__);
  185. return -EINVAL;
  186. }
  187. return 0;
  188. }
  189. U_BOOT_DRIVER(cpu_imx8_drv) = {
  190. .name = "imx8x_cpu",
  191. .id = UCLASS_CPU,
  192. .of_match = cpu_imx8_ids,
  193. .ops = &cpu_imx8_ops,
  194. .probe = imx8_cpu_probe,
  195. .plat_auto = sizeof(struct cpu_imx_plat),
  196. .flags = DM_FLAG_PRE_RELOC,
  197. };