clk-arria10.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Marek Vasut <marex@denx.de>
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <asm/io.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <dm/device_compat.h>
  11. #include <dm/devres.h>
  12. #include <dm/lists.h>
  13. #include <dm/util.h>
  14. #include <linux/bitops.h>
  15. #include <asm/arch/clock_manager.h>
  16. enum socfpga_a10_clk_type {
  17. SOCFPGA_A10_CLK_MAIN_PLL,
  18. SOCFPGA_A10_CLK_PER_PLL,
  19. SOCFPGA_A10_CLK_PERIP_CLK,
  20. SOCFPGA_A10_CLK_GATE_CLK,
  21. SOCFPGA_A10_CLK_UNKNOWN_CLK,
  22. };
  23. struct socfpga_a10_clk_plat {
  24. enum socfpga_a10_clk_type type;
  25. struct clk_bulk clks;
  26. u32 regs;
  27. /* Fixed divider */
  28. u16 fix_div;
  29. /* Control register */
  30. u16 ctl_reg;
  31. /* Divider register */
  32. u16 div_reg;
  33. u8 div_len;
  34. u8 div_off;
  35. /* Clock gating register */
  36. u16 gate_reg;
  37. u8 gate_bit;
  38. };
  39. static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk)
  40. {
  41. struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
  42. u32 reg, maxval;
  43. if (plat->clks.count == 0)
  44. return 0;
  45. if (plat->clks.count == 1) {
  46. *upclk = &plat->clks.clks[0];
  47. return 0;
  48. }
  49. if (!plat->ctl_reg) {
  50. dev_err(clk->dev, "Invalid control register\n");
  51. return -EINVAL;
  52. }
  53. reg = readl(plat->regs + plat->ctl_reg);
  54. /* Assume PLLs are ON for now */
  55. if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) {
  56. reg = (reg >> 8) & 0x3;
  57. maxval = 2;
  58. } else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) {
  59. reg = (reg >> 8) & 0x3;
  60. maxval = 3;
  61. } else {
  62. reg = (reg >> 16) & 0x7;
  63. maxval = 4;
  64. }
  65. if (reg > maxval) {
  66. dev_err(clk->dev, "Invalid clock source\n");
  67. return -EINVAL;
  68. }
  69. *upclk = &plat->clks.clks[reg];
  70. return 0;
  71. }
  72. static int socfpga_a10_clk_endisable(struct clk *clk, bool enable)
  73. {
  74. struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
  75. struct clk *upclk = NULL;
  76. int ret;
  77. if (!enable && plat->gate_reg)
  78. clrbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit));
  79. ret = socfpga_a10_clk_get_upstream(clk, &upclk);
  80. if (ret)
  81. return ret;
  82. if (upclk) {
  83. if (enable)
  84. clk_enable(upclk);
  85. else
  86. clk_disable(upclk);
  87. }
  88. if (enable && plat->gate_reg)
  89. setbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit));
  90. return 0;
  91. }
  92. static int socfpga_a10_clk_enable(struct clk *clk)
  93. {
  94. return socfpga_a10_clk_endisable(clk, true);
  95. }
  96. static int socfpga_a10_clk_disable(struct clk *clk)
  97. {
  98. return socfpga_a10_clk_endisable(clk, false);
  99. }
  100. static ulong socfpga_a10_clk_get_rate(struct clk *clk)
  101. {
  102. struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
  103. struct clk *upclk = NULL;
  104. ulong rate = 0, reg, numer, denom;
  105. int ret;
  106. ret = socfpga_a10_clk_get_upstream(clk, &upclk);
  107. if (ret || !upclk)
  108. return 0;
  109. rate = clk_get_rate(upclk);
  110. if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) {
  111. reg = readl(plat->regs + plat->ctl_reg + 4); /* VCO1 */
  112. numer = reg & CLKMGR_MAINPLL_VCO1_NUMER_MSK;
  113. denom = (reg >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) &
  114. CLKMGR_MAINPLL_VCO1_DENOM_MSK;
  115. rate /= denom + 1;
  116. rate *= numer + 1;
  117. } else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) {
  118. reg = readl(plat->regs + plat->ctl_reg + 4); /* VCO1 */
  119. numer = reg & CLKMGR_PERPLL_VCO1_NUMER_MSK;
  120. denom = (reg >> CLKMGR_PERPLL_VCO1_DENOM_LSB) &
  121. CLKMGR_PERPLL_VCO1_DENOM_MSK;
  122. rate /= denom + 1;
  123. rate *= numer + 1;
  124. } else {
  125. rate /= plat->fix_div;
  126. if (plat->fix_div == 1 && plat->ctl_reg) {
  127. reg = readl(plat->regs + plat->ctl_reg);
  128. reg &= 0x7ff;
  129. rate /= reg + 1;
  130. }
  131. if (plat->div_reg) {
  132. reg = readl(plat->regs + plat->div_reg);
  133. reg >>= plat->div_off;
  134. reg &= (1 << plat->div_len) - 1;
  135. if (plat->type == SOCFPGA_A10_CLK_PERIP_CLK)
  136. rate /= reg + 1;
  137. if (plat->type == SOCFPGA_A10_CLK_GATE_CLK)
  138. rate /= 1 << reg;
  139. }
  140. }
  141. return rate;
  142. }
  143. static struct clk_ops socfpga_a10_clk_ops = {
  144. .enable = socfpga_a10_clk_enable,
  145. .disable = socfpga_a10_clk_disable,
  146. .get_rate = socfpga_a10_clk_get_rate,
  147. };
  148. /*
  149. * This workaround tries to fix the massively broken generated "handoff" DT,
  150. * which contains duplicate clock nodes without any connection to the clock
  151. * manager DT node. Yet, those "handoff" DT nodes contain configuration of
  152. * the fixed input clock of the Arria10 which are missing from the base DT
  153. * for Arria10.
  154. *
  155. * This workaround sets up upstream clock for the fixed input clocks of the
  156. * A10 described in the base DT such that they map to the fixed clock from
  157. * the "handoff" DT. This does not fully match how the clock look on the
  158. * A10, but it is the least intrusive way to fix this mess.
  159. */
  160. static void socfpga_a10_handoff_workaround(struct udevice *dev)
  161. {
  162. struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
  163. const void *fdt = gd->fdt_blob;
  164. struct clk_bulk *bulk = &plat->clks;
  165. int i, ret, offset = dev_of_offset(dev);
  166. static const char * const socfpga_a10_fixedclk_map[] = {
  167. "osc1", "altera_arria10_hps_eosc1",
  168. "cb_intosc_ls_clk", "altera_arria10_hps_cb_intosc_ls",
  169. "f2s_free_clk", "altera_arria10_hps_f2h_free",
  170. };
  171. if (fdt_node_check_compatible(fdt, offset, "fixed-clock"))
  172. return;
  173. for (i = 0; i < ARRAY_SIZE(socfpga_a10_fixedclk_map); i += 2)
  174. if (!strcmp(dev->name, socfpga_a10_fixedclk_map[i]))
  175. break;
  176. if (i == ARRAY_SIZE(socfpga_a10_fixedclk_map))
  177. return;
  178. ret = uclass_get_device_by_name(UCLASS_CLK,
  179. socfpga_a10_fixedclk_map[i + 1], &dev);
  180. if (ret)
  181. return;
  182. bulk->count = 1;
  183. bulk->clks = devm_kcalloc(dev, bulk->count,
  184. sizeof(struct clk), GFP_KERNEL);
  185. if (!bulk->clks)
  186. return;
  187. ret = clk_request(dev, &bulk->clks[0]);
  188. if (ret)
  189. free(bulk->clks);
  190. }
  191. static int socfpga_a10_clk_bind(struct udevice *dev)
  192. {
  193. const void *fdt = gd->fdt_blob;
  194. int offset = dev_of_offset(dev);
  195. bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
  196. const char *name;
  197. int ret;
  198. for (offset = fdt_first_subnode(fdt, offset);
  199. offset > 0;
  200. offset = fdt_next_subnode(fdt, offset)) {
  201. name = fdt_get_name(fdt, offset, NULL);
  202. if (!name)
  203. return -EINVAL;
  204. if (!strcmp(name, "clocks")) {
  205. offset = fdt_first_subnode(fdt, offset);
  206. name = fdt_get_name(fdt, offset, NULL);
  207. if (!name)
  208. return -EINVAL;
  209. }
  210. /* Filter out supported sub-clock */
  211. if (fdt_node_check_compatible(fdt, offset,
  212. "altr,socfpga-a10-pll-clock") &&
  213. fdt_node_check_compatible(fdt, offset,
  214. "altr,socfpga-a10-perip-clk") &&
  215. fdt_node_check_compatible(fdt, offset,
  216. "altr,socfpga-a10-gate-clk") &&
  217. fdt_node_check_compatible(fdt, offset, "fixed-clock"))
  218. continue;
  219. if (pre_reloc_only &&
  220. !ofnode_pre_reloc(offset_to_ofnode(offset)))
  221. continue;
  222. ret = device_bind_driver_to_node(dev, "clk-a10", name,
  223. offset_to_ofnode(offset),
  224. NULL);
  225. if (ret)
  226. return ret;
  227. }
  228. return 0;
  229. }
  230. static int socfpga_a10_clk_probe(struct udevice *dev)
  231. {
  232. struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
  233. struct socfpga_a10_clk_plat *pplat;
  234. struct udevice *pdev;
  235. const void *fdt = gd->fdt_blob;
  236. int offset = dev_of_offset(dev);
  237. clk_get_bulk(dev, &plat->clks);
  238. socfpga_a10_handoff_workaround(dev);
  239. if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
  240. plat->regs = dev_read_addr(dev);
  241. } else {
  242. pdev = dev_get_parent(dev);
  243. if (!pdev)
  244. return -ENODEV;
  245. pplat = dev_get_plat(pdev);
  246. if (!pplat)
  247. return -EINVAL;
  248. plat->ctl_reg = dev_read_u32_default(dev, "reg", 0x0);
  249. plat->regs = pplat->regs;
  250. }
  251. if (!fdt_node_check_compatible(fdt, offset,
  252. "altr,socfpga-a10-pll-clock")) {
  253. /* Main PLL has 3 upstream clock */
  254. if (plat->clks.count == 3)
  255. plat->type = SOCFPGA_A10_CLK_MAIN_PLL;
  256. else
  257. plat->type = SOCFPGA_A10_CLK_PER_PLL;
  258. } else if (!fdt_node_check_compatible(fdt, offset,
  259. "altr,socfpga-a10-perip-clk")) {
  260. plat->type = SOCFPGA_A10_CLK_PERIP_CLK;
  261. } else if (!fdt_node_check_compatible(fdt, offset,
  262. "altr,socfpga-a10-gate-clk")) {
  263. plat->type = SOCFPGA_A10_CLK_GATE_CLK;
  264. } else {
  265. plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
  266. }
  267. return 0;
  268. }
  269. static int socfpga_a10_of_to_plat(struct udevice *dev)
  270. {
  271. struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
  272. unsigned int divreg[3], gatereg[2];
  273. int ret;
  274. plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
  275. plat->fix_div = dev_read_u32_default(dev, "fixed-divider", 1);
  276. ret = dev_read_u32_array(dev, "div-reg", divreg, ARRAY_SIZE(divreg));
  277. if (!ret) {
  278. plat->div_reg = divreg[0];
  279. plat->div_len = divreg[2];
  280. plat->div_off = divreg[1];
  281. }
  282. ret = dev_read_u32_array(dev, "clk-gate", gatereg, ARRAY_SIZE(gatereg));
  283. if (!ret) {
  284. plat->gate_reg = gatereg[0];
  285. plat->gate_bit = gatereg[1];
  286. }
  287. return 0;
  288. }
  289. static const struct udevice_id socfpga_a10_clk_match[] = {
  290. { .compatible = "altr,clk-mgr" },
  291. {}
  292. };
  293. U_BOOT_DRIVER(socfpga_a10_clk) = {
  294. .name = "clk-a10",
  295. .id = UCLASS_CLK,
  296. .of_match = socfpga_a10_clk_match,
  297. .ops = &socfpga_a10_clk_ops,
  298. .bind = socfpga_a10_clk_bind,
  299. .probe = socfpga_a10_clk_probe,
  300. .of_to_plat = socfpga_a10_of_to_plat,
  301. .plat_auto = sizeof(struct socfpga_a10_clk_plat),
  302. };