board.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM335X based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <env.h>
  12. #include <errno.h>
  13. #include <image.h>
  14. #include <init.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <spl.h>
  18. #include <serial.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/hardware.h>
  21. #include <asm/arch/omap.h>
  22. #include <asm/arch/ddr_defs.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/clk_synthesizer.h>
  25. #include <asm/arch/gpio.h>
  26. #include <asm/arch/mmc_host_def.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <asm/arch/mem.h>
  29. #include <asm/io.h>
  30. #include <asm/emif.h>
  31. #include <asm/gpio.h>
  32. #include <asm/omap_common.h>
  33. #include <asm/omap_sec_common.h>
  34. #include <asm/omap_mmc.h>
  35. #include <i2c.h>
  36. #include <miiphy.h>
  37. #include <cpsw.h>
  38. #include <linux/bitops.h>
  39. #include <linux/delay.h>
  40. #include <power/tps65217.h>
  41. #include <power/tps65910.h>
  42. #include <env_internal.h>
  43. #include <watchdog.h>
  44. #include "../common/board_detect.h"
  45. #include "board.h"
  46. DECLARE_GLOBAL_DATA_PTR;
  47. /* GPIO that controls power to DDR on EVM-SK */
  48. #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
  49. #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
  50. #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
  51. #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
  52. #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
  53. #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
  54. #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
  55. #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
  56. #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
  57. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  58. #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  59. #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  60. #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  61. #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  62. #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
  63. #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
  64. /*
  65. * Read header information from EEPROM into global structure.
  66. */
  67. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  68. void do_board_detect(void)
  69. {
  70. enable_i2c0_pin_mux();
  71. #ifndef CONFIG_DM_I2C
  72. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  73. #endif
  74. if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  75. CONFIG_EEPROM_CHIP_ADDRESS))
  76. printf("ti_i2c_eeprom_init failed\n");
  77. }
  78. #endif
  79. #ifndef CONFIG_DM_SERIAL
  80. struct serial_device *default_serial_console(void)
  81. {
  82. if (board_is_icev2())
  83. return &eserial4_device;
  84. else
  85. return &eserial1_device;
  86. }
  87. #endif
  88. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  89. static const struct ddr_data ddr2_data = {
  90. .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  91. .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  92. .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  93. };
  94. static const struct cmd_control ddr2_cmd_ctrl_data = {
  95. .cmd0csratio = MT47H128M16RT25E_RATIO,
  96. .cmd1csratio = MT47H128M16RT25E_RATIO,
  97. .cmd2csratio = MT47H128M16RT25E_RATIO,
  98. };
  99. static const struct emif_regs ddr2_emif_reg_data = {
  100. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  101. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  102. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  103. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  104. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  105. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  106. };
  107. static const struct emif_regs ddr2_evm_emif_reg_data = {
  108. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  109. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  110. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  111. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  112. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  113. .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
  114. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  115. };
  116. static const struct ddr_data ddr3_data = {
  117. .datardsratio0 = MT41J128MJT125_RD_DQS,
  118. .datawdsratio0 = MT41J128MJT125_WR_DQS,
  119. .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
  120. .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
  121. };
  122. static const struct ddr_data ddr3_beagleblack_data = {
  123. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  124. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  125. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  126. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  127. };
  128. static const struct ddr_data ddr3_evm_data = {
  129. .datardsratio0 = MT41J512M8RH125_RD_DQS,
  130. .datawdsratio0 = MT41J512M8RH125_WR_DQS,
  131. .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
  132. .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
  133. };
  134. static const struct ddr_data ddr3_icev2_data = {
  135. .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
  136. .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
  137. .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
  138. .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
  139. };
  140. static const struct cmd_control ddr3_cmd_ctrl_data = {
  141. .cmd0csratio = MT41J128MJT125_RATIO,
  142. .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
  143. .cmd1csratio = MT41J128MJT125_RATIO,
  144. .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
  145. .cmd2csratio = MT41J128MJT125_RATIO,
  146. .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
  147. };
  148. static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
  149. .cmd0csratio = MT41K256M16HA125E_RATIO,
  150. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  151. .cmd1csratio = MT41K256M16HA125E_RATIO,
  152. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  153. .cmd2csratio = MT41K256M16HA125E_RATIO,
  154. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  155. };
  156. static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
  157. .cmd0csratio = MT41J512M8RH125_RATIO,
  158. .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  159. .cmd1csratio = MT41J512M8RH125_RATIO,
  160. .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  161. .cmd2csratio = MT41J512M8RH125_RATIO,
  162. .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  163. };
  164. static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
  165. .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
  166. .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  167. .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
  168. .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  169. .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
  170. .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  171. };
  172. static struct emif_regs ddr3_emif_reg_data = {
  173. .sdram_config = MT41J128MJT125_EMIF_SDCFG,
  174. .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
  175. .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
  176. .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
  177. .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
  178. .zq_config = MT41J128MJT125_ZQ_CFG,
  179. .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
  180. PHY_EN_DYN_PWRDN,
  181. };
  182. static struct emif_regs ddr3_beagleblack_emif_reg_data = {
  183. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  184. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  185. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  186. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  187. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  188. .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
  189. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  190. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  191. };
  192. static struct emif_regs ddr3_evm_emif_reg_data = {
  193. .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
  194. .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
  195. .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
  196. .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
  197. .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
  198. .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
  199. .zq_config = MT41J512M8RH125_ZQ_CFG,
  200. .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
  201. PHY_EN_DYN_PWRDN,
  202. };
  203. static struct emif_regs ddr3_icev2_emif_reg_data = {
  204. .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
  205. .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
  206. .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
  207. .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
  208. .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
  209. .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
  210. .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
  211. PHY_EN_DYN_PWRDN,
  212. };
  213. #ifdef CONFIG_SPL_OS_BOOT
  214. int spl_start_uboot(void)
  215. {
  216. #ifdef CONFIG_SPL_SERIAL_SUPPORT
  217. /* break into full u-boot on 'c' */
  218. if (serial_tstc() && serial_getc() == 'c')
  219. return 1;
  220. #endif
  221. #ifdef CONFIG_SPL_ENV_SUPPORT
  222. env_init();
  223. env_load();
  224. if (env_get_yesno("boot_os") != 1)
  225. return 1;
  226. #endif
  227. return 0;
  228. }
  229. #endif
  230. const struct dpll_params *get_dpll_ddr_params(void)
  231. {
  232. int ind = get_sys_clk_index();
  233. if (board_is_evm_sk())
  234. return &dpll_ddr3_303MHz[ind];
  235. else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
  236. return &dpll_ddr3_400MHz[ind];
  237. else if (board_is_evm_15_or_later())
  238. return &dpll_ddr3_303MHz[ind];
  239. else
  240. return &dpll_ddr2_266MHz[ind];
  241. }
  242. static u8 bone_not_connected_to_ac_power(void)
  243. {
  244. if (board_is_bone()) {
  245. uchar pmic_status_reg;
  246. if (tps65217_reg_read(TPS65217_STATUS,
  247. &pmic_status_reg))
  248. return 1;
  249. if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
  250. puts("No AC power, switching to default OPP\n");
  251. return 1;
  252. }
  253. }
  254. return 0;
  255. }
  256. const struct dpll_params *get_dpll_mpu_params(void)
  257. {
  258. int ind = get_sys_clk_index();
  259. int freq = am335x_get_efuse_mpu_max_freq(cdev);
  260. if (bone_not_connected_to_ac_power())
  261. freq = MPUPLL_M_600;
  262. if (board_is_pb() || board_is_bone_lt())
  263. freq = MPUPLL_M_1000;
  264. switch (freq) {
  265. case MPUPLL_M_1000:
  266. return &dpll_mpu_opp[ind][5];
  267. case MPUPLL_M_800:
  268. return &dpll_mpu_opp[ind][4];
  269. case MPUPLL_M_720:
  270. return &dpll_mpu_opp[ind][3];
  271. case MPUPLL_M_600:
  272. return &dpll_mpu_opp[ind][2];
  273. case MPUPLL_M_500:
  274. return &dpll_mpu_opp100;
  275. case MPUPLL_M_300:
  276. return &dpll_mpu_opp[ind][0];
  277. }
  278. return &dpll_mpu_opp[ind][0];
  279. }
  280. static void scale_vcores_bone(int freq)
  281. {
  282. int usb_cur_lim, mpu_vdd;
  283. /*
  284. * Only perform PMIC configurations if board rev > A1
  285. * on Beaglebone White
  286. */
  287. if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
  288. return;
  289. #ifndef CONFIG_DM_I2C
  290. if (i2c_probe(TPS65217_CHIP_PM))
  291. return;
  292. #else
  293. if (power_tps65217_init(0))
  294. return;
  295. #endif
  296. /*
  297. * On Beaglebone White we need to ensure we have AC power
  298. * before increasing the frequency.
  299. */
  300. if (bone_not_connected_to_ac_power())
  301. freq = MPUPLL_M_600;
  302. /*
  303. * Override what we have detected since we know if we have
  304. * a Beaglebone Black it supports 1GHz.
  305. */
  306. if (board_is_pb() || board_is_bone_lt())
  307. freq = MPUPLL_M_1000;
  308. switch (freq) {
  309. case MPUPLL_M_1000:
  310. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  311. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  312. break;
  313. case MPUPLL_M_800:
  314. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  315. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  316. break;
  317. case MPUPLL_M_720:
  318. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
  319. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  320. break;
  321. case MPUPLL_M_600:
  322. case MPUPLL_M_500:
  323. case MPUPLL_M_300:
  324. default:
  325. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
  326. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  327. break;
  328. }
  329. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  330. TPS65217_POWER_PATH,
  331. usb_cur_lim,
  332. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  333. puts("tps65217_reg_write failure\n");
  334. /* Set DCDC3 (CORE) voltage to 1.10V */
  335. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  336. TPS65217_DCDC_VOLT_SEL_1100MV)) {
  337. puts("tps65217_voltage_update failure\n");
  338. return;
  339. }
  340. /* Set DCDC2 (MPU) voltage */
  341. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  342. puts("tps65217_voltage_update failure\n");
  343. return;
  344. }
  345. /*
  346. * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
  347. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
  348. */
  349. if (board_is_bone()) {
  350. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  351. TPS65217_DEFLS1,
  352. TPS65217_LDO_VOLTAGE_OUT_3_3,
  353. TPS65217_LDO_MASK))
  354. puts("tps65217_reg_write failure\n");
  355. } else {
  356. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  357. TPS65217_DEFLS1,
  358. TPS65217_LDO_VOLTAGE_OUT_1_8,
  359. TPS65217_LDO_MASK))
  360. puts("tps65217_reg_write failure\n");
  361. }
  362. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  363. TPS65217_DEFLS2,
  364. TPS65217_LDO_VOLTAGE_OUT_3_3,
  365. TPS65217_LDO_MASK))
  366. puts("tps65217_reg_write failure\n");
  367. }
  368. void scale_vcores_generic(int freq)
  369. {
  370. int sil_rev, mpu_vdd;
  371. /*
  372. * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
  373. * MPU frequencies we support we use a CORE voltage of
  374. * 1.10V. For MPU voltage we need to switch based on
  375. * the frequency we are running at.
  376. */
  377. #ifndef CONFIG_DM_I2C
  378. if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
  379. return;
  380. #else
  381. if (power_tps65910_init(0))
  382. return;
  383. #endif
  384. /*
  385. * Depending on MPU clock and PG we will need a different
  386. * VDD to drive at that speed.
  387. */
  388. sil_rev = readl(&cdev->deviceid) >> 28;
  389. mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
  390. /* Tell the TPS65910 to use i2c */
  391. tps65910_set_i2c_control();
  392. /* First update MPU voltage. */
  393. if (tps65910_voltage_update(MPU, mpu_vdd))
  394. return;
  395. /* Second, update the CORE voltage. */
  396. if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
  397. return;
  398. }
  399. void gpi2c_init(void)
  400. {
  401. /* When needed to be invoked prior to BSS initialization */
  402. static bool first_time = true;
  403. if (first_time) {
  404. enable_i2c0_pin_mux();
  405. #ifndef CONFIG_DM_I2C
  406. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  407. CONFIG_SYS_OMAP24_I2C_SLAVE);
  408. #endif
  409. first_time = false;
  410. }
  411. }
  412. void scale_vcores(void)
  413. {
  414. int freq;
  415. gpi2c_init();
  416. freq = am335x_get_efuse_mpu_max_freq(cdev);
  417. if (board_is_beaglebonex())
  418. scale_vcores_bone(freq);
  419. else
  420. scale_vcores_generic(freq);
  421. }
  422. void set_uart_mux_conf(void)
  423. {
  424. #if CONFIG_CONS_INDEX == 1
  425. enable_uart0_pin_mux();
  426. #elif CONFIG_CONS_INDEX == 2
  427. enable_uart1_pin_mux();
  428. #elif CONFIG_CONS_INDEX == 3
  429. enable_uart2_pin_mux();
  430. #elif CONFIG_CONS_INDEX == 4
  431. enable_uart3_pin_mux();
  432. #elif CONFIG_CONS_INDEX == 5
  433. enable_uart4_pin_mux();
  434. #elif CONFIG_CONS_INDEX == 6
  435. enable_uart5_pin_mux();
  436. #endif
  437. }
  438. void set_mux_conf_regs(void)
  439. {
  440. enable_board_pin_mux();
  441. }
  442. const struct ctrl_ioregs ioregs_evmsk = {
  443. .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  444. .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  445. .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
  446. .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  447. .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  448. };
  449. const struct ctrl_ioregs ioregs_bonelt = {
  450. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  451. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  452. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  453. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  454. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  455. };
  456. const struct ctrl_ioregs ioregs_evm15 = {
  457. .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  458. .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  459. .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  460. .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  461. .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  462. };
  463. const struct ctrl_ioregs ioregs = {
  464. .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  465. .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  466. .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  467. .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  468. .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  469. };
  470. void sdram_init(void)
  471. {
  472. if (board_is_evm_sk()) {
  473. /*
  474. * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
  475. * This is safe enough to do on older revs.
  476. */
  477. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  478. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  479. }
  480. if (board_is_icev2()) {
  481. gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
  482. gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
  483. }
  484. if (board_is_evm_sk())
  485. config_ddr(303, &ioregs_evmsk, &ddr3_data,
  486. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  487. else if (board_is_pb() || board_is_bone_lt())
  488. config_ddr(400, &ioregs_bonelt,
  489. &ddr3_beagleblack_data,
  490. &ddr3_beagleblack_cmd_ctrl_data,
  491. &ddr3_beagleblack_emif_reg_data, 0);
  492. else if (board_is_evm_15_or_later())
  493. config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
  494. &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
  495. else if (board_is_icev2())
  496. config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
  497. &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
  498. 0);
  499. else if (board_is_gp_evm())
  500. config_ddr(266, &ioregs, &ddr2_data,
  501. &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
  502. else
  503. config_ddr(266, &ioregs, &ddr2_data,
  504. &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
  505. }
  506. #endif
  507. #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
  508. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
  509. static void request_and_set_gpio(int gpio, char *name, int val)
  510. {
  511. int ret;
  512. ret = gpio_request(gpio, name);
  513. if (ret < 0) {
  514. printf("%s: Unable to request %s\n", __func__, name);
  515. return;
  516. }
  517. ret = gpio_direction_output(gpio, 0);
  518. if (ret < 0) {
  519. printf("%s: Unable to set %s as output\n", __func__, name);
  520. goto err_free_gpio;
  521. }
  522. gpio_set_value(gpio, val);
  523. return;
  524. err_free_gpio:
  525. gpio_free(gpio);
  526. }
  527. #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
  528. #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
  529. /**
  530. * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
  531. * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
  532. * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
  533. * give 50MHz output for Eth0 and 1.
  534. */
  535. static struct clk_synth cdce913_data = {
  536. .id = 0x81,
  537. .capacitor = 0x90,
  538. .mux = 0x6d,
  539. .pdiv2 = 0x2,
  540. .pdiv3 = 0x2,
  541. };
  542. #endif
  543. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
  544. defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
  545. #define MAX_CPSW_SLAVES 2
  546. /* At the moment, we do not want to stop booting for any failures here */
  547. int ft_board_setup(void *fdt, struct bd_info *bd)
  548. {
  549. const char *slave_path, *enet_name;
  550. int enetnode, slavenode, phynode;
  551. struct udevice *ethdev;
  552. char alias[16];
  553. u32 phy_id[2];
  554. int phy_addr;
  555. int i, ret;
  556. /* phy address fixup needed only on beagle bone family */
  557. if (!board_is_beaglebonex())
  558. goto done;
  559. for (i = 0; i < MAX_CPSW_SLAVES; i++) {
  560. sprintf(alias, "ethernet%d", i);
  561. slave_path = fdt_get_alias(fdt, alias);
  562. if (!slave_path)
  563. continue;
  564. slavenode = fdt_path_offset(fdt, slave_path);
  565. if (slavenode < 0)
  566. continue;
  567. enetnode = fdt_parent_offset(fdt, slavenode);
  568. enet_name = fdt_get_name(fdt, enetnode, NULL);
  569. ethdev = eth_get_dev_by_name(enet_name);
  570. if (!ethdev)
  571. continue;
  572. phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
  573. /* check for phy_id as well as phy-handle properties */
  574. ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
  575. phy_id, 2);
  576. if (ret == 2) {
  577. if (phy_id[1] != phy_addr) {
  578. printf("fixing up phy_id for %s, old: %d, new: %d\n",
  579. alias, phy_id[1], phy_addr);
  580. phy_id[0] = cpu_to_fdt32(phy_id[0]);
  581. phy_id[1] = cpu_to_fdt32(phy_addr);
  582. do_fixup_by_path(fdt, slave_path, "phy_id",
  583. phy_id, sizeof(phy_id), 0);
  584. }
  585. } else {
  586. phynode = fdtdec_lookup_phandle(fdt, slavenode,
  587. "phy-handle");
  588. if (phynode < 0)
  589. continue;
  590. ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
  591. if (ret < 0)
  592. continue;
  593. if (ret != phy_addr) {
  594. printf("fixing up phy-handle for %s, old: %d, new: %d\n",
  595. alias, ret, phy_addr);
  596. fdt_setprop_u32(fdt, phynode, "reg",
  597. cpu_to_fdt32(phy_addr));
  598. }
  599. }
  600. }
  601. done:
  602. return 0;
  603. }
  604. #endif
  605. /*
  606. * Basic board specific setup. Pinmux has been handled already.
  607. */
  608. int board_init(void)
  609. {
  610. #if defined(CONFIG_HW_WATCHDOG)
  611. hw_watchdog_init();
  612. #endif
  613. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  614. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  615. gpmc_init();
  616. #endif
  617. #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
  618. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
  619. if (board_is_icev2()) {
  620. int rv;
  621. u32 reg;
  622. REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
  623. /* Make J19 status available on GPIO1_26 */
  624. REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
  625. REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
  626. /*
  627. * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
  628. * jumpers near the port. Read the jumper value and set
  629. * the pinmux, external mux and PHY clock accordingly.
  630. * As jumper line is overridden by PHY RX_DV pin immediately
  631. * after bootstrap (power-up/reset), we need to sample
  632. * it during PHY reset using GPIO rising edge detection.
  633. */
  634. REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
  635. /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
  636. reg = readl(GPIO0_RISINGDETECT) | BIT(11);
  637. writel(reg, GPIO0_RISINGDETECT);
  638. reg = readl(GPIO1_RISINGDETECT) | BIT(26);
  639. writel(reg, GPIO1_RISINGDETECT);
  640. /* Reset PHYs to capture the Jumper setting */
  641. gpio_set_value(GPIO_PHY_RESET, 0);
  642. udelay(2); /* PHY datasheet states 1uS min. */
  643. gpio_set_value(GPIO_PHY_RESET, 1);
  644. reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
  645. if (reg) {
  646. writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
  647. /* RMII mode */
  648. printf("ETH0, CPSW\n");
  649. } else {
  650. /* MII mode */
  651. printf("ETH0, PRU\n");
  652. cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
  653. }
  654. reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
  655. if (reg) {
  656. writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
  657. /* RMII mode */
  658. printf("ETH1, CPSW\n");
  659. gpio_set_value(GPIO_MUX_MII_CTRL, 1);
  660. } else {
  661. /* MII mode */
  662. printf("ETH1, PRU\n");
  663. cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
  664. }
  665. /* disable rising edge IRQs */
  666. reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
  667. writel(reg, GPIO0_RISINGDETECT);
  668. reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
  669. writel(reg, GPIO1_RISINGDETECT);
  670. rv = setup_clock_synthesizer(&cdce913_data);
  671. if (rv) {
  672. printf("Clock synthesizer setup failed %d\n", rv);
  673. return rv;
  674. }
  675. /* reset PHYs */
  676. gpio_set_value(GPIO_PHY_RESET, 0);
  677. udelay(2); /* PHY datasheet states 1uS min. */
  678. gpio_set_value(GPIO_PHY_RESET, 1);
  679. }
  680. #endif
  681. return 0;
  682. }
  683. #ifdef CONFIG_BOARD_LATE_INIT
  684. int board_late_init(void)
  685. {
  686. struct udevice *dev;
  687. #if !defined(CONFIG_SPL_BUILD)
  688. uint8_t mac_addr[6];
  689. uint32_t mac_hi, mac_lo;
  690. #endif
  691. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  692. char *name = NULL;
  693. if (board_is_bone_lt()) {
  694. /* BeagleBoard.org BeagleBone Black Wireless: */
  695. if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
  696. name = "BBBW";
  697. }
  698. /* SeeedStudio BeagleBone Green Wireless */
  699. if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
  700. name = "BBGW";
  701. }
  702. /* BeagleBoard.org BeagleBone Blue */
  703. if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
  704. name = "BBBL";
  705. }
  706. }
  707. if (board_is_bbg1())
  708. name = "BBG1";
  709. if (board_is_bben())
  710. name = "BBEN";
  711. set_board_info_env(name);
  712. /*
  713. * Default FIT boot on HS devices. Non FIT images are not allowed
  714. * on HS devices.
  715. */
  716. if (get_device_type() == HS_DEVICE)
  717. env_set("boot_fit", "1");
  718. #endif
  719. #if !defined(CONFIG_SPL_BUILD)
  720. /* try reading mac address from efuse */
  721. mac_lo = readl(&cdev->macid0l);
  722. mac_hi = readl(&cdev->macid0h);
  723. mac_addr[0] = mac_hi & 0xFF;
  724. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  725. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  726. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  727. mac_addr[4] = mac_lo & 0xFF;
  728. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  729. if (!env_get("ethaddr")) {
  730. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  731. if (is_valid_ethaddr(mac_addr))
  732. eth_env_set_enetaddr("ethaddr", mac_addr);
  733. }
  734. mac_lo = readl(&cdev->macid1l);
  735. mac_hi = readl(&cdev->macid1h);
  736. mac_addr[0] = mac_hi & 0xFF;
  737. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  738. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  739. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  740. mac_addr[4] = mac_lo & 0xFF;
  741. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  742. if (!env_get("eth1addr")) {
  743. if (is_valid_ethaddr(mac_addr))
  744. eth_env_set_enetaddr("eth1addr", mac_addr);
  745. }
  746. #endif
  747. if (!env_get("serial#")) {
  748. char *board_serial = env_get("board_serial");
  749. char *ethaddr = env_get("ethaddr");
  750. if (!board_serial || !strncmp(board_serial, "unknown", 7))
  751. env_set("serial#", ethaddr);
  752. else
  753. env_set("serial#", board_serial);
  754. }
  755. /* Just probe the potentially supported cdce913 device */
  756. uclass_get_device(UCLASS_CLK, 0, &dev);
  757. return 0;
  758. }
  759. #endif
  760. /* CPSW plat */
  761. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  762. struct cpsw_slave_data slave_data[] = {
  763. {
  764. .slave_reg_ofs = CPSW_SLAVE0_OFFSET,
  765. .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
  766. .phy_addr = 0,
  767. },
  768. {
  769. .slave_reg_ofs = CPSW_SLAVE1_OFFSET,
  770. .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
  771. .phy_addr = 1,
  772. },
  773. };
  774. struct cpsw_platform_data am335_eth_data = {
  775. .cpsw_base = CPSW_BASE,
  776. .version = CPSW_CTRL_VERSION_2,
  777. .bd_ram_ofs = CPSW_BD_OFFSET,
  778. .ale_reg_ofs = CPSW_ALE_OFFSET,
  779. .cpdma_reg_ofs = CPSW_CPDMA_OFFSET,
  780. .mdio_div = CPSW_MDIO_DIV,
  781. .host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
  782. .channels = 8,
  783. .slaves = 2,
  784. .slave_data = slave_data,
  785. .ale_entries = 1024,
  786. .mac_control = 0x20,
  787. .active_slave = 0,
  788. .mdio_base = 0x4a101000,
  789. .gmii_sel = 0x44e10650,
  790. .phy_sel_compat = "ti,am3352-cpsw-phy-sel",
  791. .syscon_addr = 0x44e10630,
  792. .macid_sel_compat = "cpsw,am33xx",
  793. };
  794. struct eth_pdata cpsw_pdata = {
  795. .iobase = 0x4a100000,
  796. .phy_interface = 0,
  797. .priv_pdata = &am335_eth_data,
  798. };
  799. U_BOOT_DEVICE(am335x_eth) = {
  800. .name = "eth_cpsw",
  801. .plat = &cpsw_pdata,
  802. };
  803. #endif
  804. #ifdef CONFIG_SPL_LOAD_FIT
  805. int board_fit_config_name_match(const char *name)
  806. {
  807. if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
  808. return 0;
  809. else if (board_is_bone() && !strcmp(name, "am335x-bone"))
  810. return 0;
  811. else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
  812. return 0;
  813. else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
  814. return 0;
  815. else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
  816. return 0;
  817. else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
  818. return 0;
  819. else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
  820. return 0;
  821. else
  822. return -1;
  823. }
  824. #endif
  825. #ifdef CONFIG_TI_SECURE_DEVICE
  826. void board_fit_image_post_process(void **p_image, size_t *p_size)
  827. {
  828. secure_boot_verify_image(p_image, p_size);
  829. }
  830. #endif
  831. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  832. static const struct omap_hsmmc_plat am335x_mmc0_plat = {
  833. .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
  834. .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
  835. .cfg.f_min = 400000,
  836. .cfg.f_max = 52000000,
  837. .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
  838. .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  839. };
  840. U_BOOT_DEVICE(am335x_mmc0) = {
  841. .name = "omap_hsmmc",
  842. .plat = &am335x_mmc0_plat,
  843. };
  844. static const struct omap_hsmmc_plat am335x_mmc1_plat = {
  845. .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
  846. .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
  847. .cfg.f_min = 400000,
  848. .cfg.f_max = 52000000,
  849. .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
  850. .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  851. };
  852. U_BOOT_DEVICE(am335x_mmc1) = {
  853. .name = "omap_hsmmc",
  854. .plat = &am335x_mmc1_plat,
  855. };
  856. #endif