igep00x0.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * ISEE 2007 SL, <www.iseebcn.com>
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <init.h>
  9. #include <malloc.h>
  10. #include <net.h>
  11. #include <status_led.h>
  12. #include <dm.h>
  13. #include <ns16550.h>
  14. #include <twl4030.h>
  15. #include <netdev.h>
  16. #include <spl.h>
  17. #include <asm/gpio.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/mem.h>
  20. #include <asm/arch/mmc_host_def.h>
  21. #include <asm/arch/mux.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <linux/delay.h>
  24. #include <linux/mtd/mtd.h>
  25. #include <linux/mtd/rawnand.h>
  26. #include <linux/mtd/onenand.h>
  27. #include <jffs2/load_kernel.h>
  28. #include <mtd_node.h>
  29. #include <fdt_support.h>
  30. #include "igep00x0.h"
  31. static const struct ns16550_plat igep_serial = {
  32. .base = OMAP34XX_UART3,
  33. .reg_shift = 2,
  34. .clock = V_NS16550_CLK,
  35. .fcr = UART_FCR_DEFVAL,
  36. };
  37. U_BOOT_DEVICE(igep_uart) = {
  38. "ns16550_serial",
  39. &igep_serial
  40. };
  41. /*
  42. * Routine: get_board_revision
  43. * Description: GPIO_28 and GPIO_129 are used to read board and revision from
  44. * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
  45. * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
  46. * this functionality is shared by USB HOST.
  47. * Once USB reset is applied, U-boot configures these pins as input pullup to
  48. * detect board and revision:
  49. * IGEP0020-RF = 0b00
  50. * IGEP0020-RC = 0b01
  51. * IGEP0030-RG = 0b10
  52. * IGEP0030-RE = 0b11
  53. */
  54. static int get_board_revision(void)
  55. {
  56. int revision;
  57. gpio_request(IGEP0030_USB_TRANSCEIVER_RESET,
  58. "igep0030_usb_transceiver_reset");
  59. gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0);
  60. gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection");
  61. gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION);
  62. revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION);
  63. gpio_free(GPIO_IGEP00X0_BOARD_DETECTION);
  64. gpio_request(GPIO_IGEP00X0_REVISION_DETECTION,
  65. "igep00x0_revision_detection");
  66. gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION);
  67. revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION);
  68. gpio_free(GPIO_IGEP00X0_REVISION_DETECTION);
  69. gpio_free(IGEP0030_USB_TRANSCEIVER_RESET);
  70. return revision;
  71. }
  72. int onenand_board_init(struct mtd_info *mtd)
  73. {
  74. if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
  75. struct onenand_chip *this = mtd->priv;
  76. this->base = (void *)CONFIG_SYS_ONENAND_BASE;
  77. return 0;
  78. }
  79. return 1;
  80. }
  81. #if defined(CONFIG_CMD_NET)
  82. static void reset_net_chip(int gpio)
  83. {
  84. if (!gpio_request(gpio, "eth nrst")) {
  85. gpio_direction_output(gpio, 1);
  86. udelay(1);
  87. gpio_set_value(gpio, 0);
  88. udelay(40);
  89. gpio_set_value(gpio, 1);
  90. mdelay(10);
  91. }
  92. }
  93. /*
  94. * Routine: setup_net_chip
  95. * Description: Setting up the configuration GPMC registers specific to the
  96. * Ethernet hardware.
  97. */
  98. static void setup_net_chip(void)
  99. {
  100. struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  101. static const u32 gpmc_lan_config[] = {
  102. NET_LAN9221_GPMC_CONFIG1,
  103. NET_LAN9221_GPMC_CONFIG2,
  104. NET_LAN9221_GPMC_CONFIG3,
  105. NET_LAN9221_GPMC_CONFIG4,
  106. NET_LAN9221_GPMC_CONFIG5,
  107. NET_LAN9221_GPMC_CONFIG6,
  108. };
  109. enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
  110. CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
  111. /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
  112. writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
  113. /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
  114. writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
  115. /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
  116. writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
  117. &ctrl_base->gpmc_nadv_ale);
  118. reset_net_chip(64);
  119. }
  120. int board_eth_init(struct bd_info *bis)
  121. {
  122. #ifdef CONFIG_SMC911X
  123. return smc911x_initialize(0, CONFIG_SMC911X_BASE);
  124. #else
  125. return 0;
  126. #endif
  127. }
  128. #else
  129. static inline void setup_net_chip(void) {}
  130. #endif
  131. #ifdef CONFIG_OF_BOARD_SETUP
  132. static int ft_enable_by_compatible(void *blob, char *compat, int enable)
  133. {
  134. int off = fdt_node_offset_by_compatible(blob, -1, compat);
  135. if (off < 0)
  136. return off;
  137. if (enable)
  138. fdt_status_okay(blob, off);
  139. else
  140. fdt_status_disabled(blob, off);
  141. return 0;
  142. }
  143. int ft_board_setup(void *blob, struct bd_info *bd)
  144. {
  145. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  146. static const struct node_info nodes[] = {
  147. { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
  148. { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
  149. };
  150. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  151. #endif
  152. ft_enable_by_compatible(blob, "ti,omap2-nand",
  153. gpmc_cs0_flash == MTD_DEV_TYPE_NAND);
  154. ft_enable_by_compatible(blob, "ti,omap2-onenand",
  155. gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND);
  156. return 0;
  157. }
  158. #endif
  159. void set_led(void)
  160. {
  161. switch (get_board_revision()) {
  162. case 0:
  163. case 1:
  164. gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led");
  165. gpio_direction_output(IGEP0020_GPIO_LED, 1);
  166. break;
  167. case 2:
  168. case 3:
  169. gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led");
  170. gpio_direction_output(IGEP0030_GPIO_LED, 0);
  171. break;
  172. default:
  173. /* Should not happen... */
  174. break;
  175. }
  176. }
  177. void set_boardname(void)
  178. {
  179. char rev[5] = { 'F','C','G','E', };
  180. int i = get_board_revision();
  181. rev[i+1] = 0;
  182. env_set("board_rev", rev + i);
  183. env_set("board_name", i < 2 ? "igep0020" : "igep0030");
  184. }
  185. /*
  186. * Routine: misc_init_r
  187. * Description: Configure board specific parts
  188. */
  189. int misc_init_r(void)
  190. {
  191. t2_t *t2_base = (t2_t *)T2_BASE;
  192. u32 pbias_lite;
  193. twl4030_power_init();
  194. /* set VSIM to 1.8V */
  195. twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
  196. TWL4030_PM_RECEIVER_VSIM_VSEL_18,
  197. TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
  198. TWL4030_PM_RECEIVER_DEV_GRP_P1);
  199. /* set up dual-voltage GPIOs to 1.8V */
  200. pbias_lite = readl(&t2_base->pbias_lite);
  201. pbias_lite &= ~PBIASLITEVMODE1;
  202. pbias_lite |= PBIASLITEPWRDNZ1;
  203. writel(pbias_lite, &t2_base->pbias_lite);
  204. if (get_cpu_family() == CPU_OMAP36XX)
  205. writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
  206. OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
  207. OMAP34XX_CTRL_WKUP_CTRL);
  208. setup_net_chip();
  209. omap_die_id_display();
  210. set_led();
  211. set_boardname();
  212. return 0;
  213. }
  214. void board_mtdparts_default(const char **mtdids, const char **mtdparts)
  215. {
  216. struct mtd_info *mtd = get_mtd_device(NULL, 0);
  217. if (mtd) {
  218. static char ids[24];
  219. static char parts[48];
  220. const char *linux_name = "omap2-nand";
  221. if (strncmp(mtd->name, "onenand0", 8) == 0)
  222. linux_name = "omap2-onenand";
  223. snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
  224. snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
  225. linux_name, 4 * mtd->erasesize >> 10);
  226. *mtdids = ids;
  227. *mtdparts = parts;
  228. }
  229. }