poplar.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017 Linaro
  4. * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <asm/cache.h>
  11. #include <asm/io.h>
  12. #include <dm/platform_data/serial_pl01x.h>
  13. #include <asm/arch/hi3798cv200.h>
  14. #include <asm/armv8/mmu.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. static struct mm_region poplar_mem_map[] = {
  19. {
  20. .virt = 0x0UL,
  21. .phys = 0x0UL,
  22. .size = 0x80000000UL,
  23. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  24. PTE_BLOCK_INNER_SHARE
  25. }, {
  26. .virt = 0x80000000UL,
  27. .phys = 0x80000000UL,
  28. .size = 0x80000000UL,
  29. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  30. PTE_BLOCK_NON_SHARE |
  31. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  32. }, {
  33. 0,
  34. }
  35. };
  36. struct mm_region *mem_map = poplar_mem_map;
  37. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  38. static const struct pl01x_serial_plat serial_plat = {
  39. .base = REG_BASE_UART0,
  40. .type = TYPE_PL010,
  41. .clock = 75000000,
  42. };
  43. U_BOOT_DEVICE(poplar_serial) = {
  44. .name = "serial_pl01x",
  45. .plat = &serial_plat,
  46. };
  47. #endif
  48. int checkboard(void)
  49. {
  50. puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
  51. return 0;
  52. }
  53. void reset_cpu(ulong addr)
  54. {
  55. psci_system_reset();
  56. }
  57. int dram_init(void)
  58. {
  59. gd->ram_size = get_ram_size(NULL, 0x80000000);
  60. return 0;
  61. }
  62. /*
  63. * Some linux kernel versions don't use memory before its load address, so to
  64. * be generic we just pretend it isn't there. In previous uboot versions we
  65. * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
  66. * could persist in memory and be left alone by the kernel.
  67. *
  68. * That led to a problem when mapping memory in older kernels. That PSCI code
  69. * now lies in memory below the kernel load offset; it therefore won't be
  70. * touched by the kernel, and by not specially reserving it we avoid the mapping
  71. * problem as well.
  72. *
  73. */
  74. #define KERNEL_TEXT_OFFSET 0x00080000
  75. int dram_init_banksize(void)
  76. {
  77. gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
  78. gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
  79. return 0;
  80. }
  81. static void usb2_phy_config(void)
  82. {
  83. const u32 config[] = {
  84. /* close EOP pre-emphasis. open data pre-emphasis */
  85. 0xa1001c,
  86. /* Rcomp = 150mW, increase DC level */
  87. 0xa00607,
  88. /* keep Rcomp working */
  89. 0xa10700,
  90. /* Icomp = 212mW, increase current drive */
  91. 0xa00aab,
  92. /* EMI fix: rx_active not stay 1 when error packets received */
  93. 0xa11140,
  94. /* Comp mode select */
  95. 0xa11041,
  96. /* adjust eye diagram */
  97. 0xa0098c,
  98. /* adjust eye diagram */
  99. 0xa10a0a,
  100. };
  101. int i;
  102. for (i = 0; i < ARRAY_SIZE(config); i++) {
  103. writel(config[i], PERI_CTRL_USB0);
  104. clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
  105. udelay(20);
  106. }
  107. }
  108. static void usb2_phy_init(void)
  109. {
  110. /* reset usb2 controller bus/utmi/roothub */
  111. setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
  112. USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
  113. udelay(200);
  114. /* reset usb2 phy por/utmi */
  115. setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
  116. udelay(200);
  117. /* open usb2 ref clk */
  118. setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
  119. udelay(300);
  120. /* cancel usb2 power on reset */
  121. clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
  122. udelay(500);
  123. usb2_phy_config();
  124. /* cancel usb2 port reset, wait comp circuit stable */
  125. clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
  126. mdelay(10);
  127. /* open usb2 controller clk */
  128. setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
  129. USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
  130. USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
  131. udelay(200);
  132. /* cancel usb2 control reset */
  133. clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
  134. USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
  135. udelay(200);
  136. }
  137. #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  138. #include <env.h>
  139. #include <usb.h>
  140. #include <usb/dwc2_udc.h>
  141. #include <g_dnl.h>
  142. static struct dwc2_plat_otg_data poplar_otg_data = {
  143. .regs_otg = HIOTG_BASE_ADDR
  144. };
  145. static void set_usb_to_device(void)
  146. {
  147. setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID);
  148. }
  149. int board_usb_init(int index, enum usb_init_type init)
  150. {
  151. set_usb_to_device();
  152. return dwc2_udc_probe(&poplar_otg_data);
  153. }
  154. int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  155. {
  156. if (!env_get("serial#"))
  157. g_dnl_set_serialnumber("0123456789POPLAR");
  158. return 0;
  159. }
  160. #endif
  161. int board_init(void)
  162. {
  163. usb2_phy_init();
  164. return 0;
  165. }