hikey.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Linaro
  4. * Peter Griffin <peter.griffin@linaro.org>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <fdt_support.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <dm/platform_data/serial_pl01x.h>
  13. #include <errno.h>
  14. #include <malloc.h>
  15. #include <netdev.h>
  16. #include <asm/io.h>
  17. #include <usb.h>
  18. #include <linux/delay.h>
  19. #include <power/hi6553_pmic.h>
  20. #include <asm-generic/gpio.h>
  21. #include <asm/arch/dwmmc.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/periph.h>
  24. #include <asm/arch/pinmux.h>
  25. #include <asm/arch/hi6220.h>
  26. #include <asm/armv8/mmu.h>
  27. /*TODO drop this table in favour of device tree */
  28. static const struct hikey_gpio_plat hi6220_gpio[] = {
  29. { 0, HI6220_GPIO_BASE(0)},
  30. { 1, HI6220_GPIO_BASE(1)},
  31. { 2, HI6220_GPIO_BASE(2)},
  32. { 3, HI6220_GPIO_BASE(3)},
  33. { 4, HI6220_GPIO_BASE(4)},
  34. { 5, HI6220_GPIO_BASE(5)},
  35. { 6, HI6220_GPIO_BASE(6)},
  36. { 7, HI6220_GPIO_BASE(7)},
  37. { 8, HI6220_GPIO_BASE(8)},
  38. { 9, HI6220_GPIO_BASE(9)},
  39. { 10, HI6220_GPIO_BASE(10)},
  40. { 11, HI6220_GPIO_BASE(11)},
  41. { 12, HI6220_GPIO_BASE(12)},
  42. { 13, HI6220_GPIO_BASE(13)},
  43. { 14, HI6220_GPIO_BASE(14)},
  44. { 15, HI6220_GPIO_BASE(15)},
  45. { 16, HI6220_GPIO_BASE(16)},
  46. { 17, HI6220_GPIO_BASE(17)},
  47. { 18, HI6220_GPIO_BASE(18)},
  48. { 19, HI6220_GPIO_BASE(19)},
  49. };
  50. U_BOOT_DEVICES(hi6220_gpios) = {
  51. { "gpio_hi6220", &hi6220_gpio[0] },
  52. { "gpio_hi6220", &hi6220_gpio[1] },
  53. { "gpio_hi6220", &hi6220_gpio[2] },
  54. { "gpio_hi6220", &hi6220_gpio[3] },
  55. { "gpio_hi6220", &hi6220_gpio[4] },
  56. { "gpio_hi6220", &hi6220_gpio[5] },
  57. { "gpio_hi6220", &hi6220_gpio[6] },
  58. { "gpio_hi6220", &hi6220_gpio[7] },
  59. { "gpio_hi6220", &hi6220_gpio[8] },
  60. { "gpio_hi6220", &hi6220_gpio[9] },
  61. { "gpio_hi6220", &hi6220_gpio[10] },
  62. { "gpio_hi6220", &hi6220_gpio[11] },
  63. { "gpio_hi6220", &hi6220_gpio[12] },
  64. { "gpio_hi6220", &hi6220_gpio[13] },
  65. { "gpio_hi6220", &hi6220_gpio[14] },
  66. { "gpio_hi6220", &hi6220_gpio[15] },
  67. { "gpio_hi6220", &hi6220_gpio[16] },
  68. { "gpio_hi6220", &hi6220_gpio[17] },
  69. { "gpio_hi6220", &hi6220_gpio[18] },
  70. { "gpio_hi6220", &hi6220_gpio[19] },
  71. };
  72. DECLARE_GLOBAL_DATA_PTR;
  73. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  74. static const struct pl01x_serial_plat serial_plat = {
  75. #if CONFIG_CONS_INDEX == 1
  76. .base = HI6220_UART0_BASE,
  77. #elif CONFIG_CONS_INDEX == 4
  78. .base = HI6220_UART3_BASE,
  79. #else
  80. #error "Unsupported console index value."
  81. #endif
  82. .type = TYPE_PL011,
  83. .clock = 19200000
  84. };
  85. U_BOOT_DEVICE(hikey_seriala) = {
  86. .name = "serial_pl01x",
  87. .plat = &serial_plat,
  88. };
  89. #endif
  90. static struct mm_region hikey_mem_map[] = {
  91. {
  92. .virt = 0x0UL,
  93. .phys = 0x0UL,
  94. .size = 0x80000000UL,
  95. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  96. PTE_BLOCK_INNER_SHARE
  97. }, {
  98. .virt = 0x80000000UL,
  99. .phys = 0x80000000UL,
  100. .size = 0x80000000UL,
  101. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  102. PTE_BLOCK_NON_SHARE |
  103. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  104. }, {
  105. /* List terminator */
  106. 0,
  107. }
  108. };
  109. struct mm_region *mem_map = hikey_mem_map;
  110. #ifdef CONFIG_BOARD_EARLY_INIT_F
  111. int board_uart_init(void)
  112. {
  113. switch (CONFIG_CONS_INDEX) {
  114. case 1:
  115. hi6220_pinmux_config(PERIPH_ID_UART0);
  116. break;
  117. case 4:
  118. hi6220_pinmux_config(PERIPH_ID_UART3);
  119. break;
  120. default:
  121. debug("%s: Unsupported UART selected\n", __func__);
  122. return -1;
  123. }
  124. return 0;
  125. }
  126. int board_early_init_f(void)
  127. {
  128. board_uart_init();
  129. return 0;
  130. }
  131. #endif
  132. struct peri_sc_periph_regs *peri_sc =
  133. (struct peri_sc_periph_regs *)HI6220_PERI_BASE;
  134. struct alwayson_sc_regs *ao_sc =
  135. (struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
  136. /* status offset from enable reg */
  137. #define STAT_EN_OFF 0x2
  138. void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
  139. {
  140. uint32_t data;
  141. data = readl(clk_base);
  142. data |= bitfield;
  143. writel(bitfield, clk_base);
  144. do {
  145. data = readl(clk_base + STAT_EN_OFF);
  146. } while ((data & bitfield) == 0);
  147. }
  148. /* status offset from disable reg */
  149. #define STAT_DIS_OFF 0x1
  150. void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
  151. {
  152. uint32_t data;
  153. data = readl(clk_base);
  154. data |= bitfield;
  155. writel(data, clk_base);
  156. do {
  157. data = readl(clk_base + STAT_DIS_OFF);
  158. } while (data & bitfield);
  159. }
  160. #define EYE_PATTERN 0x70533483
  161. int board_usb_init(int index, enum usb_init_type init)
  162. {
  163. unsigned int data;
  164. /* enable USB clock */
  165. hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
  166. /* take usb IPs out of reset */
  167. writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
  168. PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
  169. &peri_sc->rst0_dis);
  170. do {
  171. data = readl(&peri_sc->rst0_stat);
  172. data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
  173. PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
  174. } while (data);
  175. /*CTRL 5*/
  176. data = readl(&peri_sc->ctrl5);
  177. data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
  178. data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
  179. data |= 0x300;
  180. writel(data, &peri_sc->ctrl5);
  181. /*CTRL 4*/
  182. /* configure USB PHY */
  183. data = readl(&peri_sc->ctrl4);
  184. /* make PHY out of low power mode */
  185. data &= ~PERI_CTRL4_PICO_SIDDQ;
  186. data &= ~PERI_CTRL4_PICO_OGDISABLE;
  187. data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
  188. writel(data, &peri_sc->ctrl4);
  189. writel(EYE_PATTERN, &peri_sc->ctrl8);
  190. mdelay(5);
  191. return 0;
  192. }
  193. static int config_sd_carddetect(void)
  194. {
  195. int ret;
  196. /* configure GPIO8 as nopull */
  197. writel(0, 0xf8001830);
  198. gpio_request(8, "SD CD");
  199. gpio_direction_input(8);
  200. ret = gpio_get_value(8);
  201. if (!ret) {
  202. printf("%s: SD card present\n", __func__);
  203. return 1;
  204. }
  205. printf("%s: SD card not present\n", __func__);
  206. return 0;
  207. }
  208. static void mmc1_init_pll(void)
  209. {
  210. uint32_t data;
  211. /* select SYSPLL as the source of MMC1 */
  212. /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
  213. writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
  214. do {
  215. data = readl(&peri_sc->clk0_sel);
  216. } while (!(data & (1 << 11)));
  217. /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
  218. writel(1 << 30, &peri_sc->clk0_sel);
  219. do {
  220. data = readl(&peri_sc->clk0_sel);
  221. } while (data & (1 << 14));
  222. hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
  223. hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
  224. do {
  225. /* 1.2GHz / 50 = 24MHz */
  226. writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
  227. data = readl(&peri_sc->clkcfg8bit2);
  228. } while ((data & 0x31) != 0x31);
  229. }
  230. static void mmc1_reset_clk(void)
  231. {
  232. unsigned int data;
  233. /* disable mmc1 bus clock */
  234. hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
  235. /* enable mmc1 bus clock */
  236. hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
  237. /* reset mmc1 clock domain */
  238. writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
  239. /* bypass mmc1 clock phase */
  240. data = readl(&peri_sc->ctrl2);
  241. data |= 3 << 2;
  242. writel(data, &peri_sc->ctrl2);
  243. /* disable low power */
  244. data = readl(&peri_sc->ctrl13);
  245. data |= 1 << 4;
  246. writel(data, &peri_sc->ctrl13);
  247. do {
  248. data = readl(&peri_sc->rst0_stat);
  249. } while (!(data & PERI_RST0_MMC1));
  250. /* unreset mmc1 clock domain */
  251. writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
  252. do {
  253. data = readl(&peri_sc->rst0_stat);
  254. } while (data & PERI_RST0_MMC1);
  255. }
  256. static void mmc0_reset_clk(void)
  257. {
  258. unsigned int data;
  259. /* disable mmc0 bus clock */
  260. hi6220_clk_disable(PERI_CLK0_MMC0, &peri_sc->clk0_dis);
  261. /* enable mmc0 bus clock */
  262. hi6220_clk_enable(PERI_CLK0_MMC0, &peri_sc->clk0_en);
  263. /* reset mmc0 clock domain */
  264. writel(PERI_RST0_MMC0, &peri_sc->rst0_en);
  265. /* bypass mmc0 clock phase */
  266. data = readl(&peri_sc->ctrl2);
  267. data |= 3;
  268. writel(data, &peri_sc->ctrl2);
  269. /* disable low power */
  270. data = readl(&peri_sc->ctrl13);
  271. data |= 1 << 3;
  272. writel(data, &peri_sc->ctrl13);
  273. do {
  274. data = readl(&peri_sc->rst0_stat);
  275. } while (!(data & PERI_RST0_MMC0));
  276. /* unreset mmc0 clock domain */
  277. writel(PERI_RST0_MMC0, &peri_sc->rst0_dis);
  278. do {
  279. data = readl(&peri_sc->rst0_stat);
  280. } while (data & PERI_RST0_MMC0);
  281. }
  282. /* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
  283. static void hi6220_pmussi_init(void)
  284. {
  285. uint32_t data;
  286. /* Take PMUSSI out of reset */
  287. writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
  288. &ao_sc->rst4_dis);
  289. do {
  290. data = readl(&ao_sc->rst4_stat);
  291. } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
  292. /* set PMU SSI clock latency for read operation */
  293. data = readl(&ao_sc->mcu_subsys_ctrl3);
  294. data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
  295. data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
  296. writel(data, &ao_sc->mcu_subsys_ctrl3);
  297. /* enable PMUSSI clock */
  298. data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
  299. ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
  300. hi6220_clk_enable(data, &ao_sc->clk5_en);
  301. /* Output high to PMIC on PWR_HOLD_GPIO0_0 */
  302. gpio_request(0, "PWR_HOLD_GPIO0_0");
  303. gpio_direction_output(0, 1);
  304. }
  305. int misc_init_r(void)
  306. {
  307. return 0;
  308. }
  309. int board_init(void)
  310. {
  311. return 0;
  312. }
  313. #ifdef CONFIG_MMC
  314. static int init_dwmmc(void)
  315. {
  316. int ret = 0;
  317. #ifdef CONFIG_MMC_DW
  318. /* mmc0 pll is already configured by ATF */
  319. mmc0_reset_clk();
  320. ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
  321. if (ret)
  322. printf("%s: Error configuring pinmux for eMMC (%d)\n"
  323. , __func__, ret);
  324. ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
  325. if (ret)
  326. printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
  327. /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
  328. mmc1_init_pll();
  329. mmc1_reset_clk();
  330. ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
  331. if (ret)
  332. printf("%s: Error configuring pinmux for eMMC (%d)\n"
  333. , __func__, ret);
  334. config_sd_carddetect();
  335. ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
  336. if (ret)
  337. printf("%s: Error adding SD port (%d)\n", __func__, ret);
  338. #endif
  339. return ret;
  340. }
  341. /* setup board specific PMIC */
  342. int power_init_board(void)
  343. {
  344. /* init the hi6220 pmussi ip */
  345. hi6220_pmussi_init();
  346. power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
  347. return 0;
  348. }
  349. int board_mmc_init(struct bd_info *bis)
  350. {
  351. int ret;
  352. /* add the eMMC and sd ports */
  353. ret = init_dwmmc();
  354. if (ret)
  355. debug("init_dwmmc failed\n");
  356. return ret;
  357. }
  358. #endif
  359. int dram_init(void)
  360. {
  361. gd->ram_size = PHYS_SDRAM_1_SIZE;
  362. return 0;
  363. }
  364. int dram_init_banksize(void)
  365. {
  366. /*
  367. * Reserve regions below from DT memory node (which gets generated
  368. * by U-Boot from the dram banks in arch_fixup_fdt() before booting
  369. * the kernel. This will then match the kernel hikey dts memory node.
  370. *
  371. * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
  372. * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
  373. * 0x06df,f000 - 0x06df,ffff: Mailbox message data
  374. * 0x0740,f000 - 0x0740,ffff: MCU firmware section
  375. * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
  376. * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
  377. */
  378. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  379. gd->bd->bi_dram[0].size = 0x05e00000;
  380. gd->bd->bi_dram[1].start = 0x05f00000;
  381. gd->bd->bi_dram[1].size = 0x00001000;
  382. gd->bd->bi_dram[2].start = 0x05f02000;
  383. gd->bd->bi_dram[2].size = 0x00efd000;
  384. gd->bd->bi_dram[3].start = 0x06e00000;
  385. gd->bd->bi_dram[3].size = 0x0060f000;
  386. gd->bd->bi_dram[4].start = 0x07410000;
  387. gd->bd->bi_dram[4].size = 0x1aaf0000;
  388. gd->bd->bi_dram[5].start = 0x22000000;
  389. gd->bd->bi_dram[5].size = 0x1c000000;
  390. return 0;
  391. }
  392. void reset_cpu(ulong addr)
  393. {
  394. writel(0x48698284, &ao_sc->stat0);
  395. wfi();
  396. }