gw_ventana.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Gateworks Corporation
  4. *
  5. * Author: Tim Harvey <tharvey@gateworks.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <net.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/iomux.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <asm/arch/mxc_hdmi.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/gpio.h>
  18. #include <asm/mach-imx/boot_mode.h>
  19. #include <asm/mach-imx/sata.h>
  20. #include <asm/mach-imx/spi.h>
  21. #include <asm/mach-imx/video.h>
  22. #include <asm/io.h>
  23. #include <asm/setup.h>
  24. #include <dm.h>
  25. #include <dm/platform_data/serial_mxc.h>
  26. #include <env.h>
  27. #include <hwconfig.h>
  28. #include <i2c.h>
  29. #include <fdt_support.h>
  30. #include <fsl_esdhc_imx.h>
  31. #include <jffs2/load_kernel.h>
  32. #include <linux/ctype.h>
  33. #include <miiphy.h>
  34. #include <mtd_node.h>
  35. #include <netdev.h>
  36. #include <pci.h>
  37. #include <linux/delay.h>
  38. #include <linux/libfdt.h>
  39. #include <power/pmic.h>
  40. #include <power/ltc3676_pmic.h>
  41. #include <power/pfuze100_pmic.h>
  42. #include <fdt_support.h>
  43. #include <jffs2/load_kernel.h>
  44. #include <spi_flash.h>
  45. #include "gsc.h"
  46. #include "common.h"
  47. DECLARE_GLOBAL_DATA_PTR;
  48. /*
  49. * EEPROM board info struct populated by read_eeprom so that we only have to
  50. * read it once.
  51. */
  52. struct ventana_board_info ventana_info;
  53. static int board_type;
  54. /* ENET */
  55. static iomux_v3_cfg_t const enet_pads[] = {
  56. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  57. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  58. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  59. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  64. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  66. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  73. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74. /* PHY nRST */
  75. IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  76. };
  77. #ifdef CONFIG_CMD_NAND
  78. static iomux_v3_cfg_t const nfc_pads[] = {
  79. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  80. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  81. IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  82. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  83. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94. };
  95. static void setup_gpmi_nand(void)
  96. {
  97. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  98. /* config gpmi nand iomux */
  99. SETUP_IOMUX_PADS(nfc_pads);
  100. /* config gpmi and bch clock to 100 MHz */
  101. clrsetbits_le32(&mxc_ccm->cs2cdr,
  102. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  103. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  104. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  105. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  106. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  107. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  108. /* enable gpmi and bch clock gating */
  109. setbits_le32(&mxc_ccm->CCGR4,
  110. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  111. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  112. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  113. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  114. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  115. /* enable apbh clock gating */
  116. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  117. }
  118. #endif
  119. static void setup_iomux_enet(int gpio)
  120. {
  121. SETUP_IOMUX_PADS(enet_pads);
  122. /* toggle PHY_RST# */
  123. gpio_request(gpio, "phy_rst#");
  124. gpio_direction_output(gpio, 0);
  125. mdelay(10);
  126. gpio_set_value(gpio, 1);
  127. mdelay(100);
  128. }
  129. #ifdef CONFIG_USB_EHCI_MX6
  130. static iomux_v3_cfg_t const usb_pads[] = {
  131. IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
  132. IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
  133. /* OTG PWR */
  134. IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
  135. };
  136. int board_ehci_hcd_init(int port)
  137. {
  138. int gpio;
  139. SETUP_IOMUX_PADS(usb_pads);
  140. /* Reset USB HUB */
  141. switch (board_type) {
  142. case GW53xx:
  143. case GW552x:
  144. case GW5906:
  145. gpio = (IMX_GPIO_NR(1, 9));
  146. break;
  147. case GW54proto:
  148. case GW54xx:
  149. gpio = (IMX_GPIO_NR(1, 16));
  150. break;
  151. default:
  152. return 0;
  153. }
  154. /* request and toggle hub rst */
  155. gpio_request(gpio, "usb_hub_rst#");
  156. gpio_direction_output(gpio, 0);
  157. mdelay(2);
  158. gpio_set_value(gpio, 1);
  159. return 0;
  160. }
  161. int board_ehci_power(int port, int on)
  162. {
  163. /* enable OTG VBUS */
  164. if (!port && board_type < GW_UNKNOWN) {
  165. if (gpio_cfg[board_type].otgpwr_en)
  166. gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
  167. }
  168. return 0;
  169. }
  170. #endif /* CONFIG_USB_EHCI_MX6 */
  171. #ifdef CONFIG_MXC_SPI
  172. iomux_v3_cfg_t const ecspi1_pads[] = {
  173. /* SS1 */
  174. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  175. IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  176. IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  177. IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  178. };
  179. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  180. {
  181. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
  182. }
  183. static void setup_spi(void)
  184. {
  185. gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
  186. gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
  187. SETUP_IOMUX_PADS(ecspi1_pads);
  188. }
  189. #endif
  190. /* configure eth0 PHY board-specific LED behavior */
  191. int board_phy_config(struct phy_device *phydev)
  192. {
  193. unsigned short val;
  194. /* Marvel 88E1510 */
  195. if (phydev->phy_id == 0x1410dd1) {
  196. /*
  197. * Page 3, Register 16: LED[2:0] Function Control Register
  198. * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
  199. * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
  200. */
  201. phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
  202. val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
  203. val &= 0xff00;
  204. val |= 0x0017;
  205. phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
  206. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
  207. }
  208. /* TI DP83867 */
  209. else if (phydev->phy_id == 0x2000a231) {
  210. /* configure register 0x170 for ref CLKOUT */
  211. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
  212. phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
  213. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
  214. val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
  215. val &= ~0x1f00;
  216. val |= 0x0b00; /* chD tx clock*/
  217. phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
  218. }
  219. if (phydev->drv->config)
  220. phydev->drv->config(phydev);
  221. return 0;
  222. }
  223. #ifdef CONFIG_MV88E61XX_SWITCH
  224. int mv88e61xx_hw_reset(struct phy_device *phydev)
  225. {
  226. struct mii_dev *bus = phydev->bus;
  227. /* GPIO[0] output, CLK125 */
  228. debug("enabling RGMII_REFCLK\n");
  229. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  230. 0x1a /*MV_SCRATCH_MISC*/,
  231. (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
  232. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  233. 0x1a /*MV_SCRATCH_MISC*/,
  234. (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
  235. /* RGMII delay - Physical Control register bit[15:14] */
  236. debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
  237. /* forced 1000mbps full-duplex link */
  238. bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
  239. phydev->autoneg = AUTONEG_DISABLE;
  240. phydev->speed = SPEED_1000;
  241. phydev->duplex = DUPLEX_FULL;
  242. /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
  243. bus->write(bus, 0x10, 0, 0x16, 0x8088);
  244. bus->write(bus, 0x11, 0, 0x16, 0x8088);
  245. bus->write(bus, 0x12, 0, 0x16, 0x8088);
  246. bus->write(bus, 0x13, 0, 0x16, 0x8088);
  247. return 0;
  248. }
  249. #endif // CONFIG_MV88E61XX_SWITCH
  250. int board_eth_init(struct bd_info *bis)
  251. {
  252. #ifdef CONFIG_FEC_MXC
  253. struct ventana_board_info *info = &ventana_info;
  254. if (test_bit(EECONFIG_ETH0, info->config)) {
  255. setup_iomux_enet(GP_PHY_RST);
  256. cpu_eth_init(bis);
  257. }
  258. #endif
  259. #ifdef CONFIG_E1000
  260. e1000_initialize(bis);
  261. #endif
  262. #ifdef CONFIG_CI_UDC
  263. /* For otg ethernet*/
  264. usb_eth_initialize(bis);
  265. #endif
  266. /* default to the first detected enet dev */
  267. if (!env_get("ethprime")) {
  268. struct eth_device *dev = eth_get_dev_by_index(0);
  269. if (dev) {
  270. env_set("ethprime", dev->name);
  271. printf("set ethprime to %s\n", env_get("ethprime"));
  272. }
  273. }
  274. return 0;
  275. }
  276. #if defined(CONFIG_VIDEO_IPUV3)
  277. static void enable_hdmi(struct display_info_t const *dev)
  278. {
  279. imx_enable_hdmi_phy();
  280. }
  281. static int detect_i2c(struct display_info_t const *dev)
  282. {
  283. return i2c_set_bus_num(dev->bus) == 0 &&
  284. i2c_probe(dev->addr) == 0;
  285. }
  286. static void enable_lvds(struct display_info_t const *dev)
  287. {
  288. struct iomuxc *iomux = (struct iomuxc *)
  289. IOMUXC_BASE_ADDR;
  290. /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
  291. u32 reg = readl(&iomux->gpr[2]);
  292. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  293. writel(reg, &iomux->gpr[2]);
  294. /* Enable Backlight */
  295. gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
  296. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  297. gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
  298. SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
  299. gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
  300. }
  301. struct display_info_t const displays[] = {{
  302. /* HDMI Output */
  303. .bus = -1,
  304. .addr = 0,
  305. .pixfmt = IPU_PIX_FMT_RGB24,
  306. .detect = detect_hdmi,
  307. .enable = enable_hdmi,
  308. .mode = {
  309. .name = "HDMI",
  310. .refresh = 60,
  311. .xres = 1024,
  312. .yres = 768,
  313. .pixclock = 15385,
  314. .left_margin = 220,
  315. .right_margin = 40,
  316. .upper_margin = 21,
  317. .lower_margin = 7,
  318. .hsync_len = 60,
  319. .vsync_len = 10,
  320. .sync = FB_SYNC_EXT,
  321. .vmode = FB_VMODE_NONINTERLACED
  322. } }, {
  323. /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
  324. .bus = 2,
  325. .addr = 0x4,
  326. .pixfmt = IPU_PIX_FMT_LVDS666,
  327. .detect = detect_i2c,
  328. .enable = enable_lvds,
  329. .mode = {
  330. .name = "Hannstar-XGA",
  331. .refresh = 60,
  332. .xres = 1024,
  333. .yres = 768,
  334. .pixclock = 15385,
  335. .left_margin = 220,
  336. .right_margin = 40,
  337. .upper_margin = 21,
  338. .lower_margin = 7,
  339. .hsync_len = 60,
  340. .vsync_len = 10,
  341. .sync = FB_SYNC_EXT,
  342. .vmode = FB_VMODE_NONINTERLACED
  343. } }, {
  344. /* DLC700JMG-T-4 */
  345. .bus = 2,
  346. .addr = 0x38,
  347. .detect = NULL,
  348. .enable = enable_lvds,
  349. .pixfmt = IPU_PIX_FMT_LVDS666,
  350. .mode = {
  351. .name = "DLC700JMGT4",
  352. .refresh = 60,
  353. .xres = 1024, /* 1024x600active pixels */
  354. .yres = 600,
  355. .pixclock = 15385, /* 64MHz */
  356. .left_margin = 220,
  357. .right_margin = 40,
  358. .upper_margin = 21,
  359. .lower_margin = 7,
  360. .hsync_len = 60,
  361. .vsync_len = 10,
  362. .sync = FB_SYNC_EXT,
  363. .vmode = FB_VMODE_NONINTERLACED
  364. } }, {
  365. /* DLC800FIG-T-3 */
  366. .bus = 2,
  367. .addr = 0x14,
  368. .detect = NULL,
  369. .enable = enable_lvds,
  370. .pixfmt = IPU_PIX_FMT_LVDS666,
  371. .mode = {
  372. .name = "DLC800FIGT3",
  373. .refresh = 60,
  374. .xres = 1024, /* 1024x768 active pixels */
  375. .yres = 768,
  376. .pixclock = 15385, /* 64MHz */
  377. .left_margin = 220,
  378. .right_margin = 40,
  379. .upper_margin = 21,
  380. .lower_margin = 7,
  381. .hsync_len = 60,
  382. .vsync_len = 10,
  383. .sync = FB_SYNC_EXT,
  384. .vmode = FB_VMODE_NONINTERLACED
  385. } }, {
  386. .bus = 2,
  387. .addr = 0x5d,
  388. .detect = detect_i2c,
  389. .enable = enable_lvds,
  390. .pixfmt = IPU_PIX_FMT_LVDS666,
  391. .mode = {
  392. .name = "Z101WX01",
  393. .refresh = 60,
  394. .xres = 1280,
  395. .yres = 800,
  396. .pixclock = 15385, /* 64MHz */
  397. .left_margin = 220,
  398. .right_margin = 40,
  399. .upper_margin = 21,
  400. .lower_margin = 7,
  401. .hsync_len = 60,
  402. .vsync_len = 10,
  403. .sync = FB_SYNC_EXT,
  404. .vmode = FB_VMODE_NONINTERLACED
  405. }
  406. },
  407. };
  408. size_t display_count = ARRAY_SIZE(displays);
  409. static void setup_display(void)
  410. {
  411. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  412. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  413. int reg;
  414. enable_ipu_clock();
  415. imx_setup_hdmi();
  416. /* Turn on LDB0,IPU,IPU DI0 clocks */
  417. reg = __raw_readl(&mxc_ccm->CCGR3);
  418. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  419. writel(reg, &mxc_ccm->CCGR3);
  420. /* set LDB0, LDB1 clk select to 011/011 */
  421. reg = readl(&mxc_ccm->cs2cdr);
  422. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  423. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  424. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  425. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  426. writel(reg, &mxc_ccm->cs2cdr);
  427. reg = readl(&mxc_ccm->cscmr2);
  428. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  429. writel(reg, &mxc_ccm->cscmr2);
  430. reg = readl(&mxc_ccm->chsccdr);
  431. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  432. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  433. writel(reg, &mxc_ccm->chsccdr);
  434. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  435. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  436. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  437. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  438. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  439. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  440. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  441. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  442. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  443. writel(reg, &iomux->gpr[2]);
  444. reg = readl(&iomux->gpr[3]);
  445. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
  446. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  447. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  448. writel(reg, &iomux->gpr[3]);
  449. /* LVDS Backlight GPIO on LVDS connector - output low */
  450. SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
  451. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  452. }
  453. #endif /* CONFIG_VIDEO_IPUV3 */
  454. /* setup board specific PMIC */
  455. int power_init_board(void)
  456. {
  457. setup_pmic();
  458. return 0;
  459. }
  460. #if defined(CONFIG_CMD_PCI)
  461. int imx6_pcie_toggle_reset(void)
  462. {
  463. if (board_type < GW_UNKNOWN) {
  464. uint pin = gpio_cfg[board_type].pcie_rst;
  465. gpio_request(pin, "pci_rst#");
  466. gpio_direction_output(pin, 0);
  467. mdelay(50);
  468. gpio_direction_output(pin, 1);
  469. }
  470. return 0;
  471. }
  472. /*
  473. * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
  474. * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
  475. * properly and assert reset for 100ms.
  476. */
  477. #define MAX_PCI_DEVS 32
  478. struct pci_dev {
  479. pci_dev_t devfn;
  480. unsigned short vendor;
  481. unsigned short device;
  482. unsigned short class;
  483. unsigned short busno; /* subbordinate busno */
  484. struct pci_dev *ppar;
  485. };
  486. struct pci_dev pci_devs[MAX_PCI_DEVS];
  487. int pci_devno;
  488. int pci_bridgeno;
  489. void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
  490. unsigned short vendor, unsigned short device,
  491. unsigned short class)
  492. {
  493. int i;
  494. u32 dw;
  495. struct pci_dev *pdev = &pci_devs[pci_devno++];
  496. debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
  497. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
  498. /* store array of devs for later use in device-tree fixup */
  499. pdev->devfn = dev;
  500. pdev->vendor = vendor;
  501. pdev->device = device;
  502. pdev->class = class;
  503. pdev->ppar = NULL;
  504. if (class == PCI_CLASS_BRIDGE_PCI)
  505. pdev->busno = ++pci_bridgeno;
  506. else
  507. pdev->busno = 0;
  508. /* fixup RC - it should be 00:00.0 not 00:01.0 */
  509. if (PCI_BUS(dev) == 0)
  510. pdev->devfn = 0;
  511. /* find dev's parent */
  512. for (i = 0; i < pci_devno; i++) {
  513. if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
  514. pdev->ppar = &pci_devs[i];
  515. break;
  516. }
  517. }
  518. /* assert downstream PERST# */
  519. if (vendor == PCI_VENDOR_ID_PLX &&
  520. (device & 0xfff0) == 0x8600 &&
  521. PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
  522. debug("configuring PLX 860X downstream PERST#\n");
  523. pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
  524. dw |= 0xaaa8; /* GPIO1-7 outputs */
  525. pci_hose_write_config_dword(hose, dev, 0x62c, dw);
  526. pci_hose_read_config_dword(hose, dev, 0x644, &dw);
  527. dw |= 0xfe; /* GPIO1-7 output high */
  528. pci_hose_write_config_dword(hose, dev, 0x644, dw);
  529. mdelay(100);
  530. }
  531. }
  532. #endif /* CONFIG_CMD_PCI */
  533. #ifdef CONFIG_SERIAL_TAG
  534. /*
  535. * called when setting up ATAGS before booting kernel
  536. * populate serialnum from the following (in order of priority):
  537. * serial# env var
  538. * eeprom
  539. */
  540. void get_board_serial(struct tag_serialnr *serialnr)
  541. {
  542. char *serial = env_get("serial#");
  543. if (serial) {
  544. serialnr->high = 0;
  545. serialnr->low = simple_strtoul(serial, NULL, 10);
  546. } else if (ventana_info.model[0]) {
  547. serialnr->high = 0;
  548. serialnr->low = ventana_info.serial;
  549. } else {
  550. serialnr->high = 0;
  551. serialnr->low = 0;
  552. }
  553. }
  554. #endif
  555. /*
  556. * Board Support
  557. */
  558. int board_early_init_f(void)
  559. {
  560. setup_iomux_uart();
  561. #if defined(CONFIG_VIDEO_IPUV3)
  562. setup_display();
  563. #endif
  564. return 0;
  565. }
  566. int dram_init(void)
  567. {
  568. gd->ram_size = imx_ddr_size();
  569. return 0;
  570. }
  571. int board_init(void)
  572. {
  573. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  574. clrsetbits_le32(&iomuxc_regs->gpr[1],
  575. IOMUXC_GPR1_OTG_ID_MASK,
  576. IOMUXC_GPR1_OTG_ID_GPIO1);
  577. /* address of linux boot parameters */
  578. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  579. /* read Gateworks EEPROM into global struct (used later) */
  580. setup_ventana_i2c(0);
  581. board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  582. #ifdef CONFIG_CMD_NAND
  583. if (gpio_cfg[board_type].nand)
  584. setup_gpmi_nand();
  585. #endif
  586. #ifdef CONFIG_MXC_SPI
  587. setup_spi();
  588. #endif
  589. setup_ventana_i2c(1);
  590. setup_ventana_i2c(2);
  591. #ifdef CONFIG_SATA
  592. setup_sata();
  593. #endif
  594. setup_iomux_gpio(board_type, &ventana_info);
  595. return 0;
  596. }
  597. #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
  598. /*
  599. * called during late init (after relocation and after board_init())
  600. * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
  601. * EEPROM read.
  602. */
  603. int checkboard(void)
  604. {
  605. struct ventana_board_info *info = &ventana_info;
  606. unsigned char buf[4];
  607. const char *p;
  608. int quiet; /* Quiet or minimal output mode */
  609. quiet = 0;
  610. p = env_get("quiet");
  611. if (p)
  612. quiet = simple_strtol(p, NULL, 10);
  613. else
  614. env_set("quiet", "0");
  615. puts("\nGateworks Corporation Copyright 2014\n");
  616. if (info->model[0]) {
  617. printf("Model: %s\n", info->model);
  618. printf("MFGDate: %02x-%02x-%02x%02x\n",
  619. info->mfgdate[0], info->mfgdate[1],
  620. info->mfgdate[2], info->mfgdate[3]);
  621. printf("Serial:%d\n", info->serial);
  622. } else {
  623. puts("Invalid EEPROM - board will not function fully\n");
  624. }
  625. if (quiet)
  626. return 0;
  627. /* Display GSC firmware revision/CRC/status */
  628. gsc_info(0);
  629. /* Display RTC */
  630. if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
  631. printf("RTC: %d\n",
  632. buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
  633. }
  634. return 0;
  635. }
  636. #endif
  637. #ifdef CONFIG_CMD_BMODE
  638. /*
  639. * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
  640. * see Table 8-11 and Table 5-9
  641. * BOOT_CFG1[7] = 1 (boot from NAND)
  642. * BOOT_CFG1[5] = 0 - raw NAND
  643. * BOOT_CFG1[4] = 0 - default pad settings
  644. * BOOT_CFG1[3:2] = 00 - devices = 1
  645. * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
  646. * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
  647. * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
  648. * BOOT_CFG2[0] = 0 - Reset time 12ms
  649. */
  650. static const struct boot_mode board_boot_modes[] = {
  651. /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
  652. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  653. { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
  654. { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
  655. { NULL, 0 },
  656. };
  657. #endif
  658. /* late init */
  659. int misc_init_r(void)
  660. {
  661. struct ventana_board_info *info = &ventana_info;
  662. char buf[256];
  663. int i;
  664. /* set env vars based on EEPROM data */
  665. if (ventana_info.model[0]) {
  666. char str[16], fdt[36];
  667. char *p;
  668. const char *cputype = "";
  669. /*
  670. * FDT name will be prefixed with CPU type. Three versions
  671. * will be created each increasingly generic and bootloader
  672. * env scripts will try loading each from most specific to
  673. * least.
  674. */
  675. if (is_cpu_type(MXC_CPU_MX6Q) ||
  676. is_cpu_type(MXC_CPU_MX6D))
  677. cputype = "imx6q";
  678. else if (is_cpu_type(MXC_CPU_MX6DL) ||
  679. is_cpu_type(MXC_CPU_MX6SOLO))
  680. cputype = "imx6dl";
  681. env_set("soctype", cputype);
  682. if (8 << (ventana_info.nand_flash_size-1) >= 2048)
  683. env_set("flash_layout", "large");
  684. else
  685. env_set("flash_layout", "normal");
  686. memset(str, 0, sizeof(str));
  687. for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
  688. str[i] = tolower(info->model[i]);
  689. env_set("model", str);
  690. if (!env_get("fdt_file")) {
  691. sprintf(fdt, "%s-%s.dtb", cputype, str);
  692. env_set("fdt_file", fdt);
  693. }
  694. p = strchr(str, '-');
  695. if (p) {
  696. *p++ = 0;
  697. env_set("model_base", str);
  698. sprintf(fdt, "%s-%s.dtb", cputype, str);
  699. env_set("fdt_file1", fdt);
  700. if (board_type != GW551x &&
  701. board_type != GW552x &&
  702. board_type != GW553x &&
  703. board_type != GW560x)
  704. str[4] = 'x';
  705. str[5] = 'x';
  706. str[6] = 0;
  707. sprintf(fdt, "%s-%s.dtb", cputype, str);
  708. env_set("fdt_file2", fdt);
  709. }
  710. /* initialize env from EEPROM */
  711. if (test_bit(EECONFIG_ETH0, info->config) &&
  712. !env_get("ethaddr")) {
  713. eth_env_set_enetaddr("ethaddr", info->mac0);
  714. }
  715. if (test_bit(EECONFIG_ETH1, info->config) &&
  716. !env_get("eth1addr")) {
  717. eth_env_set_enetaddr("eth1addr", info->mac1);
  718. }
  719. /* board serial-number */
  720. sprintf(str, "%6d", info->serial);
  721. env_set("serial#", str);
  722. /* memory MB */
  723. sprintf(str, "%d", (int) (gd->ram_size >> 20));
  724. env_set("mem_mb", str);
  725. }
  726. /* Set a non-initialized hwconfig based on board configuration */
  727. if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
  728. buf[0] = 0;
  729. if (gpio_cfg[board_type].rs232_en)
  730. strcat(buf, "rs232;");
  731. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  732. char buf1[32];
  733. sprintf(buf1, "dio%d:mode=gpio;", i);
  734. if (strlen(buf) + strlen(buf1) < sizeof(buf))
  735. strcat(buf, buf1);
  736. }
  737. env_set("hwconfig", buf);
  738. }
  739. /* setup baseboard specific GPIO based on board and env */
  740. setup_board_gpio(board_type, info);
  741. #ifdef CONFIG_CMD_BMODE
  742. add_board_boot_modes(board_boot_modes);
  743. #endif
  744. /* disable boot watchdog */
  745. gsc_boot_wd_disable();
  746. return 0;
  747. }
  748. #ifdef CONFIG_OF_BOARD_SETUP
  749. static int ft_sethdmiinfmt(void *blob, char *mode)
  750. {
  751. int off;
  752. if (!mode)
  753. return -EINVAL;
  754. off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
  755. if (off < 0)
  756. return off;
  757. if (0 == strcasecmp(mode, "yuv422bt656")) {
  758. u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
  759. 0x00, 0x00, 0x00 };
  760. mode = "422_ccir";
  761. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  762. fdt_setprop_u32(blob, off, "vidout_trc", 1);
  763. fdt_setprop_u32(blob, off, "vidout_blc", 1);
  764. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  765. printf(" set HDMI input mode to %s\n", mode);
  766. } else if (0 == strcasecmp(mode, "yuv422smp")) {
  767. u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
  768. 0x82, 0x81, 0x00 };
  769. mode = "422_smp";
  770. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  771. fdt_setprop_u32(blob, off, "vidout_trc", 0);
  772. fdt_setprop_u32(blob, off, "vidout_blc", 0);
  773. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  774. printf(" set HDMI input mode to %s\n", mode);
  775. } else {
  776. return -EINVAL;
  777. }
  778. return 0;
  779. }
  780. #if defined(CONFIG_CMD_PCI)
  781. #define PCI_ID(x) ( \
  782. (PCI_BUS(x->devfn)<<16)| \
  783. (PCI_DEV(x->devfn)<<11)| \
  784. (PCI_FUNC(x->devfn)<<8) \
  785. )
  786. int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
  787. {
  788. uint32_t reg[5];
  789. char node[32];
  790. int np;
  791. sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
  792. PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
  793. np = fdt_subnode_offset(blob, par, node);
  794. if (np >= 0)
  795. return np;
  796. np = fdt_add_subnode(blob, par, node);
  797. if (np < 0) {
  798. printf(" %s failed: no space\n", __func__);
  799. return np;
  800. }
  801. memset(reg, 0, sizeof(reg));
  802. reg[0] = cpu_to_fdt32(PCI_ID(dev));
  803. fdt_setprop(blob, np, "reg", reg, sizeof(reg));
  804. return np;
  805. }
  806. /* build a path of nested PCI devs for all bridges passed through */
  807. int fdt_add_pci_path(void *blob, struct pci_dev *dev)
  808. {
  809. struct pci_dev *bridges[MAX_PCI_DEVS];
  810. int k, np;
  811. /* build list of parents */
  812. np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  813. if (np < 0)
  814. return np;
  815. k = 0;
  816. while (dev) {
  817. bridges[k++] = dev;
  818. dev = dev->ppar;
  819. };
  820. /* now add them the to DT in reverse order */
  821. while (k--) {
  822. np = fdt_add_pci_node(blob, np, bridges[k]);
  823. if (np < 0)
  824. break;
  825. }
  826. return np;
  827. }
  828. /*
  829. * The GW16082 has a hardware errata errata such that it's
  830. * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
  831. * of this normal PCI interrupt swizzling will not work so we will
  832. * provide an irq-map via device-tree.
  833. */
  834. int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
  835. {
  836. int len;
  837. int host;
  838. uint32_t imap_new[8*4*4];
  839. const uint32_t *imap;
  840. uint32_t irq[4];
  841. uint32_t reg[4];
  842. int i;
  843. /* build irq-map based on host controllers map */
  844. host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  845. if (host < 0) {
  846. printf(" %s failed: missing host\n", __func__);
  847. return host;
  848. }
  849. /* use interrupt data from root complex's node */
  850. imap = fdt_getprop(blob, host, "interrupt-map", &len);
  851. if (!imap || len != 128) {
  852. printf(" %s failed: invalid interrupt-map\n",
  853. __func__);
  854. return -FDT_ERR_NOTFOUND;
  855. }
  856. /* obtain irq's of host controller in pin order */
  857. for (i = 0; i < 4; i++)
  858. irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
  859. /*
  860. * determine number of swizzles necessary:
  861. * For each bridge we pass through we need to swizzle
  862. * the number of the slot we are on.
  863. */
  864. struct pci_dev *d;
  865. int b;
  866. b = 0;
  867. d = dev->ppar;
  868. while(d && d->ppar) {
  869. b += PCI_DEV(d->devfn);
  870. d = d->ppar;
  871. }
  872. /* create new irq mappings for slots12-15
  873. * <skt> <idsel> <slot> <skt-inta> <skt-intb>
  874. * J3 AD28 12 INTD INTA
  875. * J4 AD29 13 INTC INTD
  876. * J5 AD30 14 INTB INTC
  877. * J2 AD31 15 INTA INTB
  878. */
  879. for (i = 0; i < 4; i++) {
  880. /* addr matches bus:dev:func */
  881. u32 addr = dev->busno << 16 | (12+i) << 11;
  882. /* default cells from root complex */
  883. memcpy(&imap_new[i*32], imap, 128);
  884. /* first cell is PCI device address (BDF) */
  885. imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
  886. imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
  887. imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
  888. imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
  889. /* third cell is pin */
  890. imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
  891. imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
  892. imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
  893. imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
  894. /* sixth cell is relative interrupt */
  895. imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
  896. imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
  897. imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
  898. imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
  899. }
  900. fdt_setprop(blob, np, "interrupt-map", imap_new,
  901. sizeof(imap_new));
  902. reg[0] = cpu_to_fdt32(0xfff00);
  903. reg[1] = 0;
  904. reg[2] = 0;
  905. reg[3] = cpu_to_fdt32(0x7);
  906. fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
  907. fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
  908. fdt_setprop_string(blob, np, "device_type", "pci");
  909. fdt_setprop_cell(blob, np, "#address-cells", 3);
  910. fdt_setprop_cell(blob, np, "#size-cells", 2);
  911. printf(" Added custom interrupt-map for GW16082\n");
  912. return 0;
  913. }
  914. /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
  915. int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
  916. {
  917. char *tmp, *end;
  918. char mac[16];
  919. unsigned char mac_addr[6];
  920. int j;
  921. sprintf(mac, "eth1addr");
  922. tmp = env_get(mac);
  923. if (tmp) {
  924. for (j = 0; j < 6; j++) {
  925. mac_addr[j] = tmp ?
  926. simple_strtoul(tmp, &end,16) : 0;
  927. if (tmp)
  928. tmp = (*end) ? end+1 : end;
  929. }
  930. fdt_setprop(blob, np, "local-mac-address", mac_addr,
  931. sizeof(mac_addr));
  932. printf(" Added mac addr for eth1\n");
  933. return 0;
  934. }
  935. return -1;
  936. }
  937. /*
  938. * PCI DT nodes must be nested therefore if we need to apply a DT fixup
  939. * we will walk the PCI bus and add bridge nodes up to the device receiving
  940. * the fixup.
  941. */
  942. void ft_board_pci_fixup(void *blob, struct bd_info *bd)
  943. {
  944. int i, np;
  945. struct pci_dev *dev;
  946. for (i = 0; i < pci_devno; i++) {
  947. dev = &pci_devs[i];
  948. /*
  949. * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
  950. * an EEPROM at i2c1-0x50.
  951. */
  952. if ((dev->vendor == PCI_VENDOR_ID_TI) &&
  953. (dev->device == 0x8240) &&
  954. (i2c_set_bus_num(1) == 0) &&
  955. (i2c_probe(0x50) == 0))
  956. {
  957. np = fdt_add_pci_path(blob, dev);
  958. if (np > 0)
  959. fdt_fixup_gw16082(blob, np, dev);
  960. }
  961. /* ethernet1 mac address */
  962. else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
  963. (dev->device == 0x4380))
  964. {
  965. np = fdt_add_pci_path(blob, dev);
  966. if (np > 0)
  967. fdt_fixup_sky2(blob, np, dev);
  968. }
  969. }
  970. }
  971. #endif /* if defined(CONFIG_CMD_PCI) */
  972. void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
  973. {
  974. int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
  975. if (off) {
  976. fdt_delprop(blob, off, "ext-reset-output");
  977. fdt_delprop(blob, off, "fsl,ext-reset-output");
  978. }
  979. }
  980. /*
  981. * called prior to booting kernel or by 'fdt boardsetup' command
  982. *
  983. * unless 'fdt_noauto' env var is set we will update the following in the DTB:
  984. * - mtd partitions based on mtdparts/mtdids env
  985. * - system-serial (board serial num from EEPROM)
  986. * - board (full model from EEPROM)
  987. * - peripherals removed from DTB if not loaded on board (per EEPROM config)
  988. */
  989. #define WDOG1_ADDR 0x20bc000
  990. #define WDOG2_ADDR 0x20c0000
  991. #define GPIO3_ADDR 0x20a4000
  992. #define USDHC3_ADDR 0x2198000
  993. #define PWM0_ADDR 0x2080000
  994. int ft_board_setup(void *blob, struct bd_info *bd)
  995. {
  996. struct ventana_board_info *info = &ventana_info;
  997. struct ventana_eeprom_config *cfg;
  998. static const struct node_info nodes[] = {
  999. { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
  1000. { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
  1001. };
  1002. const char *model = env_get("model");
  1003. const char *display = env_get("display");
  1004. int i;
  1005. char rev = 0;
  1006. /* determine board revision */
  1007. for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
  1008. if (ventana_info.model[i] >= 'A') {
  1009. rev = ventana_info.model[i];
  1010. break;
  1011. }
  1012. }
  1013. if (env_get("fdt_noauto")) {
  1014. puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
  1015. return 0;
  1016. }
  1017. if (test_bit(EECONFIG_NAND, info->config)) {
  1018. /* Update partition nodes using info from mtdparts env var */
  1019. puts(" Updating MTD partitions...\n");
  1020. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  1021. }
  1022. /* Update display timings from display env var */
  1023. if (display) {
  1024. if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
  1025. display) >= 0)
  1026. printf(" Set display timings for %s...\n", display);
  1027. }
  1028. printf(" Adjusting FDT per EEPROM for %s...\n", model);
  1029. /* board serial number */
  1030. fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
  1031. strlen(env_get("serial#")) + 1);
  1032. /* board (model contains model from device-tree) */
  1033. fdt_setprop(blob, 0, "board", info->model,
  1034. strlen((const char *)info->model) + 1);
  1035. /* set desired digital video capture format */
  1036. ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
  1037. /*
  1038. * Board model specific fixups
  1039. */
  1040. switch (board_type) {
  1041. case GW51xx:
  1042. /*
  1043. * disable wdog node for GW51xx-A/B to work around
  1044. * errata causing wdog timer to be unreliable.
  1045. */
  1046. if (rev >= 'A' && rev < 'C') {
  1047. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
  1048. WDOG1_ADDR);
  1049. if (i)
  1050. fdt_status_disabled(blob, i);
  1051. }
  1052. /* GW51xx-E adds WDOG1_B external reset */
  1053. if (rev < 'E')
  1054. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1055. break;
  1056. case GW52xx:
  1057. /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
  1058. if (info->model[4] == '2') {
  1059. u32 handle = 0;
  1060. u32 *range = NULL;
  1061. i = fdt_node_offset_by_compatible(blob, -1,
  1062. "fsl,imx6q-pcie");
  1063. if (i)
  1064. range = (u32 *)fdt_getprop(blob, i,
  1065. "reset-gpio", NULL);
  1066. if (range) {
  1067. i = fdt_node_offset_by_compat_reg(blob,
  1068. "fsl,imx6q-gpio", GPIO3_ADDR);
  1069. if (i)
  1070. handle = fdt_get_phandle(blob, i);
  1071. if (handle) {
  1072. range[0] = cpu_to_fdt32(handle);
  1073. range[1] = cpu_to_fdt32(23);
  1074. }
  1075. }
  1076. /* these have broken usd_vsel */
  1077. if (strstr((const char *)info->model, "SP318-B") ||
  1078. strstr((const char *)info->model, "SP331-B"))
  1079. gpio_cfg[board_type].usd_vsel = 0;
  1080. /* GW522x-B adds WDOG1_B external reset */
  1081. if (rev < 'B')
  1082. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1083. }
  1084. /* GW520x-E adds WDOG1_B external reset */
  1085. else if (info->model[4] == '0' && rev < 'E')
  1086. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1087. break;
  1088. case GW53xx:
  1089. /* GW53xx-E adds WDOG1_B external reset */
  1090. if (rev < 'E')
  1091. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1092. break;
  1093. case GW54xx:
  1094. /*
  1095. * disable serial2 node for GW54xx for compatibility with older
  1096. * 3.10.x kernel that improperly had this node enabled in the DT
  1097. */
  1098. fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
  1099. 0);
  1100. /* GW54xx-E adds WDOG2_B external reset */
  1101. if (rev < 'E')
  1102. ft_board_wdog_fixup(blob, WDOG2_ADDR);
  1103. break;
  1104. case GW551x:
  1105. /*
  1106. * isolate CSI0_DATA_EN for GW551x-A to work around errata
  1107. * causing non functional digital video in (it is not hooked up)
  1108. */
  1109. if (rev == 'A') {
  1110. u32 *range = NULL;
  1111. int len;
  1112. const u32 *handle = NULL;
  1113. i = fdt_node_offset_by_compatible(blob, -1,
  1114. "fsl,imx-tda1997x-video");
  1115. if (i)
  1116. handle = fdt_getprop(blob, i, "pinctrl-0",
  1117. NULL);
  1118. if (handle)
  1119. i = fdt_node_offset_by_phandle(blob,
  1120. fdt32_to_cpu(*handle));
  1121. if (i)
  1122. range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
  1123. &len);
  1124. if (range) {
  1125. len /= sizeof(u32);
  1126. for (i = 0; i < len; i += 6) {
  1127. u32 mux_reg = fdt32_to_cpu(range[i+0]);
  1128. u32 conf_reg = fdt32_to_cpu(range[i+1]);
  1129. /* mux PAD_CSI0_DATA_EN to GPIO */
  1130. if (is_cpu_type(MXC_CPU_MX6Q) &&
  1131. mux_reg == 0x260 &&
  1132. conf_reg == 0x630)
  1133. range[i+3] = cpu_to_fdt32(0x5);
  1134. else if (!is_cpu_type(MXC_CPU_MX6Q) &&
  1135. mux_reg == 0x08c &&
  1136. conf_reg == 0x3a0)
  1137. range[i+3] = cpu_to_fdt32(0x5);
  1138. }
  1139. fdt_setprop_inplace(blob, i, "fsl,pins", range,
  1140. len);
  1141. }
  1142. /* set BT656 video format */
  1143. ft_sethdmiinfmt(blob, "yuv422bt656");
  1144. }
  1145. /* GW551x-C adds WDOG1_B external reset */
  1146. if (rev < 'C')
  1147. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1148. break;
  1149. case GW5901:
  1150. case GW5902:
  1151. /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
  1152. if (rev < 'B')
  1153. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1154. break;
  1155. }
  1156. /* Configure DIO */
  1157. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  1158. struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
  1159. char arg[10];
  1160. sprintf(arg, "dio%d", i);
  1161. if (!hwconfig(arg))
  1162. continue;
  1163. if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
  1164. {
  1165. phys_addr_t addr;
  1166. int off;
  1167. printf(" Enabling pwm%d for DIO%d\n",
  1168. cfg->pwm_param, i);
  1169. addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
  1170. off = fdt_node_offset_by_compat_reg(blob,
  1171. "fsl,imx6q-pwm",
  1172. addr);
  1173. if (off)
  1174. fdt_status_okay(blob, off);
  1175. }
  1176. }
  1177. /* remove no-1-8-v if UHS-I support is present */
  1178. if (gpio_cfg[board_type].usd_vsel) {
  1179. debug("Enabling UHS-I support\n");
  1180. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
  1181. USDHC3_ADDR);
  1182. if (i)
  1183. fdt_delprop(blob, i, "no-1-8-v");
  1184. }
  1185. #if defined(CONFIG_CMD_PCI)
  1186. if (!env_get("nopcifixup"))
  1187. ft_board_pci_fixup(blob, bd);
  1188. #endif
  1189. /*
  1190. * Peripheral Config:
  1191. * remove nodes by alias path if EEPROM config tells us the
  1192. * peripheral is not loaded on the board.
  1193. */
  1194. if (env_get("fdt_noconfig")) {
  1195. puts(" Skiping periperhal config (fdt_noconfig defined)\n");
  1196. return 0;
  1197. }
  1198. cfg = econfig;
  1199. while (cfg->name) {
  1200. if (!test_bit(cfg->bit, info->config)) {
  1201. fdt_del_node_and_alias(blob, cfg->dtalias ?
  1202. cfg->dtalias : cfg->name);
  1203. }
  1204. cfg++;
  1205. }
  1206. return 0;
  1207. }
  1208. #endif /* CONFIG_OF_BOARD_SETUP */
  1209. static struct mxc_serial_plat ventana_mxc_serial_plat = {
  1210. .reg = (struct mxc_uart *)UART2_BASE,
  1211. };
  1212. U_BOOT_DEVICE(ventana_serial) = {
  1213. .name = "serial_mxc",
  1214. .plat = &ventana_mxc_serial_plat,
  1215. };