lx2160a.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018-2020 NXP
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <dm/platform_data/serial_pl01x.h>
  10. #include <i2c.h>
  11. #include <malloc.h>
  12. #include <errno.h>
  13. #include <netdev.h>
  14. #include <fsl_ddr.h>
  15. #include <fsl_sec.h>
  16. #include <asm/io.h>
  17. #include <fdt_support.h>
  18. #include <linux/bitops.h>
  19. #include <linux/libfdt.h>
  20. #include <linux/delay.h>
  21. #include <fsl-mc/fsl_mc.h>
  22. #include <env_internal.h>
  23. #include <efi_loader.h>
  24. #include <asm/arch/mmu.h>
  25. #include <hwconfig.h>
  26. #include <asm/arch/clock.h>
  27. #include <asm/arch/config.h>
  28. #include <asm/arch/fsl_serdes.h>
  29. #include <asm/arch/soc.h>
  30. #include "../common/qixis.h"
  31. #include "../common/vid.h"
  32. #include <fsl_immap.h>
  33. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  34. #ifdef CONFIG_EMC2305
  35. #include "../common/emc2305.h"
  36. #endif
  37. #ifdef CONFIG_TARGET_LX2160AQDS
  38. #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
  39. #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
  40. #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
  41. #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
  42. #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
  43. #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
  44. #define SDHC1_BASE_PMUX_DSPI 2
  45. #define SDHC2_BASE_PMUX_DSPI 2
  46. #define IIC5_PMUX_SPI3 3
  47. #endif /* CONFIG_TARGET_LX2160AQDS */
  48. DECLARE_GLOBAL_DATA_PTR;
  49. static struct pl01x_serial_plat serial0 = {
  50. #if CONFIG_CONS_INDEX == 0
  51. .base = CONFIG_SYS_SERIAL0,
  52. #elif CONFIG_CONS_INDEX == 1
  53. .base = CONFIG_SYS_SERIAL1,
  54. #else
  55. #error "Unsupported console index value."
  56. #endif
  57. .type = TYPE_PL011,
  58. };
  59. U_BOOT_DEVICE(nxp_serial0) = {
  60. .name = "serial_pl01x",
  61. .plat = &serial0,
  62. };
  63. static struct pl01x_serial_plat serial1 = {
  64. .base = CONFIG_SYS_SERIAL1,
  65. .type = TYPE_PL011,
  66. };
  67. U_BOOT_DEVICE(nxp_serial1) = {
  68. .name = "serial_pl01x",
  69. .plat = &serial1,
  70. };
  71. int select_i2c_ch_pca9547(u8 ch)
  72. {
  73. int ret;
  74. #ifndef CONFIG_DM_I2C
  75. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  76. #else
  77. struct udevice *dev;
  78. ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  79. if (!ret)
  80. ret = dm_i2c_write(dev, 0, &ch, 1);
  81. #endif
  82. if (ret) {
  83. puts("PCA: failed to select proper channel\n");
  84. return ret;
  85. }
  86. return 0;
  87. }
  88. static void uart_get_clock(void)
  89. {
  90. serial0.clock = get_serial_clock();
  91. serial1.clock = get_serial_clock();
  92. }
  93. int board_early_init_f(void)
  94. {
  95. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  96. i2c_early_init_f();
  97. #endif
  98. /* get required clock for UART IP */
  99. uart_get_clock();
  100. #ifdef CONFIG_EMC2305
  101. select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
  102. emc2305_init(I2C_EMC2305_ADDR);
  103. set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
  104. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  105. #endif
  106. fsl_lsch3_early_init_f();
  107. return 0;
  108. }
  109. #ifdef CONFIG_OF_BOARD_FIXUP
  110. int board_fix_fdt(void *fdt)
  111. {
  112. char *reg_names, *reg_name;
  113. int names_len, old_name_len, new_name_len, remaining_names_len;
  114. struct str_map {
  115. char *old_str;
  116. char *new_str;
  117. } reg_names_map[] = {
  118. { "ccsr", "dbi" },
  119. { "pf_ctrl", "ctrl" }
  120. };
  121. int off = -1, i = 0;
  122. if (IS_SVR_REV(get_svr(), 1, 0))
  123. return 0;
  124. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
  125. while (off != -FDT_ERR_NOTFOUND) {
  126. fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
  127. strlen("fsl,ls-pcie") + 1);
  128. reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
  129. &names_len);
  130. if (!reg_names)
  131. continue;
  132. reg_name = reg_names;
  133. remaining_names_len = names_len - (reg_name - reg_names);
  134. i = 0;
  135. while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
  136. old_name_len = strlen(reg_names_map[i].old_str);
  137. new_name_len = strlen(reg_names_map[i].new_str);
  138. if (memcmp(reg_name, reg_names_map[i].old_str,
  139. old_name_len) == 0) {
  140. /* first only leave required bytes for new_str
  141. * and copy rest of the string after it
  142. */
  143. memcpy(reg_name + new_name_len,
  144. reg_name + old_name_len,
  145. remaining_names_len - old_name_len);
  146. /* Now copy new_str */
  147. memcpy(reg_name, reg_names_map[i].new_str,
  148. new_name_len);
  149. names_len -= old_name_len;
  150. names_len += new_name_len;
  151. i++;
  152. }
  153. reg_name = memchr(reg_name, '\0', remaining_names_len);
  154. if (!reg_name)
  155. break;
  156. reg_name += 1;
  157. remaining_names_len = names_len -
  158. (reg_name - reg_names);
  159. }
  160. fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
  161. off = fdt_node_offset_by_compatible(fdt, off,
  162. "fsl,lx2160a-pcie");
  163. }
  164. return 0;
  165. }
  166. #endif
  167. #if defined(CONFIG_TARGET_LX2160AQDS)
  168. void esdhc_dspi_status_fixup(void *blob)
  169. {
  170. const char esdhc0_path[] = "/soc/esdhc@2140000";
  171. const char esdhc1_path[] = "/soc/esdhc@2150000";
  172. const char dspi0_path[] = "/soc/spi@2100000";
  173. const char dspi1_path[] = "/soc/spi@2110000";
  174. const char dspi2_path[] = "/soc/spi@2120000";
  175. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  176. u32 sdhc1_base_pmux;
  177. u32 sdhc2_base_pmux;
  178. u32 iic5_pmux;
  179. /* Check RCW field sdhc1_base_pmux to enable/disable
  180. * esdhc0/dspi0 DT node
  181. */
  182. sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  183. & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
  184. sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
  185. if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
  186. do_fixup_by_path(blob, dspi0_path, "status", "okay",
  187. sizeof("okay"), 1);
  188. do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
  189. sizeof("disabled"), 1);
  190. } else {
  191. do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  192. sizeof("okay"), 1);
  193. do_fixup_by_path(blob, dspi0_path, "status", "disabled",
  194. sizeof("disabled"), 1);
  195. }
  196. /* Check RCW field sdhc2_base_pmux to enable/disable
  197. * esdhc1/dspi1 DT node
  198. */
  199. sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
  200. & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
  201. sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
  202. if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
  203. do_fixup_by_path(blob, dspi1_path, "status", "okay",
  204. sizeof("okay"), 1);
  205. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  206. sizeof("disabled"), 1);
  207. } else {
  208. do_fixup_by_path(blob, esdhc1_path, "status", "okay",
  209. sizeof("okay"), 1);
  210. do_fixup_by_path(blob, dspi1_path, "status", "disabled",
  211. sizeof("disabled"), 1);
  212. }
  213. /* Check RCW field IIC5 to enable dspi2 DT node */
  214. iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  215. & FSL_CHASSIS3_IIC5_PMUX_MASK;
  216. iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
  217. if (iic5_pmux == IIC5_PMUX_SPI3)
  218. do_fixup_by_path(blob, dspi2_path, "status", "okay",
  219. sizeof("okay"), 1);
  220. else
  221. do_fixup_by_path(blob, dspi2_path, "status", "disabled",
  222. sizeof("disabled"), 1);
  223. }
  224. #endif
  225. int esdhc_status_fixup(void *blob, const char *compat)
  226. {
  227. #if defined(CONFIG_TARGET_LX2160AQDS)
  228. /* Enable esdhc and dspi DT nodes based on RCW fields */
  229. esdhc_dspi_status_fixup(blob);
  230. #else
  231. /* Enable both esdhc DT nodes for LX2160ARDB */
  232. do_fixup_by_compat(blob, compat, "status", "okay",
  233. sizeof("okay"), 1);
  234. #endif
  235. return 0;
  236. }
  237. #if defined(CONFIG_VID)
  238. int i2c_multiplexer_select_vid_channel(u8 channel)
  239. {
  240. return select_i2c_ch_pca9547(channel);
  241. }
  242. int init_func_vid(void)
  243. {
  244. int set_vid;
  245. if (IS_SVR_REV(get_svr(), 1, 0))
  246. set_vid = adjust_vdd(800);
  247. else
  248. set_vid = adjust_vdd(0);
  249. if (set_vid < 0)
  250. printf("core voltage not adjusted\n");
  251. return 0;
  252. }
  253. #endif
  254. int checkboard(void)
  255. {
  256. enum boot_src src = get_boot_src();
  257. char buf[64];
  258. u8 sw;
  259. #ifdef CONFIG_TARGET_LX2160AQDS
  260. int clock;
  261. static const char *const freq[] = {"100", "125", "156.25",
  262. "161.13", "322.26", "", "", "",
  263. "", "", "", "", "", "", "",
  264. "100 separate SSCG"};
  265. #endif
  266. cpu_name(buf);
  267. #ifdef CONFIG_TARGET_LX2160AQDS
  268. printf("Board: %s-QDS, ", buf);
  269. #else
  270. printf("Board: %s-RDB, ", buf);
  271. #endif
  272. sw = QIXIS_READ(arch);
  273. printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
  274. if (src == BOOT_SOURCE_SD_MMC) {
  275. puts("SD\n");
  276. } else if (src == BOOT_SOURCE_SD_MMC2) {
  277. puts("eMMC\n");
  278. } else {
  279. sw = QIXIS_READ(brdcfg[0]);
  280. sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
  281. switch (sw) {
  282. case 0:
  283. case 4:
  284. puts("FlexSPI DEV#0\n");
  285. break;
  286. case 1:
  287. puts("FlexSPI DEV#1\n");
  288. break;
  289. case 2:
  290. case 3:
  291. puts("FlexSPI EMU\n");
  292. break;
  293. default:
  294. printf("invalid setting, xmap: %d\n", sw);
  295. break;
  296. }
  297. }
  298. #ifdef CONFIG_TARGET_LX2160AQDS
  299. printf("FPGA: v%d (%s), build %d",
  300. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  301. (int)qixis_read_minor());
  302. /* the timestamp string contains "\n" at the end */
  303. printf(" on %s", qixis_read_time(buf));
  304. puts("SERDES1 Reference : ");
  305. sw = QIXIS_READ(brdcfg[2]);
  306. clock = sw >> 4;
  307. printf("Clock1 = %sMHz ", freq[clock]);
  308. clock = sw & 0x0f;
  309. printf("Clock2 = %sMHz", freq[clock]);
  310. sw = QIXIS_READ(brdcfg[3]);
  311. puts("\nSERDES2 Reference : ");
  312. clock = sw >> 4;
  313. printf("Clock1 = %sMHz ", freq[clock]);
  314. clock = sw & 0x0f;
  315. printf("Clock2 = %sMHz", freq[clock]);
  316. sw = QIXIS_READ(brdcfg[12]);
  317. puts("\nSERDES3 Reference : ");
  318. clock = sw >> 4;
  319. printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
  320. #else
  321. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  322. puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
  323. puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
  324. puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
  325. #endif
  326. return 0;
  327. }
  328. #ifdef CONFIG_TARGET_LX2160AQDS
  329. /*
  330. * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
  331. */
  332. u8 qixis_esdhc_detect_quirk(void)
  333. {
  334. /*
  335. * SDHC1 Card ID:
  336. * Specifies the type of card installed in the SDHC1 adapter slot.
  337. * 000= (reserved)
  338. * 001= eMMC V4.5 adapter is installed.
  339. * 010= SD/MMC 3.3V adapter is installed.
  340. * 011= eMMC V4.4 adapter is installed.
  341. * 100= eMMC V5.0 adapter is installed.
  342. * 101= MMC card/Legacy (3.3V) adapter is installed.
  343. * 110= SDCard V2/V3 adapter installed.
  344. * 111= no adapter is installed.
  345. */
  346. return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
  347. QIXIS_ESDHC_NO_ADAPTER);
  348. }
  349. static void esdhc_adapter_card_ident(void)
  350. {
  351. u8 card_id, val;
  352. val = QIXIS_READ(sdhc1);
  353. card_id = val & QIXIS_SDID_MASK;
  354. switch (card_id) {
  355. case QIXIS_ESDHC_ADAPTER_TYPE_SD:
  356. /* Power cycle to card */
  357. val &= ~QIXIS_SDHC1_S1V3;
  358. QIXIS_WRITE(sdhc1, val);
  359. mdelay(1);
  360. val |= QIXIS_SDHC1_S1V3;
  361. QIXIS_WRITE(sdhc1, val);
  362. /* Route to SDHC1_VS */
  363. val = QIXIS_READ(brdcfg[11]);
  364. val |= QIXIS_SDHC1_VS;
  365. QIXIS_WRITE(brdcfg[11], val);
  366. break;
  367. default:
  368. break;
  369. }
  370. }
  371. int config_board_mux(void)
  372. {
  373. u8 reg11, reg5, reg13;
  374. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  375. u32 sdhc1_base_pmux;
  376. u32 sdhc2_base_pmux;
  377. u32 iic5_pmux;
  378. /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
  379. * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
  380. * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
  381. * Qixis and remote systems are isolated from the I2C1 bus.
  382. * Processor connections are still available.
  383. * SPI2 CS2_B controls EN25S64 SPI memory device.
  384. * SPI3 CS2_B controls EN25S64 SPI memory device.
  385. * EC2 connects to PHY #2 using RGMII protocol.
  386. * CLK_OUT connects to FPGA for clock measurement.
  387. */
  388. reg5 = QIXIS_READ(brdcfg[5]);
  389. reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
  390. QIXIS_WRITE(brdcfg[5], reg5);
  391. /* Check RCW field sdhc1_base_pmux
  392. * esdhc0 : sdhc1_base_pmux = 0
  393. * dspi0 : sdhc1_base_pmux = 2
  394. */
  395. sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  396. & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
  397. sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
  398. if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
  399. reg11 = QIXIS_READ(brdcfg[11]);
  400. reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
  401. QIXIS_WRITE(brdcfg[11], reg11);
  402. } else {
  403. /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
  404. * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
  405. * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
  406. */
  407. reg11 = QIXIS_READ(brdcfg[11]);
  408. reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
  409. QIXIS_WRITE(brdcfg[11], reg11);
  410. }
  411. /* Check RCW field sdhc2_base_pmux
  412. * esdhc1 : sdhc2_base_pmux = 0 (default)
  413. * dspi1 : sdhc2_base_pmux = 2
  414. */
  415. sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
  416. & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
  417. sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
  418. if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
  419. reg13 = QIXIS_READ(brdcfg[13]);
  420. reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
  421. QIXIS_WRITE(brdcfg[13], reg13);
  422. } else {
  423. reg13 = QIXIS_READ(brdcfg[13]);
  424. reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
  425. QIXIS_WRITE(brdcfg[13], reg13);
  426. }
  427. /* Check RCW field IIC5 to enable dspi2 DT nodei
  428. * dspi2: IIC5 = 3
  429. */
  430. iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  431. & FSL_CHASSIS3_IIC5_PMUX_MASK;
  432. iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
  433. if (iic5_pmux == IIC5_PMUX_SPI3) {
  434. /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
  435. reg11 = QIXIS_READ(brdcfg[11]);
  436. reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
  437. QIXIS_WRITE(brdcfg[11], reg11);
  438. /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
  439. * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
  440. * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
  441. */
  442. reg11 = QIXIS_READ(brdcfg[11]);
  443. reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
  444. QIXIS_WRITE(brdcfg[11], reg11);
  445. } else {
  446. /*
  447. * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
  448. * do not change it.
  449. * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
  450. */
  451. reg11 = QIXIS_READ(brdcfg[11]);
  452. if ((reg11 & 0x30) != 0x30) {
  453. reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
  454. QIXIS_WRITE(brdcfg[11], reg11);
  455. }
  456. /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
  457. * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
  458. * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
  459. */
  460. reg11 = QIXIS_READ(brdcfg[11]);
  461. reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
  462. QIXIS_WRITE(brdcfg[11], reg11);
  463. }
  464. return 0;
  465. }
  466. int board_early_init_r(void)
  467. {
  468. esdhc_adapter_card_ident();
  469. return 0;
  470. }
  471. #elif defined(CONFIG_TARGET_LX2160ARDB)
  472. int config_board_mux(void)
  473. {
  474. u8 brdcfg;
  475. brdcfg = QIXIS_READ(brdcfg[4]);
  476. /* The BRDCFG4 register controls general board configuration.
  477. *|-------------------------------------------|
  478. *|Field | Function |
  479. *|-------------------------------------------|
  480. *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
  481. *|CAN_EN | 0= CAN transceivers are disabled. |
  482. *| | 1= CAN transceivers are enabled. |
  483. *|-------------------------------------------|
  484. */
  485. brdcfg |= BIT_MASK(5);
  486. QIXIS_WRITE(brdcfg[4], brdcfg);
  487. return 0;
  488. }
  489. #else
  490. int config_board_mux(void)
  491. {
  492. return 0;
  493. }
  494. #endif
  495. unsigned long get_board_sys_clk(void)
  496. {
  497. #ifdef CONFIG_TARGET_LX2160AQDS
  498. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  499. switch (sysclk_conf & 0x03) {
  500. case QIXIS_SYSCLK_100:
  501. return 100000000;
  502. case QIXIS_SYSCLK_125:
  503. return 125000000;
  504. case QIXIS_SYSCLK_133:
  505. return 133333333;
  506. }
  507. return 100000000;
  508. #else
  509. return 100000000;
  510. #endif
  511. }
  512. unsigned long get_board_ddr_clk(void)
  513. {
  514. #ifdef CONFIG_TARGET_LX2160AQDS
  515. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  516. switch ((ddrclk_conf & 0x30) >> 4) {
  517. case QIXIS_DDRCLK_100:
  518. return 100000000;
  519. case QIXIS_DDRCLK_125:
  520. return 125000000;
  521. case QIXIS_DDRCLK_133:
  522. return 133333333;
  523. }
  524. return 100000000;
  525. #else
  526. return 100000000;
  527. #endif
  528. }
  529. int board_init(void)
  530. {
  531. #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
  532. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  533. #endif
  534. #ifdef CONFIG_ENV_IS_NOWHERE
  535. gd->env_addr = (ulong)&default_environment[0];
  536. #endif
  537. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  538. #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
  539. /* invert AQR107 IRQ pins polarity */
  540. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
  541. #endif
  542. #ifdef CONFIG_FSL_CAAM
  543. sec_init();
  544. #endif
  545. #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
  546. pci_init();
  547. #endif
  548. return 0;
  549. }
  550. void detail_board_ddr_info(void)
  551. {
  552. int i;
  553. u64 ddr_size = 0;
  554. puts("\nDDR ");
  555. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  556. ddr_size += gd->bd->bi_dram[i].size;
  557. print_size(ddr_size, "");
  558. print_ddr_info(0);
  559. }
  560. #ifdef CONFIG_MISC_INIT_R
  561. int misc_init_r(void)
  562. {
  563. config_board_mux();
  564. return 0;
  565. }
  566. #endif
  567. #ifdef CONFIG_FSL_MC_ENET
  568. extern int fdt_fixup_board_phy(void *fdt);
  569. void fdt_fixup_board_enet(void *fdt)
  570. {
  571. int offset;
  572. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  573. if (offset < 0)
  574. offset = fdt_path_offset(fdt, "/fsl-mc");
  575. if (offset < 0) {
  576. printf("%s: fsl-mc node not found in device tree (error %d)\n",
  577. __func__, offset);
  578. return;
  579. }
  580. if (get_mc_boot_status() == 0 &&
  581. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
  582. fdt_status_okay(fdt, offset);
  583. #ifndef CONFIG_DM_ETH
  584. fdt_fixup_board_phy(fdt);
  585. #endif
  586. } else {
  587. fdt_status_fail(fdt, offset);
  588. }
  589. }
  590. void board_quiesce_devices(void)
  591. {
  592. fsl_mc_ldpaa_exit(gd->bd);
  593. }
  594. #endif
  595. #ifdef CONFIG_OF_BOARD_SETUP
  596. int ft_board_setup(void *blob, struct bd_info *bd)
  597. {
  598. int i;
  599. u16 mc_memory_bank = 0;
  600. u64 *base;
  601. u64 *size;
  602. u64 mc_memory_base = 0;
  603. u64 mc_memory_size = 0;
  604. u16 total_memory_banks;
  605. ft_cpu_setup(blob, bd);
  606. fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
  607. if (mc_memory_base != 0)
  608. mc_memory_bank++;
  609. total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
  610. base = calloc(total_memory_banks, sizeof(u64));
  611. size = calloc(total_memory_banks, sizeof(u64));
  612. /* fixup DT for the three GPP DDR banks */
  613. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  614. base[i] = gd->bd->bi_dram[i].start;
  615. size[i] = gd->bd->bi_dram[i].size;
  616. }
  617. #ifdef CONFIG_RESV_RAM
  618. /* reduce size if reserved memory is within this bank */
  619. if (gd->arch.resv_ram >= base[0] &&
  620. gd->arch.resv_ram < base[0] + size[0])
  621. size[0] = gd->arch.resv_ram - base[0];
  622. else if (gd->arch.resv_ram >= base[1] &&
  623. gd->arch.resv_ram < base[1] + size[1])
  624. size[1] = gd->arch.resv_ram - base[1];
  625. else if (gd->arch.resv_ram >= base[2] &&
  626. gd->arch.resv_ram < base[2] + size[2])
  627. size[2] = gd->arch.resv_ram - base[2];
  628. #endif
  629. if (mc_memory_base != 0) {
  630. for (i = 0; i <= total_memory_banks; i++) {
  631. if (base[i] == 0 && size[i] == 0) {
  632. base[i] = mc_memory_base;
  633. size[i] = mc_memory_size;
  634. break;
  635. }
  636. }
  637. }
  638. fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
  639. #ifdef CONFIG_USB
  640. fsl_fdt_fixup_dr_usb(blob, bd);
  641. #endif
  642. #ifdef CONFIG_FSL_MC_ENET
  643. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  644. fdt_fixup_board_enet(blob);
  645. #endif
  646. fdt_fixup_icid(blob);
  647. return 0;
  648. }
  649. #endif
  650. void qixis_dump_switch(void)
  651. {
  652. int i, nr_of_cfgsw;
  653. QIXIS_WRITE(cms[0], 0x00);
  654. nr_of_cfgsw = QIXIS_READ(cms[1]);
  655. puts("DIP switch settings dump:\n");
  656. for (i = 1; i <= nr_of_cfgsw; i++) {
  657. QIXIS_WRITE(cms[0], i);
  658. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  659. }
  660. }