omapl138_lcdk.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Based on da850evm.c. Original Copyrights follow:
  6. *
  7. * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
  8. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  9. */
  10. #include <common.h>
  11. #include <env.h>
  12. #include <i2c.h>
  13. #include <init.h>
  14. #include <net.h>
  15. #include <asm/arch/hardware.h>
  16. #include <asm/ti-common/davinci_nand.h>
  17. #include <asm/io.h>
  18. #include <ns16550.h>
  19. #include <dm/platdata.h>
  20. #include <linux/errno.h>
  21. #include <asm/mach-types.h>
  22. #include <asm/arch/davinci_misc.h>
  23. #ifdef CONFIG_MMC_DAVINCI
  24. #include <mmc.h>
  25. #include <asm/arch/sdmmc_defs.h>
  26. #endif
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
  29. #ifdef CONFIG_MMC_DAVINCI
  30. /* MMC0 pin muxer settings */
  31. const struct pinmux_config mmc0_pins[] = {
  32. /* GP0[11] is required for SD to work on Rev 3 EVMs */
  33. { pinmux(0), 8, 4 }, /* GP0[11] */
  34. { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
  35. { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
  36. { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
  37. { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
  38. { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
  39. { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
  40. /* LCDK supports only 4-bit mode, remaining pins are not configured */
  41. };
  42. #endif
  43. /* UART pin muxer settings */
  44. static const struct pinmux_config uart_pins[] = {
  45. { pinmux(0), 4, 6 },
  46. { pinmux(0), 4, 7 },
  47. { pinmux(4), 2, 4 },
  48. { pinmux(4), 2, 5 }
  49. };
  50. #ifdef CONFIG_DRIVER_TI_EMAC
  51. static const struct pinmux_config emac_pins[] = {
  52. { pinmux(2), 8, 1 },
  53. { pinmux(2), 8, 2 },
  54. { pinmux(2), 8, 3 },
  55. { pinmux(2), 8, 4 },
  56. { pinmux(2), 8, 5 },
  57. { pinmux(2), 8, 6 },
  58. { pinmux(2), 8, 7 },
  59. { pinmux(3), 8, 0 },
  60. { pinmux(3), 8, 1 },
  61. { pinmux(3), 8, 2 },
  62. { pinmux(3), 8, 3 },
  63. { pinmux(3), 8, 4 },
  64. { pinmux(3), 8, 5 },
  65. { pinmux(3), 8, 6 },
  66. { pinmux(3), 8, 7 },
  67. { pinmux(4), 8, 0 },
  68. { pinmux(4), 8, 1 }
  69. };
  70. #endif /* CONFIG_DRIVER_TI_EMAC */
  71. /* I2C pin muxer settings */
  72. static const struct pinmux_config i2c_pins[] = {
  73. { pinmux(4), 2, 2 },
  74. { pinmux(4), 2, 3 }
  75. };
  76. #ifdef CONFIG_NAND_DAVINCI
  77. const struct pinmux_config nand_pins[] = {
  78. { pinmux(7), 1, 1 },
  79. { pinmux(7), 1, 2 },
  80. { pinmux(7), 1, 4 },
  81. { pinmux(7), 1, 5 },
  82. { pinmux(8), 1, 0 },
  83. { pinmux(8), 1, 1 },
  84. { pinmux(8), 1, 2 },
  85. { pinmux(8), 1, 3 },
  86. { pinmux(8), 1, 4 },
  87. { pinmux(8), 1, 5 },
  88. { pinmux(8), 1, 6 },
  89. { pinmux(8), 1, 7 },
  90. { pinmux(9), 1, 0 },
  91. { pinmux(9), 1, 1 },
  92. { pinmux(9), 1, 2 },
  93. { pinmux(9), 1, 3 },
  94. { pinmux(9), 1, 4 },
  95. { pinmux(9), 1, 5 },
  96. { pinmux(9), 1, 6 },
  97. { pinmux(9), 1, 7 },
  98. { pinmux(12), 1, 5 },
  99. { pinmux(12), 1, 6 }
  100. };
  101. #endif
  102. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  103. #define HAS_RMII 1
  104. #else
  105. #define HAS_RMII 0
  106. #endif
  107. const struct pinmux_resource pinmuxes[] = {
  108. PINMUX_ITEM(uart_pins),
  109. PINMUX_ITEM(i2c_pins),
  110. #ifdef CONFIG_NAND_DAVINCI
  111. PINMUX_ITEM(nand_pins),
  112. #endif
  113. };
  114. const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
  115. const struct lpsc_resource lpsc[] = {
  116. { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
  117. { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
  118. { DAVINCI_LPSC_EMAC }, /* image download */
  119. { DAVINCI_LPSC_UART2 }, /* console */
  120. { DAVINCI_LPSC_GPIO },
  121. #ifdef CONFIG_MMC_DAVINCI
  122. { DAVINCI_LPSC_MMC_SD },
  123. #endif
  124. };
  125. const int lpsc_size = ARRAY_SIZE(lpsc);
  126. #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
  127. #define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
  128. #endif
  129. /*
  130. * get_board_rev() - setup to pass kernel board revision information
  131. * Returns:
  132. * bit[0-3] Maximum cpu clock rate supported by onboard SoC
  133. * 0000b - 300 MHz
  134. * 0001b - 372 MHz
  135. * 0010b - 408 MHz
  136. * 0011b - 456 MHz
  137. */
  138. u32 get_board_rev(void)
  139. {
  140. return 0;
  141. }
  142. int board_early_init_f(void)
  143. {
  144. /*
  145. * Power on required peripherals
  146. * ARM does not have access by default to PSC0 and PSC1
  147. * assuming here that the DSP bootloader has set the IOPU
  148. * such that PSC access is available to ARM
  149. */
  150. if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
  151. return 1;
  152. return 0;
  153. }
  154. int board_init(void)
  155. {
  156. irq_init();
  157. /* arch number of the board */
  158. gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
  159. /* address of boot parameters */
  160. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  161. /* setup the SUSPSRC for ARM to control emulation suspend */
  162. writel(readl(&davinci_syscfg_regs->suspsrc) &
  163. ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
  164. DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
  165. DAVINCI_SYSCFG_SUSPSRC_UART2),
  166. &davinci_syscfg_regs->suspsrc);
  167. /* configure pinmux settings */
  168. if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
  169. return 1;
  170. #ifdef CONFIG_NAND_DAVINCI
  171. /*
  172. * NAND CS setup - cycle counts based on da850evm NAND timings in the
  173. * Linux kernel @ 25MHz EMIFA
  174. */
  175. writel((DAVINCI_ABCR_WSETUP(15) |
  176. DAVINCI_ABCR_WSTROBE(63) |
  177. DAVINCI_ABCR_WHOLD(7) |
  178. DAVINCI_ABCR_RSETUP(15) |
  179. DAVINCI_ABCR_RSTROBE(63) |
  180. DAVINCI_ABCR_RHOLD(7) |
  181. DAVINCI_ABCR_TA(3) |
  182. DAVINCI_ABCR_ASIZE_16BIT),
  183. &davinci_emif_regs->ab2cr); /* CS3 */
  184. #endif
  185. #ifdef CONFIG_MMC_DAVINCI
  186. if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
  187. return 1;
  188. #endif
  189. #ifdef CONFIG_DRIVER_TI_EMAC
  190. if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
  191. return 1;
  192. davinci_emac_mii_mode_sel(HAS_RMII);
  193. #endif /* CONFIG_DRIVER_TI_EMAC */
  194. /* enable the console UART */
  195. writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
  196. DAVINCI_UART_PWREMU_MGMT_UTRST),
  197. &davinci_uart2_ctrl_regs->pwremu_mgmt);
  198. return 0;
  199. }
  200. #define CFG_MAC_ADDR_SPI_BUS 0
  201. #define CFG_MAC_ADDR_SPI_CS 0
  202. #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  203. #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
  204. #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
  205. static int get_mac_addr(u8 *addr)
  206. {
  207. /* Need to find a way to get MAC ADDRESS */
  208. return 0;
  209. }
  210. void dsp_lpsc_on(unsigned domain, unsigned int id)
  211. {
  212. dv_reg_p mdstat, mdctl, ptstat, ptcmd;
  213. struct davinci_psc_regs *psc_regs;
  214. psc_regs = davinci_psc0_regs;
  215. mdstat = &psc_regs->psc0.mdstat[id];
  216. mdctl = &psc_regs->psc0.mdctl[id];
  217. ptstat = &psc_regs->ptstat;
  218. ptcmd = &psc_regs->ptcmd;
  219. while (*ptstat & (0x1 << domain))
  220. ;
  221. if ((*mdstat & 0x1f) == 0x03)
  222. return; /* Already on and enabled */
  223. *mdctl |= 0x03;
  224. *ptcmd = 0x1 << domain;
  225. while (*ptstat & (0x1 << domain))
  226. ;
  227. while ((*mdstat & 0x1f) != 0x03)
  228. ; /* Probably an overkill... */
  229. }
  230. static void dspwake(void)
  231. {
  232. unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
  233. /* if the device is ARM only, return */
  234. if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
  235. return;
  236. if (!strcmp(env_get("dspwake"), "no"))
  237. return;
  238. *resetvect++ = 0x1E000; /* DSP Idle */
  239. /* clear out the next 10 words as NOP */
  240. memset(resetvect, 0, sizeof(unsigned) * 10);
  241. /* setup the DSP reset vector */
  242. REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
  243. dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
  244. REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
  245. }
  246. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  247. /**
  248. * rmii_hw_init
  249. *
  250. */
  251. int rmii_hw_init(void)
  252. {
  253. return 0;
  254. }
  255. #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
  256. int misc_init_r(void)
  257. {
  258. uint8_t tmp[20], addr[10];
  259. if (env_get("ethaddr") == NULL) {
  260. /* Read Ethernet MAC address from EEPROM */
  261. if (dvevm_read_mac_address(addr)) {
  262. /* Set Ethernet MAC address from EEPROM */
  263. davinci_sync_env_enetaddr(addr);
  264. } else {
  265. get_mac_addr(addr);
  266. }
  267. if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
  268. sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
  269. addr[0], addr[1], addr[2], addr[3], addr[4],
  270. addr[5]);
  271. env_set("ethaddr", (char *)tmp);
  272. } else {
  273. printf("Invalid MAC address read.\n");
  274. }
  275. }
  276. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  277. /* Select RMII fucntion through the expander */
  278. if (rmii_hw_init())
  279. printf("RMII hardware init failed!!!\n");
  280. #endif
  281. dspwake();
  282. return 0;
  283. }
  284. #if !CONFIG_IS_ENABLED(DM_MMC)
  285. #ifdef CONFIG_MMC_DAVINCI
  286. static struct davinci_mmc mmc_sd0 = {
  287. .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
  288. .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
  289. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  290. };
  291. int board_mmc_init(struct bd_info *bis)
  292. {
  293. mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
  294. /* Add slot-0 to mmc subsystem */
  295. return davinci_mmc_init(bis, &mmc_sd0);
  296. }
  297. #endif
  298. #endif
  299. #ifdef CONFIG_SPL_BUILD
  300. static const struct ns16550_plat serial_pdata = {
  301. .base = DAVINCI_UART2_BASE,
  302. .reg_shift = 2,
  303. .clock = 228000000,
  304. .fcr = UART_FCR_DEFVAL,
  305. };
  306. U_BOOT_DEVICE(omapl138_uart) = {
  307. .name = "ns16550_serial",
  308. .plat = &serial_pdata,
  309. };
  310. static const struct davinci_mmc_plat mmc_plat = {
  311. .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
  312. .cfg = {
  313. .f_min = 200000,
  314. .f_max = 25000000,
  315. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  316. .host_caps = MMC_MODE_4BIT,
  317. .b_max = DAVINCI_MAX_BLOCKS,
  318. .name = "da830-mmc",
  319. },
  320. };
  321. U_BOOT_DEVICE(omapl138_mmc) = {
  322. .name = "ti_da830_mmc",
  323. .plat = &mmc_plat,
  324. };
  325. void spl_board_init(void)
  326. {
  327. davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins));
  328. }
  329. #endif