total_compute.c 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2020 Arm Limited
  4. * Usama Arif <usama.arif@arm.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <dm/platform_data/serial_pl01x.h>
  9. #include <asm/armv8/mmu.h>
  10. static const struct pl01x_serial_plat serial_plat = {
  11. .base = UART0_BASE,
  12. .type = TYPE_PL011,
  13. .clock = CONFIG_PL011_CLOCK,
  14. };
  15. U_BOOT_DEVICE(total_compute_serials) = {
  16. .name = "serial_pl01x",
  17. .plat = &serial_plat,
  18. };
  19. static struct mm_region total_compute_mem_map[] = {
  20. {
  21. .virt = 0x0UL,
  22. .phys = 0x0UL,
  23. .size = 0x80000000UL,
  24. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  25. PTE_BLOCK_NON_SHARE |
  26. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  27. }, {
  28. .virt = 0x80000000UL,
  29. .phys = 0x80000000UL,
  30. .size = 0xff80000000UL,
  31. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  32. PTE_BLOCK_INNER_SHARE
  33. }, {
  34. /* List terminator */
  35. 0,
  36. }
  37. };
  38. struct mm_region *mem_map = total_compute_mem_map;
  39. int board_init(void)
  40. {
  41. return 0;
  42. }
  43. int dram_init(void)
  44. {
  45. gd->ram_size = PHYS_SDRAM_1_SIZE;
  46. return 0;
  47. }
  48. int dram_init_banksize(void)
  49. {
  50. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  51. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  52. return 0;
  53. }
  54. /* Nothing to be done here as handled by PSCI interface */
  55. void reset_cpu(ulong addr)
  56. {
  57. }