mpspec.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. *
  5. * Adapted from coreboot src/arch/x86/boot/mpspec.c
  6. */
  7. #include <common.h>
  8. #include <cpu.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <log.h>
  13. #include <asm/cpu.h>
  14. #include <asm/irq.h>
  15. #include <asm/ioapic.h>
  16. #include <asm/lapic.h>
  17. #include <asm/mpspec.h>
  18. #include <asm/tables.h>
  19. #include <dm/uclass-internal.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. static bool isa_irq_occupied[16];
  22. struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf)
  23. {
  24. ulong mc;
  25. memcpy(mf->mpf_signature, MPF_SIGNATURE, 4);
  26. mf->mpf_physptr = (ulong)mf + sizeof(struct mp_floating_table);
  27. mf->mpf_length = 1;
  28. mf->mpf_spec = MPSPEC_V14;
  29. mf->mpf_checksum = 0;
  30. /* We don't use the default configuration table */
  31. mf->mpf_feature1 = 0;
  32. /* Indicate that virtual wire mode is always implemented */
  33. mf->mpf_feature2 = 0;
  34. mf->mpf_feature3 = 0;
  35. mf->mpf_feature4 = 0;
  36. mf->mpf_feature5 = 0;
  37. mf->mpf_checksum = table_compute_checksum(mf, mf->mpf_length * 16);
  38. mc = (ulong)mf + sizeof(struct mp_floating_table);
  39. return (struct mp_config_table *)mc;
  40. }
  41. void mp_config_table_init(struct mp_config_table *mc)
  42. {
  43. memcpy(mc->mpc_signature, MPC_SIGNATURE, 4);
  44. mc->mpc_length = sizeof(struct mp_config_table);
  45. mc->mpc_spec = MPSPEC_V14;
  46. mc->mpc_checksum = 0;
  47. mc->mpc_oemptr = 0;
  48. mc->mpc_oemsize = 0;
  49. mc->mpc_entry_count = 0;
  50. mc->mpc_lapic = LAPIC_DEFAULT_BASE;
  51. mc->mpe_length = 0;
  52. mc->mpe_checksum = 0;
  53. mc->reserved = 0;
  54. /* The oem/product id fields are exactly 8/12 bytes long */
  55. table_fill_string(mc->mpc_oem, CONFIG_SYS_VENDOR, 8, ' ');
  56. table_fill_string(mc->mpc_product, CONFIG_SYS_BOARD, 12, ' ');
  57. }
  58. void mp_write_processor(struct mp_config_table *mc)
  59. {
  60. struct mpc_config_processor *mpc;
  61. struct udevice *dev;
  62. u8 boot_apicid, apicver;
  63. u32 cpusignature, cpufeature;
  64. struct cpuid_result result;
  65. boot_apicid = lapicid();
  66. apicver = lapic_read(LAPIC_LVR) & 0xff;
  67. result = cpuid(1);
  68. cpusignature = result.eax;
  69. cpufeature = result.edx;
  70. for (uclass_find_first_device(UCLASS_CPU, &dev);
  71. dev;
  72. uclass_find_next_device(&dev)) {
  73. struct cpu_plat *plat = dev_get_parent_plat(dev);
  74. u8 cpuflag = MPC_CPU_EN;
  75. if (!device_active(dev))
  76. continue;
  77. mpc = (struct mpc_config_processor *)mp_next_mpc_entry(mc);
  78. mpc->mpc_type = MP_PROCESSOR;
  79. mpc->mpc_apicid = plat->cpu_id;
  80. mpc->mpc_apicver = apicver;
  81. if (boot_apicid == plat->cpu_id)
  82. cpuflag |= MPC_CPU_BP;
  83. mpc->mpc_cpuflag = cpuflag;
  84. mpc->mpc_cpusignature = cpusignature;
  85. mpc->mpc_cpufeature = cpufeature;
  86. mpc->mpc_reserved[0] = 0;
  87. mpc->mpc_reserved[1] = 0;
  88. mp_add_mpc_entry(mc, sizeof(*mpc));
  89. }
  90. }
  91. void mp_write_bus(struct mp_config_table *mc, int id, const char *bustype)
  92. {
  93. struct mpc_config_bus *mpc;
  94. mpc = (struct mpc_config_bus *)mp_next_mpc_entry(mc);
  95. mpc->mpc_type = MP_BUS;
  96. mpc->mpc_busid = id;
  97. memcpy(mpc->mpc_bustype, bustype, 6);
  98. mp_add_mpc_entry(mc, sizeof(*mpc));
  99. }
  100. void mp_write_ioapic(struct mp_config_table *mc, int id, int ver, u32 apicaddr)
  101. {
  102. struct mpc_config_ioapic *mpc;
  103. mpc = (struct mpc_config_ioapic *)mp_next_mpc_entry(mc);
  104. mpc->mpc_type = MP_IOAPIC;
  105. mpc->mpc_apicid = id;
  106. mpc->mpc_apicver = ver;
  107. mpc->mpc_flags = MPC_APIC_USABLE;
  108. mpc->mpc_apicaddr = apicaddr;
  109. mp_add_mpc_entry(mc, sizeof(*mpc));
  110. }
  111. void mp_write_intsrc(struct mp_config_table *mc, int irqtype, int irqflag,
  112. int srcbus, int srcbusirq, int dstapic, int dstirq)
  113. {
  114. struct mpc_config_intsrc *mpc;
  115. mpc = (struct mpc_config_intsrc *)mp_next_mpc_entry(mc);
  116. mpc->mpc_type = MP_INTSRC;
  117. mpc->mpc_irqtype = irqtype;
  118. mpc->mpc_irqflag = irqflag;
  119. mpc->mpc_srcbus = srcbus;
  120. mpc->mpc_srcbusirq = srcbusirq;
  121. mpc->mpc_dstapic = dstapic;
  122. mpc->mpc_dstirq = dstirq;
  123. mp_add_mpc_entry(mc, sizeof(*mpc));
  124. }
  125. void mp_write_pci_intsrc(struct mp_config_table *mc, int irqtype,
  126. int srcbus, int dev, int pin, int dstapic, int dstirq)
  127. {
  128. u8 srcbusirq = (dev << 2) | (pin - 1);
  129. mp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
  130. srcbus, srcbusirq, dstapic, dstirq);
  131. }
  132. void mp_write_lintsrc(struct mp_config_table *mc, int irqtype, int irqflag,
  133. int srcbus, int srcbusirq, int destapic, int destlint)
  134. {
  135. struct mpc_config_lintsrc *mpc;
  136. mpc = (struct mpc_config_lintsrc *)mp_next_mpc_entry(mc);
  137. mpc->mpc_type = MP_LINTSRC;
  138. mpc->mpc_irqtype = irqtype;
  139. mpc->mpc_irqflag = irqflag;
  140. mpc->mpc_srcbusid = srcbus;
  141. mpc->mpc_srcbusirq = srcbusirq;
  142. mpc->mpc_destapic = destapic;
  143. mpc->mpc_destlint = destlint;
  144. mp_add_mpc_entry(mc, sizeof(*mpc));
  145. }
  146. void mp_write_address_space(struct mp_config_table *mc,
  147. int busid, int addr_type,
  148. u32 addr_base_low, u32 addr_base_high,
  149. u32 addr_length_low, u32 addr_length_high)
  150. {
  151. struct mp_ext_system_address_space *mpe;
  152. mpe = (struct mp_ext_system_address_space *)mp_next_mpe_entry(mc);
  153. mpe->mpe_type = MPE_SYSTEM_ADDRESS_SPACE;
  154. mpe->mpe_length = sizeof(*mpe);
  155. mpe->mpe_busid = busid;
  156. mpe->mpe_addr_type = addr_type;
  157. mpe->mpe_addr_base_low = addr_base_low;
  158. mpe->mpe_addr_base_high = addr_base_high;
  159. mpe->mpe_addr_length_low = addr_length_low;
  160. mpe->mpe_addr_length_high = addr_length_high;
  161. mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
  162. }
  163. void mp_write_bus_hierarchy(struct mp_config_table *mc,
  164. int busid, int bus_info, int parent_busid)
  165. {
  166. struct mp_ext_bus_hierarchy *mpe;
  167. mpe = (struct mp_ext_bus_hierarchy *)mp_next_mpe_entry(mc);
  168. mpe->mpe_type = MPE_BUS_HIERARCHY;
  169. mpe->mpe_length = sizeof(*mpe);
  170. mpe->mpe_busid = busid;
  171. mpe->mpe_bus_info = bus_info;
  172. mpe->mpe_parent_busid = parent_busid;
  173. mpe->reserved[0] = 0;
  174. mpe->reserved[1] = 0;
  175. mpe->reserved[2] = 0;
  176. mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
  177. }
  178. void mp_write_compat_address_space(struct mp_config_table *mc, int busid,
  179. int addr_modifier, u32 range_list)
  180. {
  181. struct mp_ext_compat_address_space *mpe;
  182. mpe = (struct mp_ext_compat_address_space *)mp_next_mpe_entry(mc);
  183. mpe->mpe_type = MPE_COMPAT_ADDRESS_SPACE;
  184. mpe->mpe_length = sizeof(*mpe);
  185. mpe->mpe_busid = busid;
  186. mpe->mpe_addr_modifier = addr_modifier;
  187. mpe->mpe_range_list = range_list;
  188. mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
  189. }
  190. u32 mptable_finalize(struct mp_config_table *mc)
  191. {
  192. ulong end;
  193. mc->mpe_checksum = table_compute_checksum((void *)mp_next_mpc_entry(mc),
  194. mc->mpe_length);
  195. mc->mpc_checksum = table_compute_checksum(mc, mc->mpc_length);
  196. end = mp_next_mpe_entry(mc);
  197. debug("Write the MP table at: %lx - %lx\n", (ulong)mc, end);
  198. return end;
  199. }
  200. static void mptable_add_isa_interrupts(struct mp_config_table *mc, int bus_isa,
  201. int apicid, int external_int2)
  202. {
  203. int i;
  204. mp_write_intsrc(mc, external_int2 ? MP_INT : MP_EXTINT,
  205. MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  206. bus_isa, 0, apicid, 0);
  207. mp_write_intsrc(mc, MP_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  208. bus_isa, 1, apicid, 1);
  209. mp_write_intsrc(mc, external_int2 ? MP_EXTINT : MP_INT,
  210. MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  211. bus_isa, 0, apicid, 2);
  212. for (i = 3; i < 16; i++) {
  213. /*
  214. * Do not write ISA interrupt entry if it is already occupied
  215. * by the platform devices.
  216. */
  217. if (isa_irq_occupied[i])
  218. continue;
  219. mp_write_intsrc(mc, MP_INT,
  220. MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  221. bus_isa, i, apicid, i);
  222. }
  223. }
  224. /*
  225. * Check duplicated I/O interrupt assignment table entry, to make sure
  226. * there is only one entry with the given bus, device and interrupt pin.
  227. */
  228. static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base,
  229. int entry_num, int bus, int device, int pin)
  230. {
  231. struct mpc_config_intsrc *intsrc = intsrc_base;
  232. int i;
  233. for (i = 0; i < entry_num; i++) {
  234. if (intsrc->mpc_srcbus == bus &&
  235. intsrc->mpc_srcbusirq == ((device << 2) | (pin - 1)))
  236. break;
  237. intsrc++;
  238. }
  239. return (i == entry_num) ? false : true;
  240. }
  241. /* TODO: move this to driver model */
  242. __weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
  243. {
  244. /* PIRQ[A-H] are connected to I/O APIC INTPIN#16-23 */
  245. return pirq + 16;
  246. }
  247. static int mptable_add_intsrc(struct mp_config_table *mc,
  248. int bus_isa, int apicid)
  249. {
  250. struct mpc_config_intsrc *intsrc_base;
  251. int intsrc_entries = 0;
  252. const void *blob = gd->fdt_blob;
  253. struct udevice *dev;
  254. int len, count;
  255. const u32 *cell;
  256. int i, ret;
  257. ret = uclass_first_device_err(UCLASS_IRQ, &dev);
  258. if (ret && ret != -ENODEV) {
  259. debug("%s: Cannot find irq router node\n", __func__);
  260. return ret;
  261. }
  262. /* Get I/O interrupt information from device tree */
  263. cell = fdt_getprop(blob, dev_of_offset(dev), "intel,pirq-routing",
  264. &len);
  265. if (!cell)
  266. return -ENOENT;
  267. if ((len % sizeof(struct pirq_routing)) == 0)
  268. count = len / sizeof(struct pirq_routing);
  269. else
  270. return -EINVAL;
  271. intsrc_base = (struct mpc_config_intsrc *)mp_next_mpc_entry(mc);
  272. for (i = 0; i < count; i++) {
  273. struct pirq_routing pr;
  274. int bus, dev, func;
  275. int dstirq;
  276. pr.bdf = fdt_addr_to_cpu(cell[0]);
  277. pr.pin = fdt_addr_to_cpu(cell[1]);
  278. pr.pirq = fdt_addr_to_cpu(cell[2]);
  279. bus = PCI_BUS(pr.bdf);
  280. dev = PCI_DEV(pr.bdf);
  281. func = PCI_FUNC(pr.bdf);
  282. if (check_dup_entry(intsrc_base, intsrc_entries,
  283. bus, dev, pr.pin)) {
  284. debug("found entry for bus %d device %d INT%c, skipping\n",
  285. bus, dev, 'A' + pr.pin - 1);
  286. cell += sizeof(struct pirq_routing) / sizeof(u32);
  287. continue;
  288. }
  289. dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq);
  290. /*
  291. * For PIRQ which is connected to I/O APIC interrupt pin#0-15,
  292. * mark it as occupied so that we can skip it later.
  293. */
  294. if (dstirq < 16)
  295. isa_irq_occupied[dstirq] = true;
  296. mp_write_pci_intsrc(mc, MP_INT, bus, dev, pr.pin,
  297. apicid, dstirq);
  298. intsrc_entries++;
  299. cell += sizeof(struct pirq_routing) / sizeof(u32);
  300. }
  301. /* Legacy Interrupts */
  302. debug("Writing ISA IRQs\n");
  303. mptable_add_isa_interrupts(mc, bus_isa, apicid, 0);
  304. return 0;
  305. }
  306. static void mptable_add_lintsrc(struct mp_config_table *mc, int bus_isa)
  307. {
  308. mp_write_lintsrc(mc, MP_EXTINT,
  309. MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  310. bus_isa, 0, MP_APIC_ALL, 0);
  311. mp_write_lintsrc(mc, MP_NMI,
  312. MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  313. bus_isa, 0, MP_APIC_ALL, 1);
  314. }
  315. ulong write_mp_table(ulong addr)
  316. {
  317. struct mp_config_table *mc;
  318. int ioapic_id, ioapic_ver;
  319. int bus_isa = 0xff;
  320. int ret;
  321. ulong end;
  322. /* 16 byte align the table address */
  323. addr = ALIGN(addr, 16);
  324. /* Write floating table */
  325. mc = mp_write_floating_table((struct mp_floating_table *)addr);
  326. /* Write configuration table header */
  327. mp_config_table_init(mc);
  328. /* Write processor entry */
  329. mp_write_processor(mc);
  330. /* Write bus entry */
  331. mp_write_bus(mc, bus_isa, BUSTYPE_ISA);
  332. /* Write I/O APIC entry */
  333. ioapic_id = io_apic_read(IO_APIC_ID) >> 24;
  334. ioapic_ver = io_apic_read(IO_APIC_VER) & 0xff;
  335. mp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
  336. /* Write I/O interrupt assignment entry */
  337. ret = mptable_add_intsrc(mc, bus_isa, ioapic_id);
  338. if (ret)
  339. debug("Failed to write I/O interrupt assignment table\n");
  340. /* Write local interrupt assignment entry */
  341. mptable_add_lintsrc(mc, bus_isa);
  342. /* Finalize the MP table */
  343. end = mptable_finalize(mc);
  344. return end;
  345. }