itss.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Interrupt Timer Subsystem
  4. *
  5. * Copyright (C) 2017 Intel Corporation.
  6. * Copyright (C) 2017 Siemens AG
  7. * Copyright 2019 Google LLC
  8. *
  9. * Taken from coreboot itss.c
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <dt-structs.h>
  14. #include <irq.h>
  15. #include <log.h>
  16. #include <malloc.h>
  17. #include <p2sb.h>
  18. #include <spl.h>
  19. #include <asm/itss.h>
  20. struct itss_plat {
  21. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  22. /* Put this first since driver model will copy the data here */
  23. struct dtd_intel_itss dtplat;
  24. #endif
  25. };
  26. /* struct pmc_route - Routing for PMC to GPIO */
  27. struct pmc_route {
  28. u32 pmc;
  29. u32 gpio;
  30. };
  31. struct itss_priv {
  32. struct pmc_route *route;
  33. uint route_count;
  34. u32 irq_snapshot[NUM_IPC_REGS];
  35. };
  36. static int set_polarity(struct udevice *dev, uint irq, bool active_low)
  37. {
  38. u32 mask;
  39. uint reg;
  40. if (irq > ITSS_MAX_IRQ)
  41. return -EINVAL;
  42. reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * (irq / IRQS_PER_IPC);
  43. mask = 1 << (irq % IRQS_PER_IPC);
  44. pcr_clrsetbits32(dev, reg, mask, active_low ? mask : 0);
  45. return 0;
  46. }
  47. #ifndef CONFIG_TPL_BUILD
  48. static int snapshot_polarities(struct udevice *dev)
  49. {
  50. struct itss_priv *priv = dev_get_priv(dev);
  51. const int start = GPIO_IRQ_START;
  52. const int end = GPIO_IRQ_END;
  53. int reg_start;
  54. int reg_end;
  55. int i;
  56. reg_start = start / IRQS_PER_IPC;
  57. reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
  58. log_debug("ITSS IRQ Polarities snapshot %p\n", priv->irq_snapshot);
  59. for (i = reg_start; i < reg_end; i++) {
  60. uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
  61. priv->irq_snapshot[i] = pcr_read32(dev, reg);
  62. log_debug(" - %d, reg %x: irq_snapshot[i] %x\n", i, reg,
  63. priv->irq_snapshot[i]);
  64. }
  65. /* Save the snapshot for use after relocation */
  66. gd->start_addr_sp -= sizeof(*priv);
  67. gd->start_addr_sp &= ~0xf;
  68. gd->arch.itss_priv = (void *)gd->start_addr_sp;
  69. memcpy(gd->arch.itss_priv, priv, sizeof(*priv));
  70. return 0;
  71. }
  72. static void show_polarities(struct udevice *dev, const char *msg)
  73. {
  74. int i;
  75. log_debug("ITSS IRQ Polarities %s:\n", msg);
  76. for (i = 0; i < NUM_IPC_REGS; i++) {
  77. uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
  78. log_debug("IPC%d: 0x%08x\n", i, pcr_read32(dev, reg));
  79. }
  80. }
  81. static int restore_polarities(struct udevice *dev)
  82. {
  83. struct itss_priv *priv = dev_get_priv(dev);
  84. struct itss_priv *old_priv;
  85. const int start = GPIO_IRQ_START;
  86. const int end = GPIO_IRQ_END;
  87. int reg_start;
  88. int reg_end;
  89. int i;
  90. /* Get the snapshot which was stored by the pre-reloc device */
  91. old_priv = gd->arch.itss_priv;
  92. if (!old_priv)
  93. return log_msg_ret("priv", -EFAULT);
  94. memcpy(priv->irq_snapshot, old_priv->irq_snapshot,
  95. sizeof(priv->irq_snapshot));
  96. show_polarities(dev, "Before");
  97. log_debug("priv->irq_snapshot %p\n", priv->irq_snapshot);
  98. reg_start = start / IRQS_PER_IPC;
  99. reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
  100. for (i = reg_start; i < reg_end; i++) {
  101. u32 mask;
  102. u16 reg;
  103. int irq_start;
  104. int irq_end;
  105. irq_start = i * IRQS_PER_IPC;
  106. irq_end = min(irq_start + IRQS_PER_IPC - 1, ITSS_MAX_IRQ);
  107. if (start > irq_end)
  108. continue;
  109. if (end < irq_start)
  110. break;
  111. /* Track bits within the bounds of of the register */
  112. irq_start = max(start, irq_start) % IRQS_PER_IPC;
  113. irq_end = min(end, irq_end) % IRQS_PER_IPC;
  114. /* Create bitmask of the inclusive range of start and end */
  115. mask = (((1U << irq_end) - 1) | (1U << irq_end));
  116. mask &= ~((1U << irq_start) - 1);
  117. reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
  118. log_debug(" - %d, reg %x: mask %x, irq_snapshot[i] %x\n",
  119. i, reg, mask, priv->irq_snapshot[i]);
  120. pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]);
  121. }
  122. show_polarities(dev, "After");
  123. return 0;
  124. }
  125. #endif
  126. static int route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
  127. {
  128. struct itss_priv *priv = dev_get_priv(dev);
  129. struct pmc_route *route;
  130. int i;
  131. for (i = 0, route = priv->route; i < priv->route_count; i++, route++) {
  132. if (pmc_gpe_num == route->pmc)
  133. return route->gpio;
  134. }
  135. return -ENOENT;
  136. }
  137. static int itss_bind(struct udevice *dev)
  138. {
  139. /* This is not set with of-platdata, so set it manually */
  140. if (CONFIG_IS_ENABLED(OF_PLATDATA))
  141. dev->driver_data = X86_IRQT_ITSS;
  142. return 0;
  143. }
  144. static int itss_of_to_plat(struct udevice *dev)
  145. {
  146. struct itss_priv *priv = dev_get_priv(dev);
  147. int ret;
  148. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  149. struct itss_plat *plat = dev_get_plat(dev);
  150. struct dtd_intel_itss *dtplat = &plat->dtplat;
  151. /*
  152. * It would be nice to do this in the bind() method, but with
  153. * of-platdata binding happens in the order that DM finds things in the
  154. * linker list (i.e. alphabetical order by driver name). So the GPIO
  155. * device may well be bound before its parent (p2sb), and this call
  156. * will fail if p2sb is not bound yet.
  157. *
  158. * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc
  159. */
  160. ret = p2sb_set_port_id(dev, dtplat->intel_p2sb_port_id);
  161. if (ret)
  162. return log_msg_ret("Could not set port id", ret);
  163. priv->route = (struct pmc_route *)dtplat->intel_pmc_routes;
  164. priv->route_count = ARRAY_SIZE(dtplat->intel_pmc_routes) /
  165. sizeof(struct pmc_route);
  166. #else
  167. int size;
  168. size = dev_read_size(dev, "intel,pmc-routes");
  169. if (size < 0)
  170. return size;
  171. priv->route = malloc(size);
  172. if (!priv->route)
  173. return -ENOMEM;
  174. ret = dev_read_u32_array(dev, "intel,pmc-routes", (u32 *)priv->route,
  175. size / sizeof(fdt32_t));
  176. if (ret)
  177. return log_msg_ret("Cannot read pmc-routes", ret);
  178. priv->route_count = size / sizeof(struct pmc_route);
  179. #endif
  180. return 0;
  181. }
  182. static const struct irq_ops itss_ops = {
  183. .route_pmc_gpio_gpe = route_pmc_gpio_gpe,
  184. .set_polarity = set_polarity,
  185. #ifndef CONFIG_TPL_BUILD
  186. .snapshot_polarities = snapshot_polarities,
  187. .restore_polarities = restore_polarities,
  188. #endif
  189. };
  190. static const struct udevice_id itss_ids[] = {
  191. { .compatible = "intel,itss", .data = X86_IRQT_ITSS },
  192. { }
  193. };
  194. U_BOOT_DRIVER(intel_itss) = {
  195. .name = "intel_itss",
  196. .id = UCLASS_IRQ,
  197. .of_match = itss_ids,
  198. .ops = &itss_ops,
  199. .bind = itss_bind,
  200. .of_to_plat = itss_of_to_plat,
  201. .plat_auto = sizeof(struct itss_plat),
  202. .priv_auto = sizeof(struct itss_priv),
  203. };