uart.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Special driver to handle of-platdata
  4. *
  5. * Copyright 2019 Google LLC
  6. *
  7. * Some code from coreboot lpss.c
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <dt-structs.h>
  12. #include <malloc.h>
  13. #include <ns16550.h>
  14. #include <spl.h>
  15. #include <asm/io.h>
  16. #include <asm/pci.h>
  17. #include <asm/lpss.h>
  18. /* Low-power Subsystem (LPSS) clock register */
  19. enum {
  20. LPSS_CLOCK_CTL_REG = 0x200,
  21. LPSS_CNT_CLOCK_EN = 1,
  22. LPSS_CNT_CLK_UPDATE = 1U << 31,
  23. LPSS_CLOCK_DIV_N_SHIFT = 16,
  24. LPSS_CLOCK_DIV_N_MASK = 0x7fff << LPSS_CLOCK_DIV_N_SHIFT,
  25. LPSS_CLOCK_DIV_M_SHIFT = 1,
  26. LPSS_CLOCK_DIV_M_MASK = 0x7fff << LPSS_CLOCK_DIV_M_SHIFT,
  27. /* These set the UART input clock speed */
  28. LPSS_UART_CLK_M_VAL = 0x25a,
  29. LPSS_UART_CLK_N_VAL = 0x7fff,
  30. };
  31. static void lpss_clk_update(void *regs, u32 clk_m_val, u32 clk_n_val)
  32. {
  33. u32 clk_sel;
  34. clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT |
  35. clk_m_val << LPSS_CLOCK_DIV_M_SHIFT;
  36. clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN;
  37. writel(clk_sel, regs + LPSS_CLOCK_CTL_REG);
  38. }
  39. static void uart_lpss_init(void *regs)
  40. {
  41. /* Take UART out of reset */
  42. lpss_reset_release(regs);
  43. /* Set M and N divisor inputs and enable clock */
  44. lpss_clk_update(regs, LPSS_UART_CLK_M_VAL, LPSS_UART_CLK_N_VAL);
  45. }
  46. void apl_uart_init(pci_dev_t bdf, ulong base)
  47. {
  48. /* Set UART base address */
  49. pci_x86_write_config(bdf, PCI_BASE_ADDRESS_0, base, PCI_SIZE_32);
  50. /* Enable memory access and bus master */
  51. pci_x86_write_config(bdf, PCI_COMMAND, PCI_COMMAND_MEMORY |
  52. PCI_COMMAND_MASTER, PCI_SIZE_32);
  53. uart_lpss_init((void *)base);
  54. }
  55. /*
  56. * This driver uses its own compatible string but almost everything else from
  57. * the standard ns16550 driver. This allows us to provide an of-platdata
  58. * implementation, since the platdata produced by of-platdata does not match
  59. * struct ns16550_plat.
  60. *
  61. * When running with of-platdata (generally TPL), the platdata is converted to
  62. * something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
  63. * proper), we use ns16550's of_to_plat routine.
  64. */
  65. static int apl_ns16550_probe(struct udevice *dev)
  66. {
  67. struct ns16550_plat *plat = dev_get_plat(dev);
  68. if (!CONFIG_IS_ENABLED(PCI))
  69. apl_uart_init(plat->bdf, plat->base);
  70. return ns16550_serial_probe(dev);
  71. }
  72. static int apl_ns16550_of_to_plat(struct udevice *dev)
  73. {
  74. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  75. struct dtd_intel_apl_ns16550 *dtplat = dev_get_plat(dev);
  76. struct ns16550_plat *plat;
  77. /*
  78. * Convert our plat to the ns16550's plat, so we can just use
  79. * that driver
  80. */
  81. plat = malloc(sizeof(*plat));
  82. if (!plat)
  83. return -ENOMEM;
  84. plat->base = dtplat->early_regs[0];
  85. plat->reg_width = 1;
  86. plat->reg_shift = dtplat->reg_shift;
  87. plat->reg_offset = 0;
  88. plat->clock = dtplat->clock_frequency;
  89. plat->fcr = UART_FCR_DEFVAL;
  90. plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
  91. dev->plat = plat;
  92. #else
  93. int ret;
  94. ret = ns16550_serial_of_to_plat(dev);
  95. if (ret)
  96. return ret;
  97. #endif /* OF_PLATDATA */
  98. return 0;
  99. }
  100. static const struct udevice_id apl_ns16550_serial_ids[] = {
  101. { .compatible = "intel,apl-ns16550" },
  102. { },
  103. };
  104. U_BOOT_DRIVER(intel_apl_ns16550) = {
  105. .name = "intel_apl_ns16550",
  106. .id = UCLASS_SERIAL,
  107. .of_match = apl_ns16550_serial_ids,
  108. .plat_auto = sizeof(struct ns16550_plat),
  109. .priv_auto = sizeof(struct NS16550),
  110. .ops = &ns16550_serial_ops,
  111. .of_to_plat = apl_ns16550_of_to_plat,
  112. .probe = apl_ns16550_probe,
  113. };