pmc.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017 Intel Corporation.
  4. * Copyright 2019 Google LLC
  5. *
  6. * Modified from coreboot pmclib.c, pmc.c and pmutil.c
  7. */
  8. #define LOG_CATEGORY UCLASS_ACPI_PMC
  9. #include <common.h>
  10. #include <dt-structs.h>
  11. #include <dm.h>
  12. #include <log.h>
  13. #include <spl.h>
  14. #include <acpi/acpi_s3.h>
  15. #include <asm/io.h>
  16. #include <asm/pci.h>
  17. #include <linux/bitops.h>
  18. #include <power/acpi_pmc.h>
  19. #define GPIO_GPE_CFG 0x1050
  20. /* Memory mapped IO registers behind PMC_BASE_ADDRESS */
  21. #define PRSTS 0x1000
  22. #define GEN_PMCON1 0x1020
  23. #define COLD_BOOT_STS BIT(27)
  24. #define COLD_RESET_STS BIT(26)
  25. #define WARM_RESET_STS BIT(25)
  26. #define GLOBAL_RESET_STS BIT(24)
  27. #define SRS BIT(20)
  28. #define MS4V BIT(18)
  29. #define RPS BIT(2)
  30. #define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \
  31. WARM_RESET_STS | GLOBAL_RESET_STS | \
  32. SRS | MS4V)
  33. #define GEN_PMCON2 0x1024
  34. #define GEN_PMCON3 0x1028
  35. /* Offset of TCO registers from ACPI base I/O address */
  36. #define TCO_REG_OFFSET 0x60
  37. #define TCO1_STS 0x64
  38. #define DMISCI_STS BIT(9)
  39. #define BOOT_STS BIT(18)
  40. #define TCO2_STS 0x66
  41. #define TCO1_CNT 0x68
  42. #define TCO_LOCK BIT(12)
  43. #define TCO2_CNT 0x6a
  44. enum {
  45. ETR = 0x1048,
  46. CF9_LOCK = 1UL << 31,
  47. CF9_GLB_RST = 1 << 20,
  48. };
  49. struct apl_pmc_plat {
  50. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  51. struct dtd_intel_apl_pmc dtplat;
  52. #endif
  53. pci_dev_t bdf;
  54. };
  55. static int apl_pmc_fill_power_state(struct udevice *dev)
  56. {
  57. struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
  58. upriv->tco1_sts = inw(upriv->acpi_base + TCO1_STS);
  59. upriv->tco2_sts = inw(upriv->acpi_base + TCO2_STS);
  60. upriv->prsts = readl(upriv->pmc_bar0 + PRSTS);
  61. upriv->gen_pmcon1 = readl(upriv->pmc_bar0 + GEN_PMCON1);
  62. upriv->gen_pmcon2 = readl(upriv->pmc_bar0 + GEN_PMCON2);
  63. upriv->gen_pmcon3 = readl(upriv->pmc_bar0 + GEN_PMCON3);
  64. return 0;
  65. }
  66. static int apl_prev_sleep_state(struct udevice *dev, int prev_sleep_state)
  67. {
  68. struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
  69. /* WAK_STS bit will not be set when waking from G3 state */
  70. if (!(upriv->pm1_sts & WAK_STS) &&
  71. (upriv->gen_pmcon1 & COLD_BOOT_STS))
  72. prev_sleep_state = ACPI_S5;
  73. return prev_sleep_state;
  74. }
  75. static int apl_disable_tco(struct udevice *dev)
  76. {
  77. struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
  78. pmc_disable_tco_base(upriv->acpi_base + TCO_REG_OFFSET);
  79. return 0;
  80. }
  81. static int apl_global_reset_set_enable(struct udevice *dev, bool enable)
  82. {
  83. struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
  84. if (enable)
  85. setbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
  86. else
  87. clrbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
  88. return 0;
  89. }
  90. int apl_pmc_ofdata_to_uc_plat(struct udevice *dev)
  91. {
  92. struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
  93. struct apl_pmc_plat *plat = dev_get_plat(dev);
  94. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  95. u32 base[6];
  96. int size;
  97. int ret;
  98. ret = dev_read_u32_array(dev, "early-regs", base,
  99. ARRAY_SIZE(base));
  100. if (ret)
  101. return log_msg_ret("Missing/short early-regs", ret);
  102. if (spl_phase() == PHASE_TPL) {
  103. upriv->pmc_bar0 = (void *)base[0];
  104. upriv->pmc_bar2 = (void *)base[2];
  105. /* Since PCI is not enabled, we must get the BDF manually */
  106. plat->bdf = pci_get_devfn(dev);
  107. if (plat->bdf < 0)
  108. return log_msg_ret("Cannot get PMC PCI address",
  109. plat->bdf);
  110. }
  111. upriv->acpi_base = base[4];
  112. /* Get the dwX values for pmc gpe settings */
  113. size = dev_read_size(dev, "gpe0-dw");
  114. if (size < 0)
  115. return log_msg_ret("Cannot read gpe0-dm", size);
  116. upriv->gpe0_count = size / sizeof(u32);
  117. ret = dev_read_u32_array(dev, "gpe0-dw", upriv->gpe0_dw,
  118. upriv->gpe0_count);
  119. if (ret)
  120. return log_msg_ret("Bad gpe0-dw", ret);
  121. return pmc_ofdata_to_uc_plat(dev);
  122. #else
  123. struct dtd_intel_apl_pmc *dtplat = &plat->dtplat;
  124. plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
  125. upriv->pmc_bar0 = (void *)dtplat->early_regs[0];
  126. upriv->pmc_bar2 = (void *)dtplat->early_regs[2];
  127. upriv->acpi_base = dtplat->early_regs[4];
  128. upriv->gpe0_dwx_mask = dtplat->gpe0_dwx_mask;
  129. upriv->gpe0_dwx_shift_base = dtplat->gpe0_dwx_shift_base;
  130. upriv->gpe0_sts_reg = dtplat->gpe0_sts;
  131. upriv->gpe0_sts_reg += upriv->acpi_base;
  132. upriv->gpe0_en_reg = dtplat->gpe0_en;
  133. upriv->gpe0_en_reg += upriv->acpi_base;
  134. upriv->gpe0_count = min((int)ARRAY_SIZE(dtplat->gpe0_dw), GPE0_REG_MAX);
  135. memcpy(upriv->gpe0_dw, dtplat->gpe0_dw, sizeof(dtplat->gpe0_dw));
  136. #endif
  137. upriv->gpe_cfg = (u32 *)(upriv->pmc_bar0 + GPIO_GPE_CFG);
  138. return 0;
  139. }
  140. static int enable_pmcbar(struct udevice *dev)
  141. {
  142. struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
  143. struct apl_pmc_plat *priv = dev_get_plat(dev);
  144. pci_dev_t pmc = priv->bdf;
  145. /*
  146. * Set PMC base addresses and enable decoding. BARs 1 and 3 are 64-bit
  147. * BARs.
  148. */
  149. pci_x86_write_config(pmc, PCI_BASE_ADDRESS_0, (ulong)upriv->pmc_bar0,
  150. PCI_SIZE_32);
  151. pci_x86_write_config(pmc, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
  152. pci_x86_write_config(pmc, PCI_BASE_ADDRESS_2, (ulong)upriv->pmc_bar2,
  153. PCI_SIZE_32);
  154. pci_x86_write_config(pmc, PCI_BASE_ADDRESS_3, 0, PCI_SIZE_32);
  155. pci_x86_write_config(pmc, PCI_BASE_ADDRESS_4, upriv->acpi_base,
  156. PCI_SIZE_16);
  157. pci_x86_write_config(pmc, PCI_COMMAND, PCI_COMMAND_IO |
  158. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
  159. PCI_SIZE_16);
  160. return 0;
  161. }
  162. static int apl_pmc_probe(struct udevice *dev)
  163. {
  164. if (spl_phase() == PHASE_TPL) {
  165. return enable_pmcbar(dev);
  166. } else {
  167. struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
  168. upriv->pmc_bar0 = (void *)dm_pci_read_bar32(dev, 0);
  169. upriv->pmc_bar2 = (void *)dm_pci_read_bar32(dev, 2);
  170. }
  171. return 0;
  172. }
  173. static struct acpi_pmc_ops apl_pmc_ops = {
  174. .init = apl_pmc_fill_power_state,
  175. .prev_sleep_state = apl_prev_sleep_state,
  176. .disable_tco = apl_disable_tco,
  177. .global_reset_set_enable = apl_global_reset_set_enable,
  178. };
  179. static const struct udevice_id apl_pmc_ids[] = {
  180. { .compatible = "intel,apl-pmc" },
  181. { }
  182. };
  183. U_BOOT_DRIVER(intel_apl_pmc) = {
  184. .name = "intel_apl_pmc",
  185. .id = UCLASS_ACPI_PMC,
  186. .of_match = apl_pmc_ids,
  187. .of_to_plat = apl_pmc_ofdata_to_uc_plat,
  188. .probe = apl_pmc_probe,
  189. .ops = &apl_pmc_ops,
  190. .plat_auto = sizeof(struct apl_pmc_plat),
  191. };