board.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <ns16550.h>
  12. #include <spl.h>
  13. #include <asm/cache.h>
  14. #include <asm/io.h>
  15. #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
  16. #include <asm/arch/clock.h>
  17. #endif
  18. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  19. #include <asm/arch/funcmux.h>
  20. #endif
  21. #if IS_ENABLED(CONFIG_TEGRA_MC)
  22. #include <asm/arch/mc.h>
  23. #endif
  24. #include <asm/arch/tegra.h>
  25. #include <asm/arch-tegra/ap.h>
  26. #include <asm/arch-tegra/board.h>
  27. #include <asm/arch-tegra/cboot.h>
  28. #include <asm/arch-tegra/pmc.h>
  29. #include <asm/arch-tegra/sys_proto.h>
  30. #include <asm/arch-tegra/warmboot.h>
  31. void save_boot_params_ret(void);
  32. DECLARE_GLOBAL_DATA_PTR;
  33. enum {
  34. /* UARTs which we can enable */
  35. UARTA = 1 << 0,
  36. UARTB = 1 << 1,
  37. UARTC = 1 << 2,
  38. UARTD = 1 << 3,
  39. UARTE = 1 << 4,
  40. UART_COUNT = 5,
  41. };
  42. static bool from_spl __attribute__ ((section(".data")));
  43. #ifndef CONFIG_SPL_BUILD
  44. void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
  45. unsigned long r3)
  46. {
  47. from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
  48. /*
  49. * The logic for this is somewhat indirect. The purpose of the marker
  50. * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
  51. * was loaded from a read-only instance of itself, which is something
  52. * that can happen in secure boot setups. So basically the presence
  53. * of the marker is an indication that U-Boot was loaded by one such
  54. * special variant of U-Boot. Conversely, the absence of the marker
  55. * indicates that this instance of U-Boot was loaded by something
  56. * other than a special U-Boot. This could be SPL, but it could just
  57. * as well be one of any number of other first stage bootloaders.
  58. */
  59. if (from_spl)
  60. cboot_save_boot_params(r0, r1, r2, r3);
  61. save_boot_params_ret();
  62. }
  63. #endif
  64. bool spl_was_boot_source(void)
  65. {
  66. return from_spl;
  67. }
  68. #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  69. #if !defined(CONFIG_TEGRA124)
  70. #error tegra_cpu_is_non_secure has only been validated on Tegra124
  71. #endif
  72. bool tegra_cpu_is_non_secure(void)
  73. {
  74. /*
  75. * This register reads 0xffffffff in non-secure mode. This register
  76. * only implements bits 31:20, so the lower bits will always read 0 in
  77. * secure mode. Thus, the lower bits are an indicator for secure vs.
  78. * non-secure mode.
  79. */
  80. struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  81. uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
  82. return (mc_s_cfg0 & 1) == 1;
  83. }
  84. #endif
  85. #if IS_ENABLED(CONFIG_TEGRA_MC)
  86. /* Read the RAM size directly from the memory controller */
  87. static phys_size_t query_sdram_size(void)
  88. {
  89. struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  90. u32 emem_cfg;
  91. phys_size_t size_bytes;
  92. emem_cfg = readl(&mc->mc_emem_cfg);
  93. #if defined(CONFIG_TEGRA20)
  94. debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
  95. size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
  96. #else
  97. debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
  98. #ifndef CONFIG_PHYS_64BIT
  99. /*
  100. * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
  101. * and will wrap. Clip the reported size to the maximum that a 32-bit
  102. * variable can represent (rounded to a page).
  103. */
  104. if (emem_cfg >= 4096) {
  105. size_bytes = U32_MAX & ~(0x1000 - 1);
  106. } else
  107. #endif
  108. {
  109. /* RAM size EMC is programmed to. */
  110. size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
  111. #ifndef CONFIG_ARM64
  112. /*
  113. * If all RAM fits within 32-bits, it can be accessed without
  114. * LPAE, so go test the RAM size. Otherwise, we can't access
  115. * all the RAM, and get_ram_size() would get confused, so
  116. * avoid using it. There's no reason we should need this
  117. * validation step anyway.
  118. */
  119. if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
  120. size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
  121. size_bytes);
  122. #endif
  123. }
  124. #endif
  125. #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
  126. /* External memory limited to 2047 MB due to IROM/HI-VEC */
  127. if (size_bytes == SZ_2G)
  128. size_bytes -= SZ_1M;
  129. #endif
  130. return size_bytes;
  131. }
  132. #endif
  133. int dram_init(void)
  134. {
  135. int err;
  136. /* try to initialize DRAM from cboot DTB first */
  137. err = cboot_dram_init();
  138. if (err == 0)
  139. return 0;
  140. #if IS_ENABLED(CONFIG_TEGRA_MC)
  141. /* We do not initialise DRAM here. We just query the size */
  142. gd->ram_size = query_sdram_size();
  143. #endif
  144. return 0;
  145. }
  146. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  147. static int uart_configs[] = {
  148. #if defined(CONFIG_TEGRA20)
  149. #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
  150. FUNCMUX_UART1_UAA_UAB,
  151. #elif defined(CONFIG_TEGRA_UARTA_GPU)
  152. FUNCMUX_UART1_GPU,
  153. #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
  154. FUNCMUX_UART1_SDIO1,
  155. #else
  156. FUNCMUX_UART1_IRRX_IRTX,
  157. #endif
  158. FUNCMUX_UART2_UAD,
  159. -1,
  160. FUNCMUX_UART4_GMC,
  161. -1,
  162. #elif defined(CONFIG_TEGRA30)
  163. FUNCMUX_UART1_ULPI, /* UARTA */
  164. -1,
  165. -1,
  166. -1,
  167. -1,
  168. #elif defined(CONFIG_TEGRA114)
  169. -1,
  170. -1,
  171. -1,
  172. FUNCMUX_UART4_GMI, /* UARTD */
  173. -1,
  174. #elif defined(CONFIG_TEGRA124)
  175. FUNCMUX_UART1_KBC, /* UARTA */
  176. -1,
  177. -1,
  178. FUNCMUX_UART4_GPIO, /* UARTD */
  179. -1,
  180. #else /* Tegra210 */
  181. FUNCMUX_UART1_UART1, /* UARTA */
  182. -1,
  183. -1,
  184. FUNCMUX_UART4_UART4, /* UARTD */
  185. -1,
  186. #endif
  187. };
  188. /**
  189. * Set up the specified uarts
  190. *
  191. * @param uarts_ids Mask containing UARTs to init (UARTx)
  192. */
  193. static void setup_uarts(int uart_ids)
  194. {
  195. static enum periph_id id_for_uart[] = {
  196. PERIPH_ID_UART1,
  197. PERIPH_ID_UART2,
  198. PERIPH_ID_UART3,
  199. PERIPH_ID_UART4,
  200. PERIPH_ID_UART5,
  201. };
  202. size_t i;
  203. for (i = 0; i < UART_COUNT; i++) {
  204. if (uart_ids & (1 << i)) {
  205. enum periph_id id = id_for_uart[i];
  206. funcmux_select(id, uart_configs[i]);
  207. clock_ll_start_uart(id);
  208. }
  209. }
  210. }
  211. #endif
  212. void board_init_uart_f(void)
  213. {
  214. #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
  215. int uart_ids = 0; /* bit mask of which UART ids to enable */
  216. #ifdef CONFIG_TEGRA_ENABLE_UARTA
  217. uart_ids |= UARTA;
  218. #endif
  219. #ifdef CONFIG_TEGRA_ENABLE_UARTB
  220. uart_ids |= UARTB;
  221. #endif
  222. #ifdef CONFIG_TEGRA_ENABLE_UARTC
  223. uart_ids |= UARTC;
  224. #endif
  225. #ifdef CONFIG_TEGRA_ENABLE_UARTD
  226. uart_ids |= UARTD;
  227. #endif
  228. #ifdef CONFIG_TEGRA_ENABLE_UARTE
  229. uart_ids |= UARTE;
  230. #endif
  231. setup_uarts(uart_ids);
  232. #endif
  233. }
  234. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  235. static struct ns16550_plat ns16550_com1_pdata = {
  236. .base = CONFIG_SYS_NS16550_COM1,
  237. .reg_shift = 2,
  238. .clock = CONFIG_SYS_NS16550_CLK,
  239. .fcr = UART_FCR_DEFVAL,
  240. };
  241. U_BOOT_DEVICE(ns16550_com1) = {
  242. "ns16550_serial", &ns16550_com1_pdata
  243. };
  244. #endif
  245. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  246. void enable_caches(void)
  247. {
  248. /* Enable D-cache. I-cache is already enabled in start.S */
  249. dcache_enable();
  250. }
  251. #endif