bsec.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <misc.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/bsec.h>
  11. #include <asm/arch/stm32mp1_smc.h>
  12. #include <linux/arm-smccc.h>
  13. #include <linux/iopoll.h>
  14. #define BSEC_OTP_MAX_VALUE 95
  15. #define BSEC_TIMEOUT_US 10000
  16. /* BSEC REGISTER OFFSET (base relative) */
  17. #define BSEC_OTP_CONF_OFF 0x000
  18. #define BSEC_OTP_CTRL_OFF 0x004
  19. #define BSEC_OTP_WRDATA_OFF 0x008
  20. #define BSEC_OTP_STATUS_OFF 0x00C
  21. #define BSEC_OTP_LOCK_OFF 0x010
  22. #define BSEC_DENABLE_OFF 0x014
  23. #define BSEC_DISTURBED_OFF 0x01C
  24. #define BSEC_ERROR_OFF 0x034
  25. #define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */
  26. #define BSEC_SPLOCK_OFF 0x064 /* OTP write sticky lock */
  27. #define BSEC_SWLOCK_OFF 0x07C /* shadow write sticky lock */
  28. #define BSEC_SRLOCK_OFF 0x094 /* shadow read sticky lock */
  29. #define BSEC_OTP_DATA_OFF 0x200
  30. /* BSEC_CONFIGURATION Register MASK */
  31. #define BSEC_CONF_POWER_UP 0x001
  32. /* BSEC_CONTROL Register */
  33. #define BSEC_READ 0x000
  34. #define BSEC_WRITE 0x100
  35. /* LOCK Register */
  36. #define OTP_LOCK_MASK 0x1F
  37. #define OTP_LOCK_BANK_SHIFT 0x05
  38. #define OTP_LOCK_BIT_MASK 0x01
  39. /* STATUS Register */
  40. #define BSEC_MODE_BUSY_MASK 0x08
  41. #define BSEC_MODE_PROGFAIL_MASK 0x10
  42. #define BSEC_MODE_PWR_MASK 0x20
  43. /* DENABLE Register */
  44. #define BSEC_DENABLE_DBGSWENABLE BIT(10)
  45. /*
  46. * OTP Lock services definition
  47. * Value must corresponding to the bit number in the register
  48. */
  49. #define BSEC_LOCK_PROGRAM 0x04
  50. /**
  51. * bsec_lock() - manage lock for each type SR/SP/SW
  52. * @address: address of bsec IP register
  53. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  54. * Return: true if locked else false
  55. */
  56. static bool bsec_read_lock(u32 address, u32 otp)
  57. {
  58. u32 bit;
  59. u32 bank;
  60. bit = 1 << (otp & OTP_LOCK_MASK);
  61. bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
  62. return !!(readl(address + bank) & bit);
  63. }
  64. /**
  65. * bsec_check_error() - Check status of one otp
  66. * @base: base address of bsec IP
  67. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  68. * Return: 0 if no error, -EAGAIN or -ENOTSUPP
  69. */
  70. static u32 bsec_check_error(u32 base, u32 otp)
  71. {
  72. u32 bit;
  73. u32 bank;
  74. bit = 1 << (otp & OTP_LOCK_MASK);
  75. bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
  76. if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
  77. return -EAGAIN;
  78. else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
  79. return -ENOTSUPP;
  80. return 0;
  81. }
  82. /**
  83. * bsec_read_SR_lock() - read SR lock (Shadowing)
  84. * @base: base address of bsec IP
  85. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  86. * Return: true if locked else false
  87. */
  88. static bool bsec_read_SR_lock(u32 base, u32 otp)
  89. {
  90. return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
  91. }
  92. /**
  93. * bsec_read_SP_lock() - read SP lock (program Lock)
  94. * @base: base address of bsec IP
  95. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  96. * Return: true if locked else false
  97. */
  98. static bool bsec_read_SP_lock(u32 base, u32 otp)
  99. {
  100. return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
  101. }
  102. /**
  103. * bsec_SW_lock() - manage SW lock (Write in Shadow)
  104. * @base: base address of bsec IP
  105. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  106. * Return: true if locked else false
  107. */
  108. static bool bsec_read_SW_lock(u32 base, u32 otp)
  109. {
  110. return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
  111. }
  112. /**
  113. * bsec_power_safmem() - Activate or deactivate safmem power
  114. * @base: base address of bsec IP
  115. * @power: true to power up , false to power down
  116. * Return: 0 if succeed
  117. */
  118. static int bsec_power_safmem(u32 base, bool power)
  119. {
  120. u32 val;
  121. u32 mask;
  122. if (power) {
  123. setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
  124. mask = BSEC_MODE_PWR_MASK;
  125. } else {
  126. clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
  127. mask = 0;
  128. }
  129. /* waiting loop */
  130. return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
  131. val, (val & BSEC_MODE_PWR_MASK) == mask,
  132. BSEC_TIMEOUT_US);
  133. }
  134. /**
  135. * bsec_shadow_register() - copy safmen otp to bsec data
  136. * @base: base address of bsec IP
  137. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  138. * Return: 0 if no error
  139. */
  140. static int bsec_shadow_register(u32 base, u32 otp)
  141. {
  142. u32 val;
  143. int ret;
  144. bool power_up = false;
  145. /* check if shadowing of otp is locked */
  146. if (bsec_read_SR_lock(base, otp))
  147. pr_debug("bsec : OTP %d is locked and refreshed with 0\n", otp);
  148. /* check if safemem is power up */
  149. val = readl(base + BSEC_OTP_STATUS_OFF);
  150. if (!(val & BSEC_MODE_PWR_MASK)) {
  151. ret = bsec_power_safmem(base, true);
  152. if (ret)
  153. return ret;
  154. power_up = true;
  155. }
  156. /* set BSEC_OTP_CTRL_OFF with the otp value*/
  157. writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF);
  158. /* check otp status*/
  159. ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
  160. val, (val & BSEC_MODE_BUSY_MASK) == 0,
  161. BSEC_TIMEOUT_US);
  162. if (ret)
  163. return ret;
  164. ret = bsec_check_error(base, otp);
  165. if (power_up)
  166. bsec_power_safmem(base, false);
  167. return ret;
  168. }
  169. /**
  170. * bsec_read_shadow() - read an otp data value from shadow
  171. * @base: base address of bsec IP
  172. * @val: read value
  173. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  174. * Return: 0 if no error
  175. */
  176. static int bsec_read_shadow(u32 base, u32 *val, u32 otp)
  177. {
  178. *val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
  179. return bsec_check_error(base, otp);
  180. }
  181. /**
  182. * bsec_write_shadow() - write value in BSEC data register in shadow
  183. * @base: base address of bsec IP
  184. * @val: value to write
  185. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  186. * Return: 0 if no error
  187. */
  188. static int bsec_write_shadow(u32 base, u32 val, u32 otp)
  189. {
  190. /* check if programming of otp is locked */
  191. if (bsec_read_SW_lock(base, otp))
  192. pr_debug("bsec : OTP %d is lock, write will be ignore\n", otp);
  193. writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
  194. return bsec_check_error(base, otp);
  195. }
  196. /**
  197. * bsec_program_otp() - program a bit in SAFMEM
  198. * @base: base address of bsec IP
  199. * @val: value to program
  200. * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
  201. * after the function the otp data is not refreshed in shadow
  202. * Return: 0 if no error
  203. */
  204. static int bsec_program_otp(long base, u32 val, u32 otp)
  205. {
  206. u32 ret;
  207. bool power_up = false;
  208. if (bsec_read_SP_lock(base, otp))
  209. pr_debug("bsec : OTP %d locked, prog will be ignore\n", otp);
  210. if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
  211. pr_debug("bsec : Global lock, prog will be ignore\n");
  212. /* check if safemem is power up */
  213. if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
  214. ret = bsec_power_safmem(base, true);
  215. if (ret)
  216. return ret;
  217. power_up = true;
  218. }
  219. /* set value in write register*/
  220. writel(val, base + BSEC_OTP_WRDATA_OFF);
  221. /* set BSEC_OTP_CTRL_OFF with the otp value */
  222. writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);
  223. /* check otp status*/
  224. ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
  225. val, (val & BSEC_MODE_BUSY_MASK) == 0,
  226. BSEC_TIMEOUT_US);
  227. if (ret)
  228. return ret;
  229. if (val & BSEC_MODE_PROGFAIL_MASK)
  230. ret = -EACCES;
  231. else
  232. ret = bsec_check_error(base, otp);
  233. if (power_up)
  234. bsec_power_safmem(base, false);
  235. return ret;
  236. }
  237. /* BSEC MISC driver *******************************************************/
  238. struct stm32mp_bsec_plat {
  239. u32 base;
  240. };
  241. static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
  242. {
  243. struct stm32mp_bsec_plat *plat;
  244. u32 tmp_data = 0;
  245. int ret;
  246. if (IS_ENABLED(CONFIG_TFABOOT))
  247. return stm32_smc(STM32_SMC_BSEC,
  248. STM32_SMC_READ_OTP,
  249. otp, 0, val);
  250. plat = dev_get_plat(dev);
  251. /* read current shadow value */
  252. ret = bsec_read_shadow(plat->base, &tmp_data, otp);
  253. if (ret)
  254. return ret;
  255. /* copy otp in shadow */
  256. ret = bsec_shadow_register(plat->base, otp);
  257. if (ret)
  258. return ret;
  259. ret = bsec_read_shadow(plat->base, val, otp);
  260. if (ret)
  261. return ret;
  262. /* restore shadow value */
  263. ret = bsec_write_shadow(plat->base, tmp_data, otp);
  264. return ret;
  265. }
  266. static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
  267. {
  268. struct stm32mp_bsec_plat *plat;
  269. if (IS_ENABLED(CONFIG_TFABOOT))
  270. return stm32_smc(STM32_SMC_BSEC,
  271. STM32_SMC_READ_SHADOW,
  272. otp, 0, val);
  273. plat = dev_get_plat(dev);
  274. return bsec_read_shadow(plat->base, val, otp);
  275. }
  276. static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
  277. {
  278. struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
  279. /* return OTP permanent write lock status */
  280. *val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
  281. return 0;
  282. }
  283. static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
  284. {
  285. struct stm32mp_bsec_plat *plat;
  286. if (IS_ENABLED(CONFIG_TFABOOT))
  287. return stm32_smc_exec(STM32_SMC_BSEC,
  288. STM32_SMC_PROG_OTP,
  289. otp, val);
  290. plat = dev_get_plat(dev);
  291. return bsec_program_otp(plat->base, val, otp);
  292. }
  293. static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
  294. {
  295. struct stm32mp_bsec_plat *plat;
  296. if (IS_ENABLED(CONFIG_TFABOOT))
  297. return stm32_smc_exec(STM32_SMC_BSEC,
  298. STM32_SMC_WRITE_SHADOW,
  299. otp, val);
  300. plat = dev_get_plat(dev);
  301. return bsec_write_shadow(plat->base, val, otp);
  302. }
  303. static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
  304. {
  305. if (!IS_ENABLED(CONFIG_TFABOOT))
  306. return -ENOTSUPP;
  307. if (val == 1)
  308. return stm32_smc_exec(STM32_SMC_BSEC,
  309. STM32_SMC_WRLOCK_OTP,
  310. otp, 0);
  311. if (val == 0)
  312. return 0; /* nothing to do */
  313. return -EINVAL;
  314. }
  315. static int stm32mp_bsec_read(struct udevice *dev, int offset,
  316. void *buf, int size)
  317. {
  318. int ret;
  319. int i;
  320. bool shadow = true, lock = false;
  321. int nb_otp = size / sizeof(u32);
  322. int otp;
  323. unsigned int offs = offset;
  324. if (offs >= STM32_BSEC_LOCK_OFFSET) {
  325. offs -= STM32_BSEC_LOCK_OFFSET;
  326. lock = true;
  327. } else if (offs >= STM32_BSEC_OTP_OFFSET) {
  328. offs -= STM32_BSEC_OTP_OFFSET;
  329. shadow = false;
  330. }
  331. if ((offs % 4) || (size % 4))
  332. return -EINVAL;
  333. otp = offs / sizeof(u32);
  334. for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
  335. u32 *addr = &((u32 *)buf)[i - otp];
  336. if (lock)
  337. ret = stm32mp_bsec_read_lock(dev, addr, i);
  338. else if (shadow)
  339. ret = stm32mp_bsec_read_shadow(dev, addr, i);
  340. else
  341. ret = stm32mp_bsec_read_otp(dev, addr, i);
  342. if (ret)
  343. break;
  344. }
  345. if (ret)
  346. return ret;
  347. else
  348. return (i - otp) * 4;
  349. }
  350. static int stm32mp_bsec_write(struct udevice *dev, int offset,
  351. const void *buf, int size)
  352. {
  353. int ret = 0;
  354. int i;
  355. bool shadow = true, lock = false;
  356. int nb_otp = size / sizeof(u32);
  357. int otp;
  358. unsigned int offs = offset;
  359. if (offs >= STM32_BSEC_LOCK_OFFSET) {
  360. offs -= STM32_BSEC_LOCK_OFFSET;
  361. lock = true;
  362. } else if (offs >= STM32_BSEC_OTP_OFFSET) {
  363. offs -= STM32_BSEC_OTP_OFFSET;
  364. shadow = false;
  365. }
  366. if ((offs % 4) || (size % 4))
  367. return -EINVAL;
  368. otp = offs / sizeof(u32);
  369. for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
  370. u32 *val = &((u32 *)buf)[i - otp];
  371. if (lock)
  372. ret = stm32mp_bsec_write_lock(dev, *val, i);
  373. else if (shadow)
  374. ret = stm32mp_bsec_write_shadow(dev, *val, i);
  375. else
  376. ret = stm32mp_bsec_write_otp(dev, *val, i);
  377. if (ret)
  378. break;
  379. }
  380. if (ret)
  381. return ret;
  382. else
  383. return (i - otp) * 4;
  384. }
  385. static const struct misc_ops stm32mp_bsec_ops = {
  386. .read = stm32mp_bsec_read,
  387. .write = stm32mp_bsec_write,
  388. };
  389. static int stm32mp_bsec_of_to_plat(struct udevice *dev)
  390. {
  391. struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
  392. plat->base = (u32)dev_read_addr_ptr(dev);
  393. return 0;
  394. }
  395. static int stm32mp_bsec_probe(struct udevice *dev)
  396. {
  397. int otp;
  398. struct stm32mp_bsec_plat *plat;
  399. /*
  400. * update unlocked shadow for OTP cleared by the rom code
  401. * only executed in U-Boot proper when TF-A is not used
  402. */
  403. if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
  404. plat = dev_get_plat(dev);
  405. for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
  406. if (!bsec_read_SR_lock(plat->base, otp))
  407. bsec_shadow_register(plat->base, otp);
  408. }
  409. return 0;
  410. }
  411. static const struct udevice_id stm32mp_bsec_ids[] = {
  412. { .compatible = "st,stm32mp15-bsec" },
  413. {}
  414. };
  415. U_BOOT_DRIVER(stm32mp_bsec) = {
  416. .name = "stm32mp_bsec",
  417. .id = UCLASS_MISC,
  418. .of_match = stm32mp_bsec_ids,
  419. .of_to_plat = stm32mp_bsec_of_to_plat,
  420. .plat_auto = sizeof(struct stm32mp_bsec_plat),
  421. .ops = &stm32mp_bsec_ops,
  422. .probe = stm32mp_bsec_probe,
  423. };
  424. bool bsec_dbgswenable(void)
  425. {
  426. struct udevice *dev;
  427. struct stm32mp_bsec_plat *plat;
  428. int ret;
  429. ret = uclass_get_device_by_driver(UCLASS_MISC,
  430. DM_GET_DRIVER(stm32mp_bsec), &dev);
  431. if (ret || !dev) {
  432. pr_debug("bsec driver not available\n");
  433. return false;
  434. }
  435. plat = dev_get_plat(dev);
  436. if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
  437. return true;
  438. return false;
  439. }