devices.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <ns16550.h>
  8. #include <dm/platform_data/lpc32xx_hsuart.h>
  9. #include <asm/arch/clk.h>
  10. #include <asm/arch/uart.h>
  11. #include <asm/arch/mux.h>
  12. #include <asm/io.h>
  13. static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
  14. static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
  15. static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
  16. void lpc32xx_uart_init(unsigned int uart_id)
  17. {
  18. if (uart_id < 1 || uart_id > 7)
  19. return;
  20. /* Disable loopback mode, if it is set by S1L bootloader */
  21. clrbits_le32(&ctrl->loop,
  22. UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
  23. if (uart_id < 3 || uart_id > 6)
  24. return;
  25. /* Enable UART system clock */
  26. setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
  27. /* Set UART into autoclock mode */
  28. clrsetbits_le32(&ctrl->clkmode,
  29. UART_CLKMODE_MASK(uart_id),
  30. UART_CLKMODE_AUTO(uart_id));
  31. /* Bypass pre-divider of UART clock */
  32. writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
  33. &clk->u3clk + (uart_id - 3));
  34. }
  35. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  36. static const struct ns16550_plat lpc32xx_uart[] = {
  37. { .base = UART3_BASE, .reg_shift = 2,
  38. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  39. { .base = UART4_BASE, .reg_shift = 2,
  40. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  41. { .base = UART5_BASE, .reg_shift = 2,
  42. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  43. { .base = UART6_BASE, .reg_shift = 2,
  44. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  45. };
  46. #if defined(CONFIG_LPC32XX_HSUART)
  47. static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
  48. { HS_UART1_BASE, },
  49. { HS_UART2_BASE, },
  50. { HS_UART7_BASE, },
  51. };
  52. #endif
  53. U_BOOT_DEVICES(lpc32xx_uarts) = {
  54. #if defined(CONFIG_LPC32XX_HSUART)
  55. { "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
  56. { "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
  57. #endif
  58. { "ns16550_serial", &lpc32xx_uart[0], },
  59. { "ns16550_serial", &lpc32xx_uart[1], },
  60. { "ns16550_serial", &lpc32xx_uart[2], },
  61. { "ns16550_serial", &lpc32xx_uart[3], },
  62. #if defined(CONFIG_LPC32XX_HSUART)
  63. { "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
  64. #endif
  65. };
  66. #endif
  67. void lpc32xx_dma_init(void)
  68. {
  69. /* Enable DMA interface */
  70. writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
  71. }
  72. void lpc32xx_mac_init(void)
  73. {
  74. /* Enable MAC interface */
  75. writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
  76. #if defined(CONFIG_RMII)
  77. | CLK_MAC_RMII,
  78. #else
  79. | CLK_MAC_MII,
  80. #endif
  81. &clk->macclk_ctrl);
  82. }
  83. void lpc32xx_mlc_nand_init(void)
  84. {
  85. /* Enable NAND interface */
  86. writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
  87. }
  88. void lpc32xx_slc_nand_init(void)
  89. {
  90. /* Enable SLC NAND interface */
  91. writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
  92. }
  93. void lpc32xx_usb_init(void)
  94. {
  95. /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
  96. clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
  97. }
  98. void lpc32xx_i2c_init(unsigned int devnum)
  99. {
  100. /* Enable I2C interface */
  101. uint32_t ctrl = readl(&clk->i2cclk_ctrl);
  102. if (devnum == 1)
  103. ctrl |= CLK_I2C1_ENABLE;
  104. if (devnum == 2)
  105. ctrl |= CLK_I2C2_ENABLE;
  106. writel(ctrl, &clk->i2cclk_ctrl);
  107. }
  108. U_BOOT_DEVICE(lpc32xx_gpios) = {
  109. .name = "gpio_lpc32xx"
  110. };
  111. /* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
  112. #define P_MUX_SET_SSP0 0x1600
  113. void lpc32xx_ssp_init(void)
  114. {
  115. /* Enable SSP0 interface */
  116. writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
  117. /* Mux SSP0 pins */
  118. writel(P_MUX_SET_SSP0, &mux->p_mux_set);
  119. }