at91sam9m10g45_devices.c 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <asm/arch/at91_common.h>
  10. #include <asm/arch/clk.h>
  11. #include <asm/arch/gpio.h>
  12. #include <asm/io.h>
  13. /*
  14. * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
  15. * peripheral pins. Good to have if hardware is soldered optionally
  16. * or in case of SPI no slave is selected. Avoid lines to float
  17. * needlessly. Use a short local PUP define.
  18. *
  19. * Due to errata "TXD floats when CTS is inactive" pullups are always
  20. * on for TXD pins.
  21. */
  22. #ifdef CONFIG_AT91_GPIO_PULLUP
  23. # define PUP CONFIG_AT91_GPIO_PULLUP
  24. #else
  25. # define PUP 0
  26. #endif
  27. void at91_serial0_hw_init(void)
  28. {
  29. at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
  30. at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */
  31. at91_periph_clk_enable(ATMEL_ID_USART0);
  32. }
  33. void at91_serial1_hw_init(void)
  34. {
  35. at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
  36. at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */
  37. at91_periph_clk_enable(ATMEL_ID_USART1);
  38. }
  39. void at91_serial2_hw_init(void)
  40. {
  41. at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
  42. at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */
  43. at91_periph_clk_enable(ATMEL_ID_USART2);
  44. }
  45. void at91_seriald_hw_init(void)
  46. {
  47. at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
  48. at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
  49. at91_periph_clk_enable(ATMEL_ID_SYS);
  50. }
  51. #ifdef CONFIG_ATMEL_SPI
  52. void at91_spi0_hw_init(unsigned long cs_mask)
  53. {
  54. at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */
  55. at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */
  56. at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */
  57. at91_periph_clk_enable(ATMEL_ID_SPI0);
  58. if (cs_mask & (1 << 0)) {
  59. at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
  60. }
  61. if (cs_mask & (1 << 1)) {
  62. at91_set_b_periph(AT91_PIO_PORTB, 18, 1);
  63. }
  64. if (cs_mask & (1 << 2)) {
  65. at91_set_b_periph(AT91_PIO_PORTB, 19, 1);
  66. }
  67. if (cs_mask & (1 << 3)) {
  68. at91_set_b_periph(AT91_PIO_PORTD, 27, 1);
  69. }
  70. if (cs_mask & (1 << 4)) {
  71. at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
  72. }
  73. if (cs_mask & (1 << 5)) {
  74. at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
  75. }
  76. if (cs_mask & (1 << 6)) {
  77. at91_set_pio_output(AT91_PIO_PORTB, 19, 1);
  78. }
  79. if (cs_mask & (1 << 7)) {
  80. at91_set_pio_output(AT91_PIO_PORTD, 27, 1);
  81. }
  82. }
  83. void at91_spi1_hw_init(unsigned long cs_mask)
  84. {
  85. at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */
  86. at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */
  87. at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */
  88. at91_periph_clk_enable(ATMEL_ID_SPI1);
  89. if (cs_mask & (1 << 0)) {
  90. at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
  91. }
  92. if (cs_mask & (1 << 1)) {
  93. at91_set_b_periph(AT91_PIO_PORTD, 28, 1);
  94. }
  95. if (cs_mask & (1 << 2)) {
  96. at91_set_a_periph(AT91_PIO_PORTD, 18, 1);
  97. }
  98. if (cs_mask & (1 << 3)) {
  99. at91_set_a_periph(AT91_PIO_PORTD, 19, 1);
  100. }
  101. if (cs_mask & (1 << 4)) {
  102. at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
  103. }
  104. if (cs_mask & (1 << 5)) {
  105. at91_set_pio_output(AT91_PIO_PORTD, 28, 1);
  106. }
  107. if (cs_mask & (1 << 6)) {
  108. at91_set_pio_output(AT91_PIO_PORTD, 18, 1);
  109. }
  110. if (cs_mask & (1 << 7)) {
  111. at91_set_pio_output(AT91_PIO_PORTD, 19, 1);
  112. }
  113. }
  114. #endif
  115. #ifdef CONFIG_MACB
  116. void at91_macb_hw_init(void)
  117. {
  118. at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */
  119. at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */
  120. at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */
  121. at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */
  122. at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */
  123. at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */
  124. at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */
  125. at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */
  126. at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */
  127. at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */
  128. #ifndef CONFIG_RMII
  129. at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */
  130. at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */
  131. at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */
  132. at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */
  133. at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */
  134. at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */
  135. at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */
  136. at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */
  137. #endif
  138. }
  139. #endif
  140. #ifdef CONFIG_GENERIC_ATMEL_MCI
  141. void at91_mci_hw_init(void)
  142. {
  143. at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */
  144. at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */
  145. at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */
  146. at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */
  147. at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */
  148. at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */
  149. at91_periph_clk_enable(ATMEL_ID_MCI0);
  150. }
  151. #endif
  152. /* Platform data for the GPIOs */
  153. static const struct at91_port_plat at91sam9260_plat[] = {
  154. { ATMEL_BASE_PIOA, "PA" },
  155. { ATMEL_BASE_PIOB, "PB" },
  156. { ATMEL_BASE_PIOC, "PC" },
  157. { ATMEL_BASE_PIOD, "PD" },
  158. { ATMEL_BASE_PIOE, "PE" },
  159. };
  160. U_BOOT_DEVICES(at91sam9260_gpios) = {
  161. { "atmel_at91rm9200_gpio", &at91sam9260_plat[0] },
  162. { "atmel_at91rm9200_gpio", &at91sam9260_plat[1] },
  163. { "atmel_at91rm9200_gpio", &at91sam9260_plat[2] },
  164. { "atmel_at91rm9200_gpio", &at91sam9260_plat[3] },
  165. { "atmel_at91rm9200_gpio", &at91sam9260_plat[4] },
  166. };