sunxi_mmc.c 15 KB

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  1. /*
  2. * (C) Copyright 2007-2011
  3. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  4. * Aaron <leafy.myeh@allwinnertech.com>
  5. *
  6. * MMC driver for allwinner sunxi platform.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <malloc.h>
  14. #include <mmc.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/gpio.h>
  19. #include <asm/arch/mmc.h>
  20. #include <asm-generic/gpio.h>
  21. struct sunxi_mmc_plat {
  22. struct mmc_config cfg;
  23. struct mmc mmc;
  24. };
  25. struct sunxi_mmc_priv {
  26. unsigned mmc_no;
  27. uint32_t *mclkreg;
  28. unsigned fatal_err;
  29. struct gpio_desc cd_gpio; /* Change Detect GPIO */
  30. struct sunxi_mmc *reg;
  31. struct mmc_config cfg;
  32. };
  33. #if !CONFIG_IS_ENABLED(DM_MMC)
  34. /* support 4 mmc hosts */
  35. struct sunxi_mmc_priv mmc_host[4];
  36. static int sunxi_mmc_getcd_gpio(int sdc_no)
  37. {
  38. switch (sdc_no) {
  39. case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  40. case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  41. case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  42. case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  43. }
  44. return -EINVAL;
  45. }
  46. static int mmc_resource_init(int sdc_no)
  47. {
  48. struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  49. struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  50. int cd_pin, ret = 0;
  51. debug("init mmc %d resource\n", sdc_no);
  52. switch (sdc_no) {
  53. case 0:
  54. priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  55. priv->mclkreg = &ccm->sd0_clk_cfg;
  56. break;
  57. case 1:
  58. priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  59. priv->mclkreg = &ccm->sd1_clk_cfg;
  60. break;
  61. case 2:
  62. priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  63. priv->mclkreg = &ccm->sd2_clk_cfg;
  64. break;
  65. case 3:
  66. priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  67. priv->mclkreg = &ccm->sd3_clk_cfg;
  68. break;
  69. default:
  70. printf("Wrong mmc number %d\n", sdc_no);
  71. return -1;
  72. }
  73. priv->mmc_no = sdc_no;
  74. cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  75. if (cd_pin >= 0) {
  76. ret = gpio_request(cd_pin, "mmc_cd");
  77. if (!ret) {
  78. sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
  79. ret = gpio_direction_input(cd_pin);
  80. }
  81. }
  82. return ret;
  83. }
  84. #endif
  85. static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
  86. {
  87. unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
  88. bool new_mode = false;
  89. u32 val = 0;
  90. if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
  91. new_mode = true;
  92. /*
  93. * The MMC clock has an extra /2 post-divider when operating in the new
  94. * mode.
  95. */
  96. if (new_mode)
  97. hz = hz * 2;
  98. if (hz <= 24000000) {
  99. pll = CCM_MMC_CTRL_OSCM24;
  100. pll_hz = 24000000;
  101. } else {
  102. #ifdef CONFIG_MACH_SUN9I
  103. pll = CCM_MMC_CTRL_PLL_PERIPH0;
  104. pll_hz = clock_get_pll4_periph0();
  105. #else
  106. pll = CCM_MMC_CTRL_PLL6;
  107. pll_hz = clock_get_pll6();
  108. #endif
  109. }
  110. div = pll_hz / hz;
  111. if (pll_hz % hz)
  112. div++;
  113. n = 0;
  114. while (div > 16) {
  115. n++;
  116. div = (div + 1) / 2;
  117. }
  118. if (n > 3) {
  119. printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
  120. hz);
  121. return -1;
  122. }
  123. /* determine delays */
  124. if (hz <= 400000) {
  125. oclk_dly = 0;
  126. sclk_dly = 0;
  127. } else if (hz <= 25000000) {
  128. oclk_dly = 0;
  129. sclk_dly = 5;
  130. #ifdef CONFIG_MACH_SUN9I
  131. } else if (hz <= 50000000) {
  132. oclk_dly = 5;
  133. sclk_dly = 4;
  134. } else {
  135. /* hz > 50000000 */
  136. oclk_dly = 2;
  137. sclk_dly = 4;
  138. #else
  139. } else if (hz <= 50000000) {
  140. oclk_dly = 3;
  141. sclk_dly = 4;
  142. } else {
  143. /* hz > 50000000 */
  144. oclk_dly = 1;
  145. sclk_dly = 4;
  146. #endif
  147. }
  148. if (new_mode) {
  149. #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
  150. val = CCM_MMC_CTRL_MODE_SEL_NEW;
  151. setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
  152. #endif
  153. } else {
  154. val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
  155. CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
  156. }
  157. writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
  158. CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
  159. debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
  160. priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
  161. return 0;
  162. }
  163. static int mmc_update_clk(struct sunxi_mmc_priv *priv)
  164. {
  165. unsigned int cmd;
  166. unsigned timeout_msecs = 2000;
  167. cmd = SUNXI_MMC_CMD_START |
  168. SUNXI_MMC_CMD_UPCLK_ONLY |
  169. SUNXI_MMC_CMD_WAIT_PRE_OVER;
  170. writel(cmd, &priv->reg->cmd);
  171. while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
  172. if (!timeout_msecs--)
  173. return -1;
  174. udelay(1000);
  175. }
  176. /* clock update sets various irq status bits, clear these */
  177. writel(readl(&priv->reg->rint), &priv->reg->rint);
  178. return 0;
  179. }
  180. static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
  181. {
  182. unsigned rval = readl(&priv->reg->clkcr);
  183. /* Disable Clock */
  184. rval &= ~SUNXI_MMC_CLK_ENABLE;
  185. writel(rval, &priv->reg->clkcr);
  186. if (mmc_update_clk(priv))
  187. return -1;
  188. /* Set mod_clk to new rate */
  189. if (mmc_set_mod_clk(priv, mmc->clock))
  190. return -1;
  191. /* Clear internal divider */
  192. rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
  193. writel(rval, &priv->reg->clkcr);
  194. /* Re-enable Clock */
  195. rval |= SUNXI_MMC_CLK_ENABLE;
  196. writel(rval, &priv->reg->clkcr);
  197. if (mmc_update_clk(priv))
  198. return -1;
  199. return 0;
  200. }
  201. static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
  202. struct mmc *mmc)
  203. {
  204. debug("set ios: bus_width: %x, clock: %d\n",
  205. mmc->bus_width, mmc->clock);
  206. /* Change clock first */
  207. if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
  208. priv->fatal_err = 1;
  209. return -EINVAL;
  210. }
  211. /* Change bus width */
  212. if (mmc->bus_width == 8)
  213. writel(0x2, &priv->reg->width);
  214. else if (mmc->bus_width == 4)
  215. writel(0x1, &priv->reg->width);
  216. else
  217. writel(0x0, &priv->reg->width);
  218. return 0;
  219. }
  220. #if !CONFIG_IS_ENABLED(DM_MMC)
  221. static int sunxi_mmc_core_init(struct mmc *mmc)
  222. {
  223. struct sunxi_mmc_priv *priv = mmc->priv;
  224. /* Reset controller */
  225. writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
  226. udelay(1000);
  227. return 0;
  228. }
  229. #endif
  230. static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
  231. struct mmc_data *data)
  232. {
  233. const int reading = !!(data->flags & MMC_DATA_READ);
  234. const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
  235. SUNXI_MMC_STATUS_FIFO_FULL;
  236. unsigned i;
  237. unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
  238. unsigned byte_cnt = data->blocksize * data->blocks;
  239. unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
  240. if (timeout_usecs < 2000000)
  241. timeout_usecs = 2000000;
  242. /* Always read / write data through the CPU */
  243. setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
  244. for (i = 0; i < (byte_cnt >> 2); i++) {
  245. while (readl(&priv->reg->status) & status_bit) {
  246. if (!timeout_usecs--)
  247. return -1;
  248. udelay(1);
  249. }
  250. if (reading)
  251. buff[i] = readl(&priv->reg->fifo);
  252. else
  253. writel(buff[i], &priv->reg->fifo);
  254. }
  255. return 0;
  256. }
  257. static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
  258. uint timeout_msecs, uint done_bit, const char *what)
  259. {
  260. unsigned int status;
  261. do {
  262. status = readl(&priv->reg->rint);
  263. if (!timeout_msecs-- ||
  264. (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
  265. debug("%s timeout %x\n", what,
  266. status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
  267. return -ETIMEDOUT;
  268. }
  269. udelay(1000);
  270. } while (!(status & done_bit));
  271. return 0;
  272. }
  273. static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
  274. struct mmc *mmc, struct mmc_cmd *cmd,
  275. struct mmc_data *data)
  276. {
  277. unsigned int cmdval = SUNXI_MMC_CMD_START;
  278. unsigned int timeout_msecs;
  279. int error = 0;
  280. unsigned int status = 0;
  281. unsigned int bytecnt = 0;
  282. if (priv->fatal_err)
  283. return -1;
  284. if (cmd->resp_type & MMC_RSP_BUSY)
  285. debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
  286. if (cmd->cmdidx == 12)
  287. return 0;
  288. if (!cmd->cmdidx)
  289. cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
  290. if (cmd->resp_type & MMC_RSP_PRESENT)
  291. cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
  292. if (cmd->resp_type & MMC_RSP_136)
  293. cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
  294. if (cmd->resp_type & MMC_RSP_CRC)
  295. cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
  296. if (data) {
  297. if ((u32)(long)data->dest & 0x3) {
  298. error = -1;
  299. goto out;
  300. }
  301. cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
  302. if (data->flags & MMC_DATA_WRITE)
  303. cmdval |= SUNXI_MMC_CMD_WRITE;
  304. if (data->blocks > 1)
  305. cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
  306. writel(data->blocksize, &priv->reg->blksz);
  307. writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
  308. }
  309. debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
  310. cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
  311. writel(cmd->cmdarg, &priv->reg->arg);
  312. if (!data)
  313. writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
  314. /*
  315. * transfer data and check status
  316. * STATREG[2] : FIFO empty
  317. * STATREG[3] : FIFO full
  318. */
  319. if (data) {
  320. int ret = 0;
  321. bytecnt = data->blocksize * data->blocks;
  322. debug("trans data %d bytes\n", bytecnt);
  323. writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
  324. ret = mmc_trans_data_by_cpu(priv, mmc, data);
  325. if (ret) {
  326. error = readl(&priv->reg->rint) &
  327. SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
  328. error = -ETIMEDOUT;
  329. goto out;
  330. }
  331. }
  332. error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
  333. "cmd");
  334. if (error)
  335. goto out;
  336. if (data) {
  337. timeout_msecs = 120;
  338. debug("cacl timeout %x msec\n", timeout_msecs);
  339. error = mmc_rint_wait(priv, mmc, timeout_msecs,
  340. data->blocks > 1 ?
  341. SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
  342. SUNXI_MMC_RINT_DATA_OVER,
  343. "data");
  344. if (error)
  345. goto out;
  346. }
  347. if (cmd->resp_type & MMC_RSP_BUSY) {
  348. timeout_msecs = 2000;
  349. do {
  350. status = readl(&priv->reg->status);
  351. if (!timeout_msecs--) {
  352. debug("busy timeout\n");
  353. error = -ETIMEDOUT;
  354. goto out;
  355. }
  356. udelay(1000);
  357. } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
  358. }
  359. if (cmd->resp_type & MMC_RSP_136) {
  360. cmd->response[0] = readl(&priv->reg->resp3);
  361. cmd->response[1] = readl(&priv->reg->resp2);
  362. cmd->response[2] = readl(&priv->reg->resp1);
  363. cmd->response[3] = readl(&priv->reg->resp0);
  364. debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
  365. cmd->response[3], cmd->response[2],
  366. cmd->response[1], cmd->response[0]);
  367. } else {
  368. cmd->response[0] = readl(&priv->reg->resp0);
  369. debug("mmc resp 0x%08x\n", cmd->response[0]);
  370. }
  371. out:
  372. if (error < 0) {
  373. writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
  374. mmc_update_clk(priv);
  375. }
  376. writel(0xffffffff, &priv->reg->rint);
  377. writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
  378. &priv->reg->gctrl);
  379. return error;
  380. }
  381. #if !CONFIG_IS_ENABLED(DM_MMC)
  382. static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
  383. {
  384. struct sunxi_mmc_priv *priv = mmc->priv;
  385. return sunxi_mmc_set_ios_common(priv, mmc);
  386. }
  387. static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
  388. struct mmc_data *data)
  389. {
  390. struct sunxi_mmc_priv *priv = mmc->priv;
  391. return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
  392. }
  393. static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
  394. {
  395. struct sunxi_mmc_priv *priv = mmc->priv;
  396. int cd_pin;
  397. cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
  398. if (cd_pin < 0)
  399. return 1;
  400. return !gpio_get_value(cd_pin);
  401. }
  402. static const struct mmc_ops sunxi_mmc_ops = {
  403. .send_cmd = sunxi_mmc_send_cmd_legacy,
  404. .set_ios = sunxi_mmc_set_ios_legacy,
  405. .init = sunxi_mmc_core_init,
  406. .getcd = sunxi_mmc_getcd_legacy,
  407. };
  408. struct mmc *sunxi_mmc_init(int sdc_no)
  409. {
  410. struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  411. struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  412. struct mmc_config *cfg = &priv->cfg;
  413. int ret;
  414. memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
  415. cfg->name = "SUNXI SD/MMC";
  416. cfg->ops = &sunxi_mmc_ops;
  417. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  418. cfg->host_caps = MMC_MODE_4BIT;
  419. #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
  420. if (sdc_no == 2)
  421. cfg->host_caps = MMC_MODE_8BIT;
  422. #endif
  423. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  424. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  425. cfg->f_min = 400000;
  426. cfg->f_max = 52000000;
  427. if (mmc_resource_init(sdc_no) != 0)
  428. return NULL;
  429. /* config ahb clock */
  430. debug("init mmc %d clock and io\n", sdc_no);
  431. setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
  432. #ifdef CONFIG_SUNXI_GEN_SUN6I
  433. /* unassert reset */
  434. setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
  435. #endif
  436. #if defined(CONFIG_MACH_SUN9I)
  437. /* sun9i has a mmc-common module, also set the gate and reset there */
  438. writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
  439. SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
  440. #endif
  441. ret = mmc_set_mod_clk(priv, 24000000);
  442. if (ret)
  443. return NULL;
  444. return mmc_create(cfg, priv);
  445. }
  446. #else
  447. static int sunxi_mmc_set_ios(struct udevice *dev)
  448. {
  449. struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
  450. struct sunxi_mmc_priv *priv = dev_get_priv(dev);
  451. return sunxi_mmc_set_ios_common(priv, &plat->mmc);
  452. }
  453. static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  454. struct mmc_data *data)
  455. {
  456. struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
  457. struct sunxi_mmc_priv *priv = dev_get_priv(dev);
  458. return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
  459. }
  460. static int sunxi_mmc_getcd(struct udevice *dev)
  461. {
  462. struct sunxi_mmc_priv *priv = dev_get_priv(dev);
  463. if (dm_gpio_is_valid(&priv->cd_gpio))
  464. return dm_gpio_get_value(&priv->cd_gpio);
  465. return 1;
  466. }
  467. static const struct dm_mmc_ops sunxi_mmc_ops = {
  468. .send_cmd = sunxi_mmc_send_cmd,
  469. .set_ios = sunxi_mmc_set_ios,
  470. .get_cd = sunxi_mmc_getcd,
  471. };
  472. static int sunxi_mmc_probe(struct udevice *dev)
  473. {
  474. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  475. struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
  476. struct sunxi_mmc_priv *priv = dev_get_priv(dev);
  477. struct mmc_config *cfg = &plat->cfg;
  478. struct ofnode_phandle_args args;
  479. u32 *gate_reg;
  480. int bus_width, ret;
  481. cfg->name = dev->name;
  482. bus_width = dev_read_u32_default(dev, "bus-width", 1);
  483. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  484. cfg->host_caps = 0;
  485. if (bus_width == 8)
  486. cfg->host_caps |= MMC_MODE_8BIT;
  487. if (bus_width >= 4)
  488. cfg->host_caps |= MMC_MODE_4BIT;
  489. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  490. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  491. cfg->f_min = 400000;
  492. cfg->f_max = 52000000;
  493. priv->reg = (void *)dev_read_addr(dev);
  494. /* We don't have a sunxi clock driver so find the clock address here */
  495. ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
  496. 1, &args);
  497. if (ret)
  498. return ret;
  499. priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
  500. ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
  501. 0, &args);
  502. if (ret)
  503. return ret;
  504. gate_reg = (u32 *)ofnode_get_addr(args.node);
  505. setbits_le32(gate_reg, 1 << args.args[0]);
  506. priv->mmc_no = args.args[0] - 8;
  507. ret = mmc_set_mod_clk(priv, 24000000);
  508. if (ret)
  509. return ret;
  510. /* This GPIO is optional */
  511. if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  512. GPIOD_IS_IN)) {
  513. int cd_pin = gpio_get_number(&priv->cd_gpio);
  514. sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
  515. }
  516. upriv->mmc = &plat->mmc;
  517. /* Reset controller */
  518. writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
  519. udelay(1000);
  520. return 0;
  521. }
  522. static int sunxi_mmc_bind(struct udevice *dev)
  523. {
  524. struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
  525. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  526. }
  527. static const struct udevice_id sunxi_mmc_ids[] = {
  528. { .compatible = "allwinner,sun5i-a13-mmc" },
  529. { }
  530. };
  531. U_BOOT_DRIVER(sunxi_mmc_drv) = {
  532. .name = "sunxi_mmc",
  533. .id = UCLASS_MMC,
  534. .of_match = sunxi_mmc_ids,
  535. .bind = sunxi_mmc_bind,
  536. .probe = sunxi_mmc_probe,
  537. .ops = &sunxi_mmc_ops,
  538. .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
  539. .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),
  540. };
  541. #endif