Kconfig 9.3 KB

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  1. menu "RISC-V architecture"
  2. depends on RISCV
  3. config SYS_ARCH
  4. default "riscv"
  5. choice
  6. prompt "Target select"
  7. optional
  8. config TARGET_AX25_AE350
  9. bool "Support ax25-ae350"
  10. config TARGET_MICROCHIP_ICICLE
  11. bool "Support Microchip PolarFire-SoC Icicle Board"
  12. config TARGET_QEMU_VIRT
  13. bool "Support QEMU Virt Board"
  14. config TARGET_SIFIVE_UNLEASHED
  15. bool "Support SiFive Unleashed Board"
  16. config TARGET_SIFIVE_UNMATCHED
  17. bool "Support SiFive Unmatched Board"
  18. config TARGET_SIPEED_MAIX
  19. bool "Support Sipeed Maix Board"
  20. config TARGET_OPENPITON_RISCV64
  21. bool "Support RISC-V cores on OpenPiton SoC"
  22. endchoice
  23. config SYS_ICACHE_OFF
  24. bool "Do not enable icache"
  25. default n
  26. help
  27. Do not enable instruction cache in U-Boot.
  28. config SPL_SYS_ICACHE_OFF
  29. bool "Do not enable icache in SPL"
  30. depends on SPL
  31. default SYS_ICACHE_OFF
  32. help
  33. Do not enable instruction cache in SPL.
  34. config SYS_DCACHE_OFF
  35. bool "Do not enable dcache"
  36. default n
  37. help
  38. Do not enable data cache in U-Boot.
  39. config SPL_SYS_DCACHE_OFF
  40. bool "Do not enable dcache in SPL"
  41. depends on SPL
  42. default SYS_DCACHE_OFF
  43. help
  44. Do not enable data cache in SPL.
  45. # board-specific options below
  46. source "board/AndesTech/ax25-ae350/Kconfig"
  47. source "board/emulation/qemu-riscv/Kconfig"
  48. source "board/microchip/mpfs_icicle/Kconfig"
  49. source "board/sifive/unleashed/Kconfig"
  50. source "board/sifive/unmatched/Kconfig"
  51. source "board/openpiton/riscv64/Kconfig"
  52. source "board/sipeed/maix/Kconfig"
  53. # platform-specific options below
  54. source "arch/riscv/cpu/ax25/Kconfig"
  55. source "arch/riscv/cpu/fu540/Kconfig"
  56. source "arch/riscv/cpu/fu740/Kconfig"
  57. source "arch/riscv/cpu/generic/Kconfig"
  58. # architecture-specific options below
  59. choice
  60. prompt "Base ISA"
  61. default ARCH_RV32I
  62. config ARCH_RV32I
  63. bool "RV32I"
  64. select 32BIT
  65. help
  66. Choose this option to target the RV32I base integer instruction set.
  67. config ARCH_RV64I
  68. bool "RV64I"
  69. select 64BIT
  70. select PHYS_64BIT
  71. help
  72. Choose this option to target the RV64I base integer instruction set.
  73. endchoice
  74. choice
  75. prompt "Code Model"
  76. default CMODEL_MEDLOW
  77. config CMODEL_MEDLOW
  78. bool "medium low code model"
  79. help
  80. U-Boot and its statically defined symbols must lie within a single 2 GiB
  81. address range and must lie between absolute addresses -2 GiB and +2 GiB.
  82. config CMODEL_MEDANY
  83. bool "medium any code model"
  84. help
  85. U-Boot and its statically defined symbols must be within any single 2 GiB
  86. address range.
  87. endchoice
  88. choice
  89. prompt "Run Mode"
  90. default RISCV_MMODE
  91. config RISCV_MMODE
  92. bool "Machine"
  93. help
  94. Choose this option to build U-Boot for RISC-V M-Mode.
  95. config RISCV_SMODE
  96. bool "Supervisor"
  97. help
  98. Choose this option to build U-Boot for RISC-V S-Mode.
  99. endchoice
  100. choice
  101. prompt "SPL Run Mode"
  102. default SPL_RISCV_MMODE
  103. depends on SPL
  104. config SPL_RISCV_MMODE
  105. bool "Machine"
  106. help
  107. Choose this option to build U-Boot SPL for RISC-V M-Mode.
  108. config SPL_RISCV_SMODE
  109. bool "Supervisor"
  110. help
  111. Choose this option to build U-Boot SPL for RISC-V S-Mode.
  112. endchoice
  113. config RISCV_ISA_C
  114. bool "Emit compressed instructions"
  115. default y
  116. help
  117. Adds "C" to the ISA subsets that the toolchain is allowed to emit
  118. when building U-Boot, which results in compressed instructions in the
  119. U-Boot binary.
  120. config RISCV_ISA_A
  121. def_bool y
  122. config 32BIT
  123. bool
  124. config 64BIT
  125. bool
  126. config DMA_ADDR_T_64BIT
  127. bool
  128. default y if 64BIT
  129. config SIFIVE_CLINT
  130. bool
  131. depends on RISCV_MMODE
  132. help
  133. The SiFive CLINT block holds memory-mapped control and status registers
  134. associated with software and timer interrupts.
  135. config SPL_SIFIVE_CLINT
  136. bool
  137. depends on SPL_RISCV_MMODE
  138. help
  139. The SiFive CLINT block holds memory-mapped control and status registers
  140. associated with software and timer interrupts.
  141. config ANDES_PLIC
  142. bool
  143. depends on RISCV_MMODE || SPL_RISCV_MMODE
  144. select REGMAP
  145. select SYSCON
  146. select SPL_REGMAP if SPL
  147. select SPL_SYSCON if SPL
  148. help
  149. The Andes PLIC block holds memory-mapped claim and pending registers
  150. associated with software interrupt.
  151. config SYS_MALLOC_F_LEN
  152. default 0x1000
  153. config SMP
  154. bool "Symmetric Multi-Processing"
  155. depends on SBI_V01 || !RISCV_SMODE
  156. help
  157. This enables support for systems with more than one CPU. If
  158. you say N here, U-Boot will run on single and multiprocessor
  159. machines, but will use only one CPU of a multiprocessor
  160. machine. If you say Y here, U-Boot will run on many, but not
  161. all, single processor machines.
  162. config SPL_SMP
  163. bool "Symmetric Multi-Processing in SPL"
  164. depends on SPL && SPL_RISCV_MMODE
  165. default y
  166. help
  167. This enables support for systems with more than one CPU in SPL.
  168. If you say N here, U-Boot SPL will run on single and multiprocessor
  169. machines, but will use only one CPU of a multiprocessor
  170. machine. If you say Y here, U-Boot SPL will run on many, but not
  171. all, single processor machines.
  172. config NR_CPUS
  173. int "Maximum number of CPUs (2-32)"
  174. range 2 32
  175. depends on SMP || SPL_SMP
  176. default 8
  177. help
  178. On multiprocessor machines, U-Boot sets up a stack for each CPU.
  179. Stack memory is pre-allocated. U-Boot must therefore know the
  180. maximum number of CPUs that may be present.
  181. config SBI
  182. bool
  183. default y if RISCV_SMODE || SPL_RISCV_SMODE
  184. choice
  185. prompt "SBI support"
  186. default SBI_V02
  187. config SBI_V01
  188. bool "SBI v0.1 support"
  189. depends on SBI
  190. help
  191. This config allows kernel to use SBI v0.1 APIs. This will be
  192. deprecated in future once legacy M-mode software are no longer in use.
  193. config SBI_V02
  194. bool "SBI v0.2 support"
  195. depends on SBI
  196. help
  197. This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
  198. scalable and extendable to handle future needs for RISC-V supervisor
  199. interfaces. For example, with SBI v0.2 HSM extension, only a single
  200. hart need to boot and enter operating system. The booting hart can
  201. bring up secondary harts one by one afterwards.
  202. Choose this option if OpenSBI v0.7 or above release is used together
  203. with U-Boot.
  204. endchoice
  205. config SBI_IPI
  206. bool
  207. depends on SBI
  208. default y if RISCV_SMODE || SPL_RISCV_SMODE
  209. depends on SMP
  210. config XIP
  211. bool "XIP mode"
  212. help
  213. XIP (eXecute In Place) is a method for executing code directly
  214. from a NOR flash memory without copying the code to ram.
  215. Say yes here if U-Boot boots from flash directly.
  216. config SHOW_REGS
  217. bool "Show registers on unhandled exception"
  218. config RISCV_PRIV_1_9
  219. bool "Use version 1.9 of the RISC-V priviledged specification"
  220. help
  221. Older versions of the RISC-V priviledged specification had
  222. separate counter enable CSRs for each privilege mode. Writing
  223. to the unified mcounteren CSR on a processor implementing the
  224. old specification will result in an illegal instruction
  225. exception. In addition to counter CSR changes, the way virtual
  226. memory is configured was also changed.
  227. config STACK_SIZE_SHIFT
  228. int
  229. default 14
  230. config OF_BOARD_FIXUP
  231. default y if OF_SEPARATE && RISCV_SMODE
  232. menu "Use assembly optimized implementation of memory routines"
  233. config USE_ARCH_MEMCPY
  234. bool "Use an assembly optimized implementation of memcpy"
  235. default y
  236. help
  237. Enable the generation of an optimized version of memcpy.
  238. Such an implementation may be faster under some conditions
  239. but may increase the binary size.
  240. config SPL_USE_ARCH_MEMCPY
  241. bool "Use an assembly optimized implementation of memcpy for SPL"
  242. default y if USE_ARCH_MEMCPY
  243. depends on SPL
  244. help
  245. Enable the generation of an optimized version of memcpy.
  246. Such an implementation may be faster under some conditions
  247. but may increase the binary size.
  248. config TPL_USE_ARCH_MEMCPY
  249. bool "Use an assembly optimized implementation of memcpy for TPL"
  250. default y if USE_ARCH_MEMCPY
  251. depends on TPL
  252. help
  253. Enable the generation of an optimized version of memcpy.
  254. Such an implementation may be faster under some conditions
  255. but may increase the binary size.
  256. config USE_ARCH_MEMMOVE
  257. bool "Use an assembly optimized implementation of memmove"
  258. default y
  259. help
  260. Enable the generation of an optimized version of memmove.
  261. Such an implementation may be faster under some conditions
  262. but may increase the binary size.
  263. config SPL_USE_ARCH_MEMMOVE
  264. bool "Use an assembly optimized implementation of memmove for SPL"
  265. default y if USE_ARCH_MEMCPY
  266. depends on SPL
  267. help
  268. Enable the generation of an optimized version of memmove.
  269. Such an implementation may be faster under some conditions
  270. but may increase the binary size.
  271. config TPL_USE_ARCH_MEMMOVE
  272. bool "Use an assembly optimized implementation of memmove for TPL"
  273. default y if USE_ARCH_MEMCPY
  274. depends on TPL
  275. help
  276. Enable the generation of an optimized version of memmove.
  277. Such an implementation may be faster under some conditions
  278. but may increase the binary size.
  279. config USE_ARCH_MEMSET
  280. bool "Use an assembly optimized implementation of memset"
  281. default y
  282. help
  283. Enable the generation of an optimized version of memset.
  284. Such an implementation may be faster under some conditions
  285. but may increase the binary size.
  286. config SPL_USE_ARCH_MEMSET
  287. bool "Use an assembly optimized implementation of memset for SPL"
  288. default y if USE_ARCH_MEMSET
  289. depends on SPL
  290. help
  291. Enable the generation of an optimized version of memset.
  292. Such an implementation may be faster under some conditions
  293. but may increase the binary size.
  294. config TPL_USE_ARCH_MEMSET
  295. bool "Use an assembly optimized implementation of memset for TPL"
  296. default y if USE_ARCH_MEMSET
  297. depends on TPL
  298. help
  299. Enable the generation of an optimized version of memset.
  300. Such an implementation may be faster under some conditions
  301. but may increase the binary size.
  302. endmenu
  303. endmenu