ocotea.h 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312
  1. /*
  2. * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
  3. *
  4. * (C) Copyright 2005
  5. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /************************************************************************
  26. * 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com>
  27. * Adapted to current Das U-Boot source
  28. ***********************************************************************/
  29. /************************************************************************
  30. * OCOTEA.h - configuration for IBM 440GX Ref (Ocotea)
  31. ***********************************************************************/
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. /*-----------------------------------------------------------------------
  35. * High Level Configuration Options
  36. *----------------------------------------------------------------------*/
  37. #define CONFIG_OCOTEA 1 /* Board is ebony */
  38. #define CONFIG_440_GX 1 /* Specifc GX support */
  39. #define CONFIG_4xx 1 /* ... PPC4xx family */
  40. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  41. #undef CFG_DRAM_TEST /* Disable-takes long time! */
  42. #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
  43. /*-----------------------------------------------------------------------
  44. * Base addresses -- Note these are effective addresses where the
  45. * actual resources get mapped (not physical addresses)
  46. *----------------------------------------------------------------------*/
  47. #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
  48. #define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
  49. #define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
  50. #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
  51. #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
  52. #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
  53. #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
  54. #define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
  55. #define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
  56. /*-----------------------------------------------------------------------
  57. * Initial RAM & stack pointer (placed in internal SRAM)
  58. *----------------------------------------------------------------------*/
  59. #define CFG_TEMP_STACK_OCM 1
  60. #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
  61. #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
  62. #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
  63. #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
  64. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  65. #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
  66. #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
  67. #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  68. #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
  69. /*-----------------------------------------------------------------------
  70. * Serial Port
  71. *----------------------------------------------------------------------*/
  72. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  73. #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
  74. #define CONFIG_BAUDRATE 115200
  75. #define CFG_BAUDRATE_TABLE \
  76. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  77. /*-----------------------------------------------------------------------
  78. * Environment
  79. *----------------------------------------------------------------------*/
  80. /*
  81. * Define here the location of the environment variables (FLASH or NVRAM).
  82. * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
  83. * supported for backward compatibility.
  84. */
  85. #if 1
  86. #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  87. #else
  88. #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
  89. #endif
  90. /*-----------------------------------------------------------------------
  91. * NVRAM/RTC
  92. *
  93. * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
  94. * The DS1743 code assumes this condition (i.e. -- it assumes the base
  95. * address for the RTC registers is:
  96. *
  97. * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
  98. *
  99. *----------------------------------------------------------------------*/
  100. #define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
  101. #define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
  102. #ifdef CFG_ENV_IS_IN_NVRAM
  103. #define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
  104. #define CFG_ENV_ADDR \
  105. (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
  106. #endif /* CFG_ENV_IS_IN_NVRAM */
  107. /*-----------------------------------------------------------------------
  108. * FLASH related
  109. *----------------------------------------------------------------------*/
  110. #define CFG_MAX_FLASH_BANKS 3 /* number of banks */
  111. #define CFG_MAX_FLASH_SECT 64 /* sectors per device */
  112. #undef CFG_FLASH_CHECKSUM
  113. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  114. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  115. #define CFG_FLASH_ADDR0 0x5555
  116. #define CFG_FLASH_ADDR1 0x2aaa
  117. #define CFG_FLASH_WORD_SIZE unsigned char
  118. #ifdef CFG_ENV_IS_IN_FLASH
  119. #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
  120. #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
  121. #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  122. /* Address and size of Redundant Environment Sector */
  123. #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
  124. #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  125. #endif /* CFG_ENV_IS_IN_FLASH */
  126. /*-----------------------------------------------------------------------
  127. * DDR SDRAM
  128. *----------------------------------------------------------------------*/
  129. #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
  130. #define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
  131. /*-----------------------------------------------------------------------
  132. * I2C
  133. *----------------------------------------------------------------------*/
  134. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  135. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  136. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  137. #define CFG_I2C_SLAVE 0x7F
  138. #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  139. #define CONFIG_PREBOOT "echo;" \
  140. "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  141. "echo"
  142. #undef CONFIG_BOOTARGS
  143. #define CONFIG_EXTRA_ENV_SETTINGS \
  144. "netdev=eth0\0" \
  145. "hostname=ocotea\0" \
  146. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  147. "nfsroot=$(serverip):$(rootpath)\0" \
  148. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  149. "addip=setenv bootargs $(bootargs) " \
  150. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  151. ":$(hostname):$(netdev):off panic=1\0" \
  152. "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
  153. "flash_nfs=run nfsargs addip addtty;" \
  154. "bootm $(kernel_addr)\0" \
  155. "flash_self=run ramargs addip addtty;" \
  156. "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  157. "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
  158. "bootm\0" \
  159. "rootpath=/opt/eldk/ppc_4xx\0" \
  160. "bootfile=/tftpboot/ocotea/uImage\0" \
  161. "kernel_addr=fff00000\0" \
  162. "ramdisk_addr=fff10000\0" \
  163. "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \
  164. "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
  165. "cp.b 100000 fffc0000 40000;" \
  166. "setenv filesize;saveenv\0" \
  167. "upd=run load;run update\0" \
  168. ""
  169. #define CONFIG_BOOTCOMMAND "run flash_self"
  170. #if 0
  171. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  172. #else
  173. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  174. #endif
  175. #define CONFIG_BAUDRATE 115200
  176. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  177. #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  178. #define CONFIG_MII 1 /* MII PHY management */
  179. #define CONFIG_NET_MULTI 1
  180. #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
  181. #define CONFIG_PHY1_ADDR 2
  182. #define CONFIG_PHY2_ADDR 0x10
  183. #define CONFIG_PHY3_ADDR 0x18
  184. #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
  185. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  186. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
  187. CFG_CMD_ASKENV | \
  188. CFG_CMD_DATE | \
  189. CFG_CMD_DHCP | \
  190. CFG_CMD_DIAG | \
  191. CFG_CMD_ELF | \
  192. CFG_CMD_I2C | \
  193. CFG_CMD_IRQ | \
  194. CFG_CMD_MII | \
  195. CFG_CMD_NET | \
  196. CFG_CMD_NFS | \
  197. CFG_CMD_PCI | \
  198. CFG_CMD_PING | \
  199. CFG_CMD_REGINFO | \
  200. CFG_CMD_SDRAM | \
  201. CFG_CMD_SNTP )
  202. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  203. #include <cmd_confdefs.h>
  204. #undef CONFIG_WATCHDOG /* watchdog disabled */
  205. /*
  206. * Miscellaneous configurable options
  207. */
  208. #define CFG_LONGHELP /* undef to save memory */
  209. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  210. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  211. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  212. #else
  213. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  214. #endif
  215. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  216. #define CFG_MAXARGS 16 /* max number of command args */
  217. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  218. #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  219. #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  220. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  221. #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  222. #define CFG_HZ 100 /* decrementer freq: 1 ms ticks */
  223. #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
  224. #define CONFIG_LOOPW 1 /* enable loopw command */
  225. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  226. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  227. #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
  228. /*-----------------------------------------------------------------------
  229. * PCI stuff
  230. *-----------------------------------------------------------------------
  231. */
  232. /* General PCI */
  233. #define CONFIG_PCI /* include pci support */
  234. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  235. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  236. #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
  237. /* Board-specific PCI */
  238. #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
  239. #define CFG_PCI_TARGET_INIT /* let board init pci target */
  240. #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
  241. #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
  242. /*
  243. * For booting Linux, the board info and command line data
  244. * have to be in the first 8 MB of memory, since this is
  245. * the maximum mapped by the Linux kernel during initialization.
  246. */
  247. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  248. /*-----------------------------------------------------------------------
  249. * Cache Configuration
  250. */
  251. #define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
  252. #define CFG_CACHELINE_SIZE 32 /* ... */
  253. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  254. #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  255. #endif
  256. /*
  257. * Internal Definitions
  258. *
  259. * Boot Flags
  260. */
  261. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  262. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  263. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  264. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  265. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  266. #endif
  267. #endif /* __CONFIG_H */