ocotea.c 18 KB

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  1. /*
  2. * Copyright (C) 2004 PaulReynolds@lhsolutions.com
  3. *
  4. * (C) Copyright 2005
  5. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include "ocotea.h"
  27. #include <asm/processor.h>
  28. #include <spd_sdram.h>
  29. #include <440gx_enet.h>
  30. #define BOOT_SMALL_FLASH 32 /* 00100000 */
  31. #define FLASH_ONBD_N 2 /* 00000010 */
  32. #define FLASH_SRAM_SEL 1 /* 00000001 */
  33. long int fixed_sdram (void);
  34. void fpga_init (void);
  35. int board_early_init_f (void)
  36. {
  37. unsigned long mfr;
  38. unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
  39. unsigned char switch_status;
  40. unsigned long cs0_base;
  41. unsigned long cs0_size;
  42. unsigned long cs0_twt;
  43. unsigned long cs2_base;
  44. unsigned long cs2_size;
  45. unsigned long cs2_twt;
  46. /*-------------------------------------------------------------------------+
  47. | Initialize EBC CONFIG
  48. +-------------------------------------------------------------------------*/
  49. mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
  50. EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
  51. EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
  52. EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
  53. EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
  54. /*-------------------------------------------------------------------------+
  55. | FPGA. Initialize bank 7 with default values.
  56. +-------------------------------------------------------------------------*/
  57. mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
  58. EBC_BXAP_BCE_DISABLE|
  59. EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  60. EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  61. EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  62. EBC_BXAP_BEM_WRITEONLY|
  63. EBC_BXAP_PEN_DISABLED);
  64. mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
  65. EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
  66. /* read FPGA base register FPGA_REG0 */
  67. switch_status = *fpga_base;
  68. if (switch_status & 0x40) {
  69. cs0_base = 0xFFE00000;
  70. cs0_size = EBC_BXCR_BS_2MB;
  71. cs0_twt = 8;
  72. cs2_base = 0xFF800000;
  73. cs2_size = EBC_BXCR_BS_4MB;
  74. cs2_twt = 10;
  75. } else {
  76. cs0_base = 0xFFC00000;
  77. cs0_size = EBC_BXCR_BS_4MB;
  78. cs0_twt = 10;
  79. cs2_base = 0xFF800000;
  80. cs2_size = EBC_BXCR_BS_2MB;
  81. cs2_twt = 8;
  82. }
  83. /*-------------------------------------------------------------------------+
  84. | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
  85. +-------------------------------------------------------------------------*/
  86. mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
  87. EBC_BXAP_BCE_DISABLE|
  88. EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  89. EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  90. EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  91. EBC_BXAP_BEM_WRITEONLY|
  92. EBC_BXAP_PEN_DISABLED);
  93. mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
  94. cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
  95. /*-------------------------------------------------------------------------+
  96. | 8KB NVRAM/RTC. Initialize bank 1 with default values.
  97. +-------------------------------------------------------------------------*/
  98. mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
  99. EBC_BXAP_BCE_DISABLE|
  100. EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  101. EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  102. EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  103. EBC_BXAP_BEM_WRITEONLY|
  104. EBC_BXAP_PEN_DISABLED);
  105. mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
  106. EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
  107. /*-------------------------------------------------------------------------+
  108. | 4 MB FLASH. Initialize bank 2 with default values.
  109. +-------------------------------------------------------------------------*/
  110. mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
  111. EBC_BXAP_BCE_DISABLE|
  112. EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  113. EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  114. EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  115. EBC_BXAP_BEM_WRITEONLY|
  116. EBC_BXAP_PEN_DISABLED);
  117. mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
  118. cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
  119. /*-------------------------------------------------------------------------+
  120. | FPGA. Initialize bank 7 with default values.
  121. +-------------------------------------------------------------------------*/
  122. mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
  123. EBC_BXAP_BCE_DISABLE|
  124. EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  125. EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  126. EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  127. EBC_BXAP_BEM_WRITEONLY|
  128. EBC_BXAP_PEN_DISABLED);
  129. mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
  130. EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
  131. /*--------------------------------------------------------------------
  132. * Setup the interrupt controller polarities, triggers, etc.
  133. *-------------------------------------------------------------------*/
  134. mtdcr (uic0sr, 0xffffffff); /* clear all */
  135. mtdcr (uic0er, 0x00000000); /* disable all */
  136. mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
  137. mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
  138. mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
  139. mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
  140. mtdcr (uic0sr, 0xffffffff); /* clear all */
  141. mtdcr (uic1sr, 0xffffffff); /* clear all */
  142. mtdcr (uic1er, 0x00000000); /* disable all */
  143. mtdcr (uic1cr, 0x00000000); /* all non-critical */
  144. mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
  145. mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
  146. mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
  147. mtdcr (uic1sr, 0xffffffff); /* clear all */
  148. mtdcr (uic2sr, 0xffffffff); /* clear all */
  149. mtdcr (uic2er, 0x00000000); /* disable all */
  150. mtdcr (uic2cr, 0x00000000); /* all non-critical */
  151. mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
  152. mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
  153. mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
  154. mtdcr (uic2sr, 0xffffffff); /* clear all */
  155. mtdcr (uicb0sr, 0xfc000000); /* clear all */
  156. mtdcr (uicb0er, 0x00000000); /* disable all */
  157. mtdcr (uicb0cr, 0x00000000); /* all non-critical */
  158. mtdcr (uicb0pr, 0xfc000000); /* */
  159. mtdcr (uicb0tr, 0x00000000); /* */
  160. mtdcr (uicb0vr, 0x00000001); /* */
  161. mfsdr (sdr_mfr, mfr);
  162. mfr &= ~SDR0_MFR_ECS_MASK;
  163. /* mtsdr(sdr_mfr, mfr); */
  164. fpga_init();
  165. return 0;
  166. }
  167. int checkboard (void)
  168. {
  169. sys_info_t sysinfo;
  170. unsigned char *s = getenv ("serial#");
  171. get_sys_info (&sysinfo);
  172. printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
  173. if (s != NULL) {
  174. puts (", serial# ");
  175. puts (s);
  176. }
  177. putc ('\n');
  178. printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
  179. printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
  180. printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
  181. printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
  182. printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
  183. return (0);
  184. }
  185. long int initdram (int board_type)
  186. {
  187. long dram_size = 0;
  188. #if defined(CONFIG_SPD_EEPROM)
  189. dram_size = spd_sdram (0);
  190. #else
  191. dram_size = fixed_sdram ();
  192. #endif
  193. return dram_size;
  194. }
  195. #if defined(CFG_DRAM_TEST)
  196. int testdram (void)
  197. {
  198. uint *pstart = (uint *) 0x00000000;
  199. uint *pend = (uint *) 0x08000000;
  200. uint *p;
  201. for (p = pstart; p < pend; p++)
  202. *p = 0xaaaaaaaa;
  203. for (p = pstart; p < pend; p++) {
  204. if (*p != 0xaaaaaaaa) {
  205. printf ("SDRAM test fails at: %08x\n", (uint) p);
  206. return 1;
  207. }
  208. }
  209. for (p = pstart; p < pend; p++)
  210. *p = 0x55555555;
  211. for (p = pstart; p < pend; p++) {
  212. if (*p != 0x55555555) {
  213. printf ("SDRAM test fails at: %08x\n", (uint) p);
  214. return 1;
  215. }
  216. }
  217. return 0;
  218. }
  219. #endif
  220. #if !defined(CONFIG_SPD_EEPROM)
  221. /*************************************************************************
  222. * fixed sdram init -- doesn't use serial presence detect.
  223. *
  224. * Assumes: 128 MB, non-ECC, non-registered
  225. * PLB @ 133 MHz
  226. *
  227. ************************************************************************/
  228. long int fixed_sdram (void)
  229. {
  230. uint reg;
  231. /*--------------------------------------------------------------------
  232. * Setup some default
  233. *------------------------------------------------------------------*/
  234. mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
  235. mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
  236. mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
  237. mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
  238. mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
  239. /*--------------------------------------------------------------------
  240. * Setup for board-specific specific mem
  241. *------------------------------------------------------------------*/
  242. /*
  243. * Following for CAS Latency = 2.5 @ 133 MHz PLB
  244. */
  245. mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
  246. mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
  247. /* RA=10 RD=3 */
  248. mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
  249. mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
  250. mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
  251. udelay (400); /* Delay 200 usecs (min) */
  252. /*--------------------------------------------------------------------
  253. * Enable the controller, then wait for DCEN to complete
  254. *------------------------------------------------------------------*/
  255. mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
  256. for (;;) {
  257. mfsdram (mem_mcsts, reg);
  258. if (reg & 0x80000000)
  259. break;
  260. }
  261. return (128 * 1024 * 1024); /* 128 MB */
  262. }
  263. #endif /* !defined(CONFIG_SPD_EEPROM) */
  264. /*************************************************************************
  265. * pci_pre_init
  266. *
  267. * This routine is called just prior to registering the hose and gives
  268. * the board the opportunity to check things. Returning a value of zero
  269. * indicates that things are bad & PCI initialization should be aborted.
  270. *
  271. * Different boards may wish to customize the pci controller structure
  272. * (add regions, override default access routines, etc) or perform
  273. * certain pre-initialization actions.
  274. *
  275. ************************************************************************/
  276. #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
  277. int pci_pre_init(struct pci_controller * hose )
  278. {
  279. unsigned long strap;
  280. /*--------------------------------------------------------------------------+
  281. * The ocotea board is always configured as the host & requires the
  282. * PCI arbiter to be enabled.
  283. *--------------------------------------------------------------------------*/
  284. mfsdr(sdr_sdstp1, strap);
  285. if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
  286. printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
  287. return 0;
  288. }
  289. return 1;
  290. }
  291. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
  292. /*************************************************************************
  293. * pci_target_init
  294. *
  295. * The bootstrap configuration provides default settings for the pci
  296. * inbound map (PIM). But the bootstrap config choices are limited and
  297. * may not be sufficient for a given board.
  298. *
  299. ************************************************************************/
  300. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  301. void pci_target_init(struct pci_controller * hose )
  302. {
  303. DECLARE_GLOBAL_DATA_PTR;
  304. /*--------------------------------------------------------------------------+
  305. * Disable everything
  306. *--------------------------------------------------------------------------*/
  307. out32r( PCIX0_PIM0SA, 0 ); /* disable */
  308. out32r( PCIX0_PIM1SA, 0 ); /* disable */
  309. out32r( PCIX0_PIM2SA, 0 ); /* disable */
  310. out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
  311. /*--------------------------------------------------------------------------+
  312. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
  313. * options to not support sizes such as 128/256 MB.
  314. *--------------------------------------------------------------------------*/
  315. out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
  316. out32r( PCIX0_PIM0LAH, 0 );
  317. out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
  318. out32r( PCIX0_BAR0, 0 );
  319. /*--------------------------------------------------------------------------+
  320. * Program the board's subsystem id/vendor id
  321. *--------------------------------------------------------------------------*/
  322. out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
  323. out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
  324. out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
  325. }
  326. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  327. /*************************************************************************
  328. * is_pci_host
  329. *
  330. * This routine is called to determine if a pci scan should be
  331. * performed. With various hardware environments (especially cPCI and
  332. * PPMC) it's insufficient to depend on the state of the arbiter enable
  333. * bit in the strap register, or generic host/adapter assumptions.
  334. *
  335. * Rather than hard-code a bad assumption in the general 440 code, the
  336. * 440 pci code requires the board to decide at runtime.
  337. *
  338. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  339. *
  340. *
  341. ************************************************************************/
  342. #if defined(CONFIG_PCI)
  343. int is_pci_host(struct pci_controller *hose)
  344. {
  345. /* The ocotea board is always configured as host. */
  346. return(1);
  347. }
  348. #endif /* defined(CONFIG_PCI) */
  349. void fpga_init(void)
  350. {
  351. unsigned long group;
  352. unsigned long sdr0_pfc0;
  353. unsigned long sdr0_pfc1;
  354. unsigned long sdr0_cust0;
  355. unsigned long pvr;
  356. mfsdr (sdr_pfc0, sdr0_pfc0);
  357. mfsdr (sdr_pfc1, sdr0_pfc1);
  358. group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
  359. pvr = get_pvr ();
  360. sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
  361. if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
  362. sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
  363. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
  364. out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
  365. FPGA_REG2_EXT_INTFACE_ENABLE);
  366. mtsdr (sdr_pfc0, sdr0_pfc0);
  367. mtsdr (sdr_pfc1, sdr0_pfc1);
  368. } else {
  369. sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
  370. switch (group)
  371. {
  372. case 0:
  373. case 1:
  374. case 2:
  375. /* CPU trace A */
  376. out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
  377. FPGA_REG2_EXT_INTFACE_ENABLE);
  378. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
  379. mtsdr (sdr_pfc0, sdr0_pfc0);
  380. mtsdr (sdr_pfc1, sdr0_pfc1);
  381. break;
  382. case 3:
  383. case 4:
  384. case 5:
  385. case 6:
  386. /* CPU trace B - Over EBMI */
  387. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
  388. mtsdr (sdr_pfc0, sdr0_pfc0);
  389. mtsdr (sdr_pfc1, sdr0_pfc1);
  390. out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
  391. FPGA_REG2_EXT_INTFACE_DISABLE);
  392. break;
  393. }
  394. }
  395. /* Initialize the ethernet specific functions in the fpga */
  396. mfsdr(sdr_pfc1, sdr0_pfc1);
  397. mfsdr(sdr_cust0, sdr0_cust0);
  398. if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
  399. ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
  400. (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
  401. {
  402. if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
  403. {
  404. out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
  405. FPGA_REG3_ENET_GROUP7);
  406. }
  407. else
  408. {
  409. if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
  410. {
  411. out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
  412. FPGA_REG3_ENET_GROUP7);
  413. }
  414. else
  415. {
  416. out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
  417. FPGA_REG3_ENET_GROUP8);
  418. }
  419. }
  420. }
  421. else
  422. {
  423. if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
  424. {
  425. out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
  426. FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
  427. }
  428. else
  429. {
  430. out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
  431. FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
  432. }
  433. }
  434. out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
  435. FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
  436. FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
  437. /* reset the gigabyte phy if necessary */
  438. if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
  439. {
  440. if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
  441. {
  442. out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
  443. udelay(10000);
  444. out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
  445. }
  446. else
  447. {
  448. out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
  449. udelay(10000);
  450. out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
  451. }
  452. }
  453. /* Turn off the LED's */
  454. out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
  455. FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
  456. FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
  457. return;
  458. }
  459. #ifdef CONFIG_POST
  460. /*
  461. * Returns 1 if keys pressed to start the power-on long-running tests
  462. * Called from board_init_f().
  463. */
  464. int post_hotkeys_pressed(void)
  465. {
  466. return (ctrlc());
  467. }
  468. #endif