init.S 3.1 KB

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  1. /*
  2. * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <ppc_asm.tmpl>
  23. #include <config.h>
  24. /* General */
  25. #define TLB_VALID 0x00000200
  26. /* Supported page sizes */
  27. #define SZ_1K 0x00000000
  28. #define SZ_4K 0x00000010
  29. #define SZ_16K 0x00000020
  30. #define SZ_64K 0x00000030
  31. #define SZ_256K 0x00000040
  32. #define SZ_1M 0x00000050
  33. #define SZ_16M 0x00000070
  34. #define SZ_256M 0x00000090
  35. /* Storage attributes */
  36. #define SA_W 0x00000800 /* Write-through */
  37. #define SA_I 0x00000400 /* Caching inhibited */
  38. #define SA_M 0x00000200 /* Memory coherence */
  39. #define SA_G 0x00000100 /* Guarded */
  40. #define SA_E 0x00000080 /* Endian */
  41. /* Access control */
  42. #define AC_X 0x00000024 /* Execute */
  43. #define AC_W 0x00000012 /* Write */
  44. #define AC_R 0x00000009 /* Read */
  45. /* Some handy macros */
  46. #define EPN(e) ((e) & 0xfffffc00)
  47. #define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
  48. #define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
  49. #define TLB2(a) ( (a)&0x00000fbf )
  50. #define tlbtab_start\
  51. mflr r1 ;\
  52. bl 0f ;
  53. #define tlbtab_end\
  54. .long 0, 0, 0 ; \
  55. 0: mflr r0 ; \
  56. mtlr r1 ; \
  57. blr ;
  58. #define tlbentry(epn,sz,rpn,erpn,attr)\
  59. .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
  60. /**************************************************************************
  61. * TLB TABLE
  62. *
  63. * This table is used by the cpu boot code to setup the initial tlb
  64. * entries. Rather than make broad assumptions in the cpu source tree,
  65. * this table lets each board set things up however they like.
  66. *
  67. * Pointer to the table is returned in r1
  68. *
  69. *************************************************************************/
  70. .section .bootpg,"ax"
  71. .globl tlbtab
  72. tlbtab:
  73. tlbtab_start
  74. tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
  75. tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
  76. tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
  77. tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
  78. tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
  79. tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
  80. tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
  81. tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
  82. tlbtab_end